2023-03-20 11:32:29 +08:00
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//
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// MNNGelu.S
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// MNN
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//
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// Created by MNN on 2023/2/27.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __arm__
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#ifndef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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asm_function MNNGelu
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//void MNNGelu(float* dst, const float* src, size_t size, float* parameters);
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//Auto Load:
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//r0:dst, r1:src, r2:size, r3: *parameters
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push {r4-r8, r10, r11, lr}
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vpush {q4-q7}
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cmp r2, #0
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beq GeluEnd
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ldr lr, [r3, #0]
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ldr r4, [r3, #4] // r4: 0.79788458f
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ldr r5, [r3, #8] // r5: 378.f
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ldr r6, [r3, #12] // r6: 17325.f
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ldr r7, [r3, #16] // r7: 135135.f
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ldr r8, [r3, #20] // r8: 28.f
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ldr r10, [r3, #24] // r10: 3150.f
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ldr r11, [r3, #28] // r11: 62370.f
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vdup.32 q15, lr //q15: [0.044715f]x4
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vdup.32 q14, r4 //q16: [0.79788458f]x4
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vdup.32 q13, r5 //q13: [378.f]x4
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vdup.32 q12, r6 //q12: [17325.f]x4
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vdup.32 q11, r7 //q11: [135135.f]x4
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vdup.32 q10, r8 //q10: [28.f]x4
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vdup.32 q9, r10 //q9: [3150.f]x4
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vdup.32 q8, r11 //q8: [62370.f]x4
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2023-12-27 17:26:44 +08:00
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mov r4, #5
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mov r5, #-5
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2023-12-04 11:12:20 +08:00
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2023-03-20 11:32:29 +08:00
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GeluZLoop:
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vld1.32 {q0, q1}, [r1]! // q0, q1: fp32x4
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vmul.f32 q2, q0, q0
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vmul.f32 q3, q1, q1
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vmul.f32 q2, q2, q0
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vmul.f32 q3, q3, q1
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vmul.f32 q2, q2, q15
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vadd.f32 q2, q2, q0
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vmul.f32 q3, q3, q15
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vadd.f32 q3, q3, q1
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2023-10-18 10:31:02 +08:00
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vmul.f32 q2, q2, q14 // value
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vmul.f32 q3, q3, q14 // value
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// if value > 5, then value=5; if value<-5, then value=-5
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2023-12-04 11:12:20 +08:00
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vdup.32 q7, r4
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vdup.32 q6, r5
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2023-12-27 17:26:44 +08:00
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vcvt.f32.s32 q7, q7
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vcvt.f32.s32 q6, q6
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2023-10-18 10:31:02 +08:00
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vmax.f32 q2, q2, q6
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vmax.f32 q3, q3, q6
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vmin.f32 q2, q2, q7
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vmin.f32 q3, q3, q7
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2023-03-20 11:32:29 +08:00
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// tanh(value)
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vmul.f32 q4, q2, q2 // q4: value*value
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vmul.f32 q5, q3, q3 // q5: value*value
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// a
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vadd.f32 q6, q4, q13
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vadd.f32 q7, q5, q13
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vmul.f32 q6, q6, q4
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vmul.f32 q7, q7, q5
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vadd.f32 q6, q6, q12
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vadd.f32 q7, q7, q12
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vmul.f32 q6, q6, q4
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vmul.f32 q7, q7, q5
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vadd.f32 q6, q6, q11
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vadd.f32 q7, q7, q11
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vmul.f32 q6, q6, q2
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vmul.f32 q7, q7, q3
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//b
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vmul.f32 q2, q4, q10
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vmul.f32 q3, q5, q10
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vadd.f32 q2, q2, q9
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vadd.f32 q3, q3, q9
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vmul.f32 q2, q2, q4
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vmul.f32 q3, q3, q5
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vadd.f32 q2, q2, q8
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vadd.f32 q3, q3, q8
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vmul.f32 q2, q2, q4
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vmul.f32 q3, q3, q5
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vadd.f32 q2, q2, q11
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vadd.f32 q3, q3, q11
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//a/b
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vdiv.f32 s24, s24, s8
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vdiv.f32 s25, s25, s9
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vdiv.f32 s26, s26, s10
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vdiv.f32 s27, s27, s11
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vdiv.f32 s28, s28, s12
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vdiv.f32 s29, s29, s13
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vdiv.f32 s30, s30, s14
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vdiv.f32 s31, s31, s15
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// border case
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vmov.f32 q2, #1.0
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vmov.f32 q3, #-1.0
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vmov.f32 q4, #0.5
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vmin.f32 q6, q6, q2
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vmin.f32 q7, q7, q2
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vmax.f32 q6, q6, q3
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vmax.f32 q7, q7, q3
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// tanh(value)
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vadd.f32 q6, q6, q2
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vadd.f32 q7, q7, q2
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vmul.f32 q6, q6, q0
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vmul.f32 q7, q7, q1
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vmul.f32 q6, q6, q4
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vmul.f32 q7, q7, q4
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vst1.32 {q6, q7}, [r0]!
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subs r2, r2, #1
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bne GeluZLoop
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GeluEnd:
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vpop {q4-q7}
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pop {r4-r8, r10, r11, pc}
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#endif
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#endif
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