2021-04-08 15:34:23 +08:00
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#if defined(__ANDROID__) || defined(__aarch64__)
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2021-06-24 11:53:13 +08:00
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#include <math.h>
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2022-01-29 18:03:25 +08:00
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#include <float.h>
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2021-04-08 15:34:23 +08:00
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#include "Arm82Functions.hpp"
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#include "Arm82OptFunc.hpp"
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#include "Arm82WinogradOptFunc.hpp"
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#include "Arm82Vec.hpp"
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2021-06-11 17:17:13 +08:00
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#include "Arm82Binary.hpp"
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#include "Arm82Unary.hpp"
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#include "Arm82Relu.hpp"
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2021-04-08 15:34:23 +08:00
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#include "backend/cpu/compute/CommonOptFunction.h"
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2021-06-11 17:17:13 +08:00
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#include "backend/cpu/CPUPool.hpp"
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2023-12-04 11:12:20 +08:00
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#include "backend/cpu/CPURuntime.hpp"
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#define FLOAT FLOAT16
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#define PACK 8
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using Vec = MNN::Math::Vec<FLOAT16, 8>;
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#include "backend/cpu/GridSampler.hpp"
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2021-04-08 15:34:23 +08:00
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#if defined(MNN_USE_NEON)
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#include <arm_neon.h>
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#endif
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extern "C" {
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// (UP_DIV(l,8), e, 8) -> (UP_DIV(e,eP), l, eP)
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void Arm82MNNPackForMatMul_A(float* destOrigin, float const** sourceGroup, const int32_t* info, const int32_t* el);
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// C(UP_DIV(h,8), e, h8) = B(UP_DIV(h,hP), l, hP) * A(l, eP), hP = 24
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// parameter: [aStride, l, h, cStride, bExtraStride]
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// aStride in parameter is deprecated (useless), but for code clean, just retain it
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void MNNPackedMatMulFP16(float* C, const float* A, const float* B, const size_t* parameter, const float* postParameters, const float* bias);
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// C(UP_DIV(h,8), e, h8) = B(UP_DIV(h,hP), l, hP) * A(l, e), hP = 24, e >= 1
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// parameter: [aStride, l, h, cStride, bExtraStride]
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2023-06-27 10:33:16 +08:00
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void MNNPackedMatMulRemainFP16(float* C, const float* A, const float* B, size_t eSize, const size_t* parameter, const float* postParameters, const float* bias, const float* k, const float* b);
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2024-09-12 12:57:57 +08:00
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#ifdef MNN_CPU_WEIGHT_DEQUANT_GEMM
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2023-06-27 10:33:16 +08:00
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void MNNPackedMatMulFP16_int4(float* C, const float* A, const float* B, const size_t* parameter, const float* postParameters, const float* bias, const float* k, const float* b);
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void MNNPackedMatMulRemainFP16_int4(float* C, const float* A, const float* B, size_t eSize, const size_t* parameter, const float* postParameters, const float* bias, const float* k, const float* b);
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void MNNPackedMatMulFP16_int8(float* C, const float* A, const float* B, const size_t* parameter, const float* postParameters, const float* bias, const float* k, const float* b);
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void MNNPackedMatMulRemainFP16_int8(float* C, const float* A, const float* B, size_t eSize, const size_t* parameter, const float* postParameters, const float* bias, const float* k, const float* b);
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2024-09-12 12:57:57 +08:00
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#endif
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2023-12-04 11:12:20 +08:00
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2024-09-12 12:57:57 +08:00
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#ifdef MNN_LOW_MEMORY
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2023-12-04 11:12:20 +08:00
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void MNNAbsMaxFP16(const float* source, float* absmax, size_t src_depth_quad, size_t realSize, int pack);
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void MNNQuantScaleFP16(float* sum, float* absmax, float* quant_scale, float* dequant_scale, size_t thread, size_t batch);
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void MNNDynamicQuantFP16(const float* src, int8_t* dst, const float* scale, size_t src_depth_quad, size_t realSize, int pack);
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void MNNQuantSumFP16(float* sum, const float* dequant_scale, size_t thread, size_t batch);
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2023-12-11 18:01:44 +08:00
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#endif
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2024-07-22 19:51:53 +08:00
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#if defined(__aarch64__)
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void CountMinMaxValue_FP16(float* source, float* minVal, float* maxVal, size_t sizeQuad);
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2024-10-14 19:26:28 +08:00
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void MNNDepthwiseConvFastKernelFP16(float* dst, const float* src, const float* weight, size_t width, size_t src_w_setup,
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size_t fw, size_t fh, size_t dilateX_step, size_t dilateY_step, size_t height,
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size_t srcHStep, size_t dstHStep, const float* bias, const float* parameters);
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2023-06-27 10:33:16 +08:00
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#endif
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2021-04-08 15:34:23 +08:00
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void MNNConvRunForLineDepthwiseFP16(float* dst, const float* src, const float* weight, size_t width, size_t src_w_setup,
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size_t fw, size_t fh, size_t dilateX_step, size_t dilateY_step, size_t height, size_t srcHStep, size_t dstHStep);
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}
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namespace MNN {
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static void MNNMatrixAddFP16(FLOAT16* C, const FLOAT16* A, const FLOAT16* B, size_t widthC8, size_t cStride, size_t aStride, size_t bStride, size_t height) {
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for (int y = 0; y < height; ++y) {
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auto a = A + aStride * y, b = B + bStride * y;
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auto c = C + cStride * y;
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for (int x = 0; x < widthC8; ++x) {
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vst1q_f16(c + x * 8, vaddq_f16(vld1q_f16(a + x * 8), vld1q_f16(b + x * 8)));
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}
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}
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}
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static void MNNMatrixSubFP16(FLOAT16* C, const FLOAT16* A, const FLOAT16* B, size_t widthC8, size_t cStride, size_t aStride, size_t bStride, size_t height) {
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for (int y = 0; y < height; ++y) {
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auto a = A + aStride * y, b = B + bStride * y;
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auto c = C + cStride * y;
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for (int x = 0; x < widthC8; ++x) {
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vst1q_f16(c + x * 8, vsubq_f16(vld1q_f16(a + x * 8), vld1q_f16(b + x * 8)));
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}
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}
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}
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2024-07-22 19:51:53 +08:00
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#if defined(__aarch64__)
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static void ARM82CountMinMaxValue(float* source, float* minVal, float* maxVal, size_t size) {
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if (size % 8 == 0) {
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CountMinMaxValue_FP16(source, minVal, maxVal, size / 8);
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} else {
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auto remain = size - 8 * (size / 8);
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auto max_ = ((__fp16*)source)[0];
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auto min_ = max_;
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if (size >= 8) {
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CountMinMaxValue_FP16(source, minVal, maxVal, size / 8);
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max_ = ((__fp16*)maxVal)[0];
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min_ = ((__fp16*)minVal)[0];
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}
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if (remain > 0) {
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int16_t tmp[8] = {0};
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auto srcRemain = reinterpret_cast<uint8_t*>(source) + 8 * (size / 8) * 2;
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::memcpy(tmp, srcRemain, remain * 2);
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CountMinMaxValue_FP16((float*)tmp, (float*)tmp, (float*)((uint8_t*)tmp + 2), 1);
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max_ = ALIMAX(((__fp16*)tmp)[1], max_);
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min_ = ALIMIN(((__fp16*)tmp)[0], min_);
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}
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reinterpret_cast<__fp16*>(minVal)[0] = min_;
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reinterpret_cast<__fp16*>(maxVal)[0] = max_;
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}
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}
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#endif
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2021-04-08 15:34:23 +08:00
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static void Arm82MNNPackForMatMul_B(float* destC, const float* sourceC, size_t h, size_t l, bool transpose) {
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auto dest = (int16_t*)destC;
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auto source = (int16_t*)sourceC;
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int ePack, lPack, hPack;
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Arm82MNNGetMatMulPackMode(&ePack, &lPack, &hPack);
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auto hP = (int)h / hPack;
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auto hR = (int)hP * hPack;
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if (hR != h) {
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::memset(dest, 0, UP_DIV(h, hPack) * hPack * l * sizeof(FLOAT16));
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}
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if (!transpose) {
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for (int y = 0; y < hP; ++y) {
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auto destY = dest + y * hPack * l;
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auto sourceY = source + y * hPack;
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for (int x = 0; x < l; ++x) {
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::memcpy(destY + hPack * x, sourceY + x * h, hPack * sizeof(FLOAT16));
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}
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}
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auto hRemain = h - hR;
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if (hRemain > 0) {
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auto destY = dest + hP * hPack * l;
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auto sourceY = source + hP * hPack;
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for (int x = 0; x < l; ++x) {
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::memcpy(destY + hPack * x, sourceY + x * h, hRemain * sizeof(FLOAT16));
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}
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}
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return;
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}
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for (int y = 0; y < h; ++y) {
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for (int x = 0; x < l; ++x) {
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dest[(y / hPack * l + x) * hPack + y % hPack] = source[y * l + x];
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}
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}
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}
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static void MNNScaleAndAddBiasFP16(FLOAT16* dst, const FLOAT16* src, const FLOAT16* bias, const FLOAT16* alpha, size_t planeNumber,
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size_t biasNumber) {
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for (int z = 0; z < biasNumber; ++z) {
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FLOAT16* dstZ = dst + planeNumber * 8 * z;
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const FLOAT16* srcZ = src + planeNumber * 8 * z;
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auto biasZ = vld1q_f16(bias + 8 * z), alphaZ = vld1q_f16(alpha + 8 * z);
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for (int p = 0; p < planeNumber; ++p) {
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FLOAT16* dstX = dstZ + 8 * p;
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const FLOAT16* srcX = srcZ + 8 * p;
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auto res = vaddq_f16(vmulq_f16(vld1q_f16(srcX), alphaZ), biasZ);
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vst1q_f16(dstX, res);
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}
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}
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}
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2021-06-23 14:10:31 +08:00
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static void MNNGridSampleComputeCordFP16(FLOAT16* dst, const FLOAT16* src, size_t inH, size_t inW, size_t outH, size_t outW, size_t stride, bool alignCorners) {
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float16x8_t zero = vdupq_n_f16(0);
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float16x8_t one = vdupq_n_f16(1);
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float16x8_t half = vdupq_n_f16(0.5f);
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float16x8_t a = alignCorners ? one : zero;
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float16x8_t b = alignCorners ? zero : one;
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float16x8_t inW_sub_a = vsubq_f16(vdupq_n_f16(inW), a);
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float16x8_t inH_sub_a = vsubq_f16(vdupq_n_f16(inH), a);
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int area = outH * outW;
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int areaC8 = area / 8;
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int areaRemain = area - areaC8 * 8;
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for (int i = 0; i < areaC8; ++i) {
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auto cordH = vld2q_f16(src);
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// float16x8_t x = cordH.val[0];
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// float16x8_t y = cordH.val[1];
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cordH.val[0] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[0]), inW_sub_a), b));
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cordH.val[1] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[1]), inH_sub_a), b));
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vst2q_f16(dst, cordH);
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src += 16;
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dst += 16;
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}
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2022-10-12 17:23:26 +08:00
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if (areaRemain == 0) {
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return;
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}
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2021-06-23 14:10:31 +08:00
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2021-10-12 11:32:30 +08:00
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// areaRemain
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2022-10-12 17:23:26 +08:00
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FLOAT16 tempDst[16];
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::memcpy(tempDst, src, areaRemain * 2 * sizeof(int16_t));
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auto cordH = vld2q_f16(tempDst);
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2021-10-12 11:32:30 +08:00
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cordH.val[0] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[0]), inW_sub_a), b));
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cordH.val[1] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[1]), inH_sub_a), b));
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2022-10-12 17:23:26 +08:00
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vst2q_f16(tempDst, cordH);
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::memcpy(dst, tempDst, areaRemain * 2 * sizeof(int16_t));
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2021-06-23 14:10:31 +08:00
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}
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2024-04-19 11:58:21 +08:00
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static void MNNGridSampleComputeCord3DFp16(FLOAT* dst, const FLOAT* src, size_t inD, size_t inH, size_t inW, size_t outD, size_t outH, size_t outW, size_t strideD, size_t strideH, bool alignCorners) {
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float16x8_t zero = vdupq_n_f16(0);
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float16x8_t one = vdupq_n_f16(1);
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float16x8_t half = vdupq_n_f16(0.5f);
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float16x8_t a = alignCorners ? one : zero;
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float16x8_t b = alignCorners ? zero : one;
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float16x8_t inW_sub_a = vsubq_f16(vdupq_n_f16(inW), a);
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float16x8_t inH_sub_a = vsubq_f16(vdupq_n_f16(inH), a);
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float16x8_t inD_sub_a = vsubq_f16(vdupq_n_f16(inD), a);
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size_t area = outH * outW * outD;
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size_t areaC8 = area / 8;
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size_t areaRemain = area - areaC8 * 8;
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for (int i = 0; i < areaC8; ++i) {
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auto cordH = vld3q_f16(src);
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// float16x8_t x = cordH.val[0];
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// float16x8_t y = cordH.val[1];
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cordH.val[0] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[0]), inW_sub_a), b));
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cordH.val[1] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[1]), inH_sub_a), b));
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cordH.val[2] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[2]), inD_sub_a), b));
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vst3q_f16(dst, cordH);
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src += 24;
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dst += 24;
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}
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if (areaRemain == 0) {
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return;
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}
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// areaRemain
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FLOAT16 tempDst[24];
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::memcpy(tempDst, src, areaRemain * 3 * sizeof(int16_t));
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auto cordH = vld3q_f16(tempDst);
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cordH.val[0] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[0]), inW_sub_a), b));
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cordH.val[1] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[1]), inH_sub_a), b));
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cordH.val[2] = vmulq_f16(half, vsubq_f16(vmulq_f16(vaddq_f16(one, cordH.val[2]), inD_sub_a), b));
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vst3q_f16(tempDst, cordH);
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::memcpy(dst, tempDst, areaRemain * 3 * sizeof(int16_t));
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}
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2022-01-29 18:03:25 +08:00
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static void MNNRoiPoolingMaxFP16(FLOAT16* dst, const FLOAT16* src, int hLen, int wLen, int iw) {
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2022-08-31 20:11:16 +08:00
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Vec max = Vec(-65504.0f);
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2022-01-29 18:03:25 +08:00
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for (int h = 0; h < hLen; h++, src += iw * 8) {
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for (int w = 0; w < wLen; w++) {
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Vec in = Vec::load(src + w * 8);
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max = Vec::max(max, in);
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}
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}
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Vec::save(dst, max);
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}
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static void MNNRoiAlignMaxFP16(FLOAT16* dst, const FLOAT16* src, const std::vector<std::vector<int>> &vecPos, const std::vector<std::vector<float>> &vecArea, int samplingRatioArea, int pooledHeight, int pooledWidth) {
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2023-02-15 10:30:27 +08:00
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for (int h = 0; h < pooledHeight; ++h, dst += pooledWidth * 8) {
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2022-01-29 18:03:25 +08:00
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int preCalcIdx = h * pooledWidth * samplingRatioArea;
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for (int w = 0; w < pooledWidth; ++w) {
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2022-08-31 20:11:16 +08:00
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Vec res = Vec(-65504.0f);
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2022-01-29 18:03:25 +08:00
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for (int i = 0; i < samplingRatioArea; ++i) {
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const std::vector<int>& pos = vecPos[preCalcIdx];
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const std::vector<float>& area = vecArea[preCalcIdx];
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Vec val0 = Vec::load(src + pos[0] * 8);
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Vec val1 = Vec::load(src + pos[1] * 8);
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Vec val2 = Vec::load(src + pos[2] * 8);
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Vec val3 = Vec::load(src + pos[3] * 8);
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Vec mla = val0 * area[0];
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mla = Vec::fma(mla, val1, area[1]);
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mla = Vec::fma(mla, val2, area[2]);
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mla = Vec::fma(mla, val3, area[3]);
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res = Vec::max(res, mla);
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preCalcIdx++;
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}
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Vec::save(dst + w * 8, res);
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}
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}
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}
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static void MNNRoiAlignAvgFP16(FLOAT16* dst, const FLOAT16* src, const std::vector<std::vector<int>> &vecPos, const std::vector<std::vector<float>> &vecArea, int samplingRatioArea, int pooledHeight, int pooledWidth) {
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float invSamplingCnt = 1.f / samplingRatioArea;
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2023-02-15 10:30:27 +08:00
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for (int h = 0; h < pooledHeight; ++h, dst += pooledWidth * 8) {
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2022-01-29 18:03:25 +08:00
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int preCalcIdx = h * pooledWidth * samplingRatioArea;
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for (int w = 0; w < pooledWidth; ++w) {
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Vec res = Vec(0.f);
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for (int i = 0; i < samplingRatioArea; ++i) {
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const std::vector<int>& pos = vecPos[preCalcIdx];
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const std::vector<float>& area = vecArea[preCalcIdx];
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Vec val0 = Vec::load(src + pos[0] * 8);
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Vec val1 = Vec::load(src + pos[1] * 8);
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Vec val2 = Vec::load(src + pos[2] * 8);
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Vec val3 = Vec::load(src + pos[3] * 8);
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Vec mla = val0 * area[0];
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mla = Vec::fma(mla, val1, area[1]);
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mla = Vec::fma(mla, val2, area[2]);
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mla = Vec::fma(mla, val3, area[3]);
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res += mla;
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preCalcIdx++;
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}
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res = res * invSamplingCnt;
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Vec::save(dst + w * 8, res);
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}
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}
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}
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2021-04-08 15:34:23 +08:00
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static void MNNCopyC8WithStrideFP16(const FLOAT16* source, FLOAT16* dest, size_t srcStride, size_t dstStride, size_t count) {
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using Vec = MNN::Math::Vec<FLOAT16, 8>;
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for (int i = 0; i < count; ++i) {
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auto srcPtr = source + i * srcStride;
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auto dstPtr = dest + i * dstStride;
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Vec::save(dstPtr, Vec::load(srcPtr));
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}
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}
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static void MNNAddC8WithStrideFP16(const FLOAT16* source, FLOAT16* dest, size_t srcStride, size_t dstStride, size_t count) {
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for (int i = 0; i < count; ++i) {
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auto srcPtr = source + i * srcStride;
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auto dstPtr = dest + i * dstStride;
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auto value = Vec::load(dstPtr) + Vec::load(srcPtr);
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Vec::save(dstPtr, value);
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}
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}
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static void MNNAxByClampBroadcastC8FP16(float* CF, const float* AF, const float* BF, size_t width, size_t cStride, size_t aStride, size_t height, const float* parameters) {
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auto C = (FLOAT16*)CF;
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auto A = (FLOAT16*)AF;
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auto B = (FLOAT16*)BF;
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using Vec = MNN::Math::Vec<FLOAT16, 8>;
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auto minF = Vec(parameters[2]);
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auto maxF = Vec(parameters[3]);
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auto beta = Vec(parameters[1]);
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for (int y = 0; y < height; ++y) {
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auto a = A + aStride * y;
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auto b = B + 8 * y;
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auto bv = Vec::load(b);
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auto c = C + cStride * y;
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for (int x = 0; x < width; ++x) {
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auto av = Vec::load(a + 8 * x);
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auto cv = av + bv * beta;
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cv = Vec::min(cv, maxF);
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cv = Vec::max(cv, minF);
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Vec::save(c + 8 * x, cv);
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}
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}
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}
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void ARM82StrassenMerge(FLOAT16* c11, FLOAT16* c12, FLOAT16* c21, FLOAT16* c22, FLOAT16* xAddr,
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size_t cStride, size_t eSub, size_t hSub) {
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const int pack = 8;
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for (int y = 0; y < hSub; ++y) {
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auto c11Y = c11 + y * cStride;
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auto c12Y = c12 + y * cStride;
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auto c22Y = c22 + y * cStride;
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auto c21Y = c21 + y * cStride;
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auto xY = xAddr + y * eSub * pack;
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for (int x = 0; x < eSub; ++x) {
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auto xv = vld1q_f16(xY + x * pack);
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auto c21v = vld1q_f16(c21Y + x * pack);
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auto c11v = vld1q_f16(c11Y + x * pack);
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auto c22v = vld1q_f16(c22Y + x * pack);
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auto c12v = vld1q_f16(c12Y + x * pack);
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c12v = c12v + xv;
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c21v = c12v + c21v;
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c12v = c22v + c12v;
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c22v = c22v + c21v;
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c12v = c11v + c12v;
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vst1q_f16(c12Y + x * pack, c12v);
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vst1q_f16(c22Y + x * pack, c22v);
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vst1q_f16(c21Y + x * pack, c21v);
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}
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}
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}
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[MNN:Sync] Sync internal github
Commits:
8148ae75c 弗人 bugfix
14cb8ec7f 弗人 [Converter:Bugfix] bugfix for onnx depthwise convtranspose
476fbcd90 雁行 [MNN:Feature] Open AVX cast and bugfix for contentCFG.
5e26b9fd3 雁行 [Test:Feature] Add android test.
37e147b25 雁行 [MNN:Bugfix] Bugfix for floordiv.
144c185f5 tianbu.xsw hangxing fix hiai
b4fd429d6 tianbu.xsw updateCacheFile bugfix -- update cache size
d4ba572a8 雁行 [MNN:Bugfix] Support int8 in AVX2 and some Bugfix.
43061f07e xiaying [MNN:Bugfix] Fix bug for module mode run part of model
398cc5ab6 tianhang.yth refactor demo
736380600 xiaying [Express:Bugfix] Fix memory leak for copy branch
b8dab0a27 tianhang.yth MNNFloat2Int8 sizeQuad=0 crash fix
94b95bfed ghz [BugFix]1.Better method for fast pack valid check
6a921f85e xiaying [Converter:Bugfix] Fix bug for Fuseconsttosubgraph
5f77ae889 tianhang.yth numThread bugfix
a807ef879 tianhang.yth add createSession(configs, runtimeinfo) API, add pymnn demo, pymnn logcat bugfix
ad05409d3 xiaying [MNN:Bugfix] Fix bug for StaticModule's sizecompute overflow, add error print for module mode
9d81b8299 xiaying [MNN:Bugfix] Fix bug for Unique op for output size = 1
03b15e9af xiaying [Test:Feature] Add MatMulBConst Test, Fix bug for single Convert
c944a76ee tianhang.yth add auto backend and getSessionInfo @tianbu
91fa7267b ghz [BugFix]1.fix the error in eP check
bf0041f77 ghz [BugFix]1.Fix the logic error in eP check. 2.Fix the sp align error
693871672 雁行 [CPU:Bugfix] rm adrp instruction for clang compiler bug.
1b8f6b3d8 ghz 1.Fix the wronly use of r13 in arm32 version. 2.Fix the missing callee register save and restore process.
feb7ecc4c 弗人 modify log of python offline quant
040c04811 ghz [BufFix]1.replace platform-related regs. 2.fix the same problem in arm32 version
609f37db8 弗人 add log for python quant, python convert
5511dd30a ghz [BugFix]1.Add testcases in SparseConv to check all functional code branch. 2. Fix the bug in "MNNPackC4ForMatMul_A.S" in arm64, which is caused by the missing check of eReal parameter.
a93ff9280 tianhang.yth add tf.Unique op support
9729ff773 allen.lk [Bugfix] Fix one arm32 instruction syntax that clang works but gcc DOES NOT work. use index instruction instead.
297c1ad14 雁行 [Expr:Bugfix] bugfix for tensor content used by shape compute.
ef8c369e3 弗人 catch exception
07c2dd670 弗人 add dependence to setup, base64 encode url, add time log
177e590c1 弗人 [Python:Feature] add aliyun log for python quant tool
40a7928cf allen.lk [Debug:Sparse] 1.Add group parameter in torchscript converter. 2. Stop split running to avoid memory corruption when check failed in TransformGroupConvolution 3. fix Op split issue in TransformGroupConvolution
3bdea84a1 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
c3c6fbdbd allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
bc590eee4 雁行 [Converter:Bugfix] bugfix for onnx instancenormalization convert.
d8918593f tianhang.yth add auto backend and getSessionInfo @tianbu
83a198ed7 杭行 update
d0dd3e09b 杭行 update
99540202e xiaying [Converter:Optimize] Opt the tensor convert insert
333d8db82 allen.lk [Debug:Sparse] Fix All platform-register r9 / x18 issue on arm32 and arm64.
db5994672 杭行 merge
6293de7b8 tianbu.xsw fix pymnn updateCacheFile
5c2e11cb1 tianbu.xsw do updateCache in createSession
6e7641ff4 tianbu.xsw do not limit cacheFile for a model
5287a65e4 tianbu.xsw bugfix
52ba53a91 tianbu.xsw revert pymnn api
60284d830 tianbu.xsw bugfix
6d8077490 tianbu.xsw rename updateCacheFile api params
3cb172710 tianhang.yth updateCacheFile API size default value is 0
c5b69aabf tianbu.xsw updateCacheFile python api fix
5d5da7aa5 tianbu.xsw reflector code
5707877a4 雁行 [MNN:Speed] Speedup for softmax in x86 and arm.
2a211825c tianbu.xsw reflector code for updateCacheFile
76db3a835 tianbu.xsw [Cache Feature]: Add updateCacheFile API for increment cache
b06b0fd43 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
e68bfa495 雁行 [Converter:Feature] Add UUID when model convert.
a9cb935dc xiaying [MNN:Speed] Support c4nhwc for more fastblit
019f40353 xiaying [Converter:Refractor] Reduce memory used by MNNConvert(bert from 5G -> 1G)
d2a6d3d05 xiaying [MNN:Bugfix] Fix bug for identity output not find
604d0801b xiaying [Converter:Bugfix] Fix bug for FuseGeLu
4bada2367 xiaying [MNN:Refractor] SegmentMean rewrite as segment
82070e708 xiaying [MNN:Bugfix] Fix bug for GeometryBinary
e8ea4266e xiaying Fix bug for ShapeTensorConvert compute for dim = 1 error
1f1cf1991 xiaying [Tools:Bugfix] Fix system compability for fastTestOnnx
6f422efe2 xiaying [Tools:Bugfix] Remove color for checkDir for easy to dump
968f7ec88 xiaying [MNN:Speed] Support turn broadcast binary to loop
3e7aaf46f xiaying [MNN:Refractor] Set Convolution1x1Strassen support variable input/output ptr
1f65ab163 xiaying [MNN:Bugfix] Fix bug for mini mnn can't convert model
d65953d47 xiaying [MNN:Bugfix] Fix bug for armv7a - android-14 + ARM82
8b68be45c xiaying [MNN:Feature] Add segment
8a8f264f5 xiaying [Vulkan:Bugfix] Remove unuseful print
025bb0fda xiaying [Converter:Bugfix] Fix bug for oneof don't support
43900251e tianbu.xsw enable setCacheFile python API
ebfb05c74 tianbu.xsw [Metal Feature] support metallib obtain from walle transfer task
9665c0a79 弗人 add check for path in json file
c66fef224 xiaying [Converter:Bugfix] Fix bug for oneof don't support
42f192852 xiaying [MNN:Bugfix] Fix bug for not set output / saveTensor into origin Schedule's outputs
1b95354ff 雁行 [Feature]: Support shape compute for SetDiff1D, and null input for Prod.
83966d043 xiaying [Test:Feature] Add test for static module
42d1be933 xiaying [Converter:Bugfix] Fix bug for mnn convert and static model add more outputs for origin model
9067531c3 xiaying [Converter:Refractor] formatLicence
99558bed9 xiaying [Converter:Bugfix] Count the op for unuseful and controlflow
4f6da0fa7 allen.lk [Feature:GRUMultiOutput] fix multi output dimension type
c6b219bce xiaying [Converter:Feature] Turn torch converter to object
dd4e68a37 xiaying [Converter:Feature] Support dump supported ops
80b6a60a3 xiaying [Converter:Info] If has output name, print output name instead of computed
015278fc3 xiaying [MNN:Refractor] Revert IfModule's debug info
23ac967c4 xiaying Don't transform for multi-input convolution/deconvolution
b02b0d4de xiaying Fix bug for multi-input for conv1d
254d8b1d4 xiaying Fix bug for Conv1dSqueezeMove for multi input convolution 1d
d47d0b9ca xiaying Fix bug for CPURaster's fuse nc4hw4
357c5bd33 xiaying Fix ConvBiasAdd for conv's inputs op > 1
55b1f0c9c xiaying [Converter:Bugfix] Don't transform for multi-input convolution/deconvolution
1902a30f5 xiaying [Converter:Bugfix] Fix bug for Conv1dSqueezeMove for multi input convolution 1d
c23fe617b xiaying [MNN:Bugfix] Fix bug for multi-input for conv1d
8ff018426 xiaying [MNN:Bugfix] Fix bug for CPURaster's fuse nc4hw4
d4e8cd602 xiaying [Converter:Bugfix] Fix ConvBiasAdd for conv's inputs op > 1
846266b42 tianbu.xsw return when program and tune both nullptr
fd67c76a9 xiaying [Converter:Bugfix] DepthwiseConvWeightMerge only valid for tflite
e77a242c4 xiaying [Converter:Feature] Support tflite's half pixel
be054c377 tianbu.xsw [OpenCL Bugfix] do not rewrite cache when binary program is produced
51e65aa35 xiaying [Converter:Feature] Support tflite for fp16 and multi-input convolution
1ccdfdeb5 tianbu.xsw redefine svm macro name
31234d372 tianbu.xsw [OpenCL SVM] add macro for only use wrapper
d739e35da xiaying [MNN:Bugfix] Fix compile bug for grid op
24ab13c79 Joker feat(arm82): add GridSample op support in arm82 backend, AVX(by xiaying)
7b142978e xiaying [AVX512:Speed] Optimize for e <= 8
5f6febe7b tianbu.xsw code refactor
998d91b57 xiaying [Express:Speed] Merge submodule for speed
22c89146f tianhang.yth fix alpha div by zero bug and arm server compile bug
8f829a170 tianbu.xsw [OpenCL Pad] unify conv/deconv pad computing
4a28f603e xiaying [Express:Speed] Shared Const for All Submodule
c74cf28f3 xiaying [MNN:Refractor] Seperate Const init and schedule
2a1eebb7a xiaying [Tools:Bugfix] Fix bug for modelTest.py count size
72f04008c xiaying [MNN:Refractor] Delete unuseful const op
1e735d03c xiaying [Converter:Bugfix] Fix bug for static module gen
4dfadbc6e xiaying [MNN:Refractor] Rewrite const init mode
1fcf0417a xiaying [MNN:Bugfix] Fix bug for deconvolutin multi-input for multi-batch
41d429cfd xiaying [Train:Bugfix] Revert convert NCHW for mnistTrain
f947a5f01 xiaying [Test:Feature] Add testTrain
dad59b6f6 tianbu.xsw move realize code from Backend.hpp to Tensor.cpp
cf4473ad1 xiaying [Train:Bugfix] Support pad for GeometryPoolGrad
91ab13734 xiaying [MNN:Bugfix] Fix compile bug for avx512
742e80f47 xiaying [MNN:Refractor] Opt the logic for checknan judge
12543b841 xiaying [ARM82:Bugfix] Fix compile bug for ios
3a2b0a49f xiaying [ARM82:Speed] Opt Pack / Unpack for armv8
c0f1995cd xiaying [ARM82:Speed] Opt MNNPackC8FP16 and MNNUnpackC8FP16 by asm
e0fc77dcf xiaying [MNN:Speed] Fix bug for DeconvolutionWithStride for C4HW4, open it
584bec578 xiaying [MNN:Bugfix] Fix bug for format set error for onnx
d5bd4148d xiaying [MNN:Bugfix] Fix bug for format set error for onnx
b00265841 xiaying [MNN:Bugfix] Fix bug for SparseConvolutionTiledExecutor
bb09188ac xiaying [Test:Bugfix] Fix bug for run into sparse auto
426d1babd xiaying [MNN:Refractor] Small bugfix for Group convolution and pack
7d0ea1c46 tianbu.xsw [testModel Feature] support testModel.out input resize
4169c54ce xiaying [MNN:Bugfix] Fix bug for checkNAN for origin
412a82222 xiaying [Test:Bugfix] Fix bug for CheckNAN's error of matmul
319b1d425 xiaying [MNN:Bugfix] Fix bug for multi-batch for ConvInt8
050b728a6 xiaying [Test:Bugfix] Use NCHW for ConvInt8Test
7db3423a1 xiaying [OpenCL:Bugfix] Fix bug for opencl::image,opencl::buffer for C4HW4
adcec6a7f xiaying [Vulkan:Bugfix] Fix bug for invalid tensor size limit
d2a7cf4e9 xiaying [Vulkan:Bugfix] Fix bug for onCopyBuffer of nc4hw4
557bebdd3 xiaying [MNN:Bugfix] Fix bug for BF16-ARM32
bbe186649 tianbu.xsw [Update AUTO mode]: fix MNN_FORWARD_AUTO choose priority
6deb23439 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
b137590e4 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
7003558ea xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
b5f8cae5a xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
29b09e125 xiaying [MNN:Bugfix] Fix bug for arm64-bf16
42ce00770 xiaying [MNN:Bugfix] Fix bug for ARM64 - float
a2d89fc18 雁行 [Converter:Feature] Support Binary Unary for Torch.
7f1c0deb1 xiaying [MNN:Bugfix] Fix bug for Raster for Int8
8335a6f18 tianbu.xsw [OpenCL Shared Memory] modify data_format method
b359e031b xiaying [ARM82:Bugfix] Fix bug for arm82 and speed up pack / unpack c8
24bf3fc88 雁行 [Convert:Feature] Support LayerNormFuse without gamma beta.
3e629624b xiaying [MNN:Bugfix] Fix bug for float - armv7a
2b7908ec7 tianbu.xsw modify workItemSize
3cee0d413 xiaying [MNN:Bugfix] test wrong clear
9cbbfb998 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
2d7a44484 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
eb7d0cb53 xiaying [Test:Bugfix] Don't test for NC4HW4 directly
7b40ca8d1 xiaying [MNN:Bugfix] Fix bug for ConvolutionGroup
2694d8a91 xiaying [MNN:Bugfix] Fix bug for CPUGridSample
f89af60f6 xiaying [MNN:Bugfix] Fix compile bug for arm
a151abcdd xiaying [MNN:Bugfix] Fix bug for convert for int8 / int16
b254dbe61 雁行 [MNN:Bugfix] Bugfix for Conv onClone.
d08150631 xiaying [MNN:Bugfix] Fix bug for fast rcnn
e5568a0df xiaying [MNN:Bugfix] Fix bug for CPURaster treat NC4HW4 fast blit
128318933 雁行 [Raster:Bugfix] bugfix for Raster merge onResize.
03caacbea xiaying [MNN:Bugfix] fix bug for CPUDeconvolution and Convolution1x1Strassen for iw != ow
e1e3c245c xiaying [MNN:Bugfix] Fix bug for ConvolutionWinograd
2524cbc6d xiaying [MNN:Bugfix] Fix bug for CPUSoftmax
44ec79b8f xiaying [MNN:Bugfix] Fix bug for CPUConvolutionDepthwise / Scale / DeconvolutionDW
21ae956ce xiaying [MNN:Bugfix] Fix bug for Multi-Batch-TiledExecutor
09a5069c7 xiaying [MNN:Speed] Add offset for src and dst
6776c6784 xiaying [MNN:Bugfix] Fix bug for trainable model
cc83ae30b xiaying [MNN:Bugfix] Fix bug for trainable model
2021-07-29 11:46:59 +08:00
|
|
|
void MNNUnpackTransposeInt16C8(int16_t* dst, const int16_t* src, size_t area, size_t depth, int32_t* areaOffset) {
|
|
|
|
int srcAreaOffset = areaOffset[0];
|
2021-04-08 15:34:23 +08:00
|
|
|
int c = (int)depth;
|
|
|
|
int cDiv4 = c / 8;
|
|
|
|
int cAlign = cDiv4 * 8;
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for (int hi = 0; hi < area; ++hi) {
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auto srcHeight = src + hi * 8;
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auto dstHeight = dst + hi * c;
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for (int ci = 0; ci < cDiv4; ++ci) {
|
[MNN:Sync] Sync internal github
Commits:
8148ae75c 弗人 bugfix
14cb8ec7f 弗人 [Converter:Bugfix] bugfix for onnx depthwise convtranspose
476fbcd90 雁行 [MNN:Feature] Open AVX cast and bugfix for contentCFG.
5e26b9fd3 雁行 [Test:Feature] Add android test.
37e147b25 雁行 [MNN:Bugfix] Bugfix for floordiv.
144c185f5 tianbu.xsw hangxing fix hiai
b4fd429d6 tianbu.xsw updateCacheFile bugfix -- update cache size
d4ba572a8 雁行 [MNN:Bugfix] Support int8 in AVX2 and some Bugfix.
43061f07e xiaying [MNN:Bugfix] Fix bug for module mode run part of model
398cc5ab6 tianhang.yth refactor demo
736380600 xiaying [Express:Bugfix] Fix memory leak for copy branch
b8dab0a27 tianhang.yth MNNFloat2Int8 sizeQuad=0 crash fix
94b95bfed ghz [BugFix]1.Better method for fast pack valid check
6a921f85e xiaying [Converter:Bugfix] Fix bug for Fuseconsttosubgraph
5f77ae889 tianhang.yth numThread bugfix
a807ef879 tianhang.yth add createSession(configs, runtimeinfo) API, add pymnn demo, pymnn logcat bugfix
ad05409d3 xiaying [MNN:Bugfix] Fix bug for StaticModule's sizecompute overflow, add error print for module mode
9d81b8299 xiaying [MNN:Bugfix] Fix bug for Unique op for output size = 1
03b15e9af xiaying [Test:Feature] Add MatMulBConst Test, Fix bug for single Convert
c944a76ee tianhang.yth add auto backend and getSessionInfo @tianbu
91fa7267b ghz [BugFix]1.fix the error in eP check
bf0041f77 ghz [BugFix]1.Fix the logic error in eP check. 2.Fix the sp align error
693871672 雁行 [CPU:Bugfix] rm adrp instruction for clang compiler bug.
1b8f6b3d8 ghz 1.Fix the wronly use of r13 in arm32 version. 2.Fix the missing callee register save and restore process.
feb7ecc4c 弗人 modify log of python offline quant
040c04811 ghz [BufFix]1.replace platform-related regs. 2.fix the same problem in arm32 version
609f37db8 弗人 add log for python quant, python convert
5511dd30a ghz [BugFix]1.Add testcases in SparseConv to check all functional code branch. 2. Fix the bug in "MNNPackC4ForMatMul_A.S" in arm64, which is caused by the missing check of eReal parameter.
a93ff9280 tianhang.yth add tf.Unique op support
9729ff773 allen.lk [Bugfix] Fix one arm32 instruction syntax that clang works but gcc DOES NOT work. use index instruction instead.
297c1ad14 雁行 [Expr:Bugfix] bugfix for tensor content used by shape compute.
ef8c369e3 弗人 catch exception
07c2dd670 弗人 add dependence to setup, base64 encode url, add time log
177e590c1 弗人 [Python:Feature] add aliyun log for python quant tool
40a7928cf allen.lk [Debug:Sparse] 1.Add group parameter in torchscript converter. 2. Stop split running to avoid memory corruption when check failed in TransformGroupConvolution 3. fix Op split issue in TransformGroupConvolution
3bdea84a1 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
c3c6fbdbd allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
bc590eee4 雁行 [Converter:Bugfix] bugfix for onnx instancenormalization convert.
d8918593f tianhang.yth add auto backend and getSessionInfo @tianbu
83a198ed7 杭行 update
d0dd3e09b 杭行 update
99540202e xiaying [Converter:Optimize] Opt the tensor convert insert
333d8db82 allen.lk [Debug:Sparse] Fix All platform-register r9 / x18 issue on arm32 and arm64.
db5994672 杭行 merge
6293de7b8 tianbu.xsw fix pymnn updateCacheFile
5c2e11cb1 tianbu.xsw do updateCache in createSession
6e7641ff4 tianbu.xsw do not limit cacheFile for a model
5287a65e4 tianbu.xsw bugfix
52ba53a91 tianbu.xsw revert pymnn api
60284d830 tianbu.xsw bugfix
6d8077490 tianbu.xsw rename updateCacheFile api params
3cb172710 tianhang.yth updateCacheFile API size default value is 0
c5b69aabf tianbu.xsw updateCacheFile python api fix
5d5da7aa5 tianbu.xsw reflector code
5707877a4 雁行 [MNN:Speed] Speedup for softmax in x86 and arm.
2a211825c tianbu.xsw reflector code for updateCacheFile
76db3a835 tianbu.xsw [Cache Feature]: Add updateCacheFile API for increment cache
b06b0fd43 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
e68bfa495 雁行 [Converter:Feature] Add UUID when model convert.
a9cb935dc xiaying [MNN:Speed] Support c4nhwc for more fastblit
019f40353 xiaying [Converter:Refractor] Reduce memory used by MNNConvert(bert from 5G -> 1G)
d2a6d3d05 xiaying [MNN:Bugfix] Fix bug for identity output not find
604d0801b xiaying [Converter:Bugfix] Fix bug for FuseGeLu
4bada2367 xiaying [MNN:Refractor] SegmentMean rewrite as segment
82070e708 xiaying [MNN:Bugfix] Fix bug for GeometryBinary
e8ea4266e xiaying Fix bug for ShapeTensorConvert compute for dim = 1 error
1f1cf1991 xiaying [Tools:Bugfix] Fix system compability for fastTestOnnx
6f422efe2 xiaying [Tools:Bugfix] Remove color for checkDir for easy to dump
968f7ec88 xiaying [MNN:Speed] Support turn broadcast binary to loop
3e7aaf46f xiaying [MNN:Refractor] Set Convolution1x1Strassen support variable input/output ptr
1f65ab163 xiaying [MNN:Bugfix] Fix bug for mini mnn can't convert model
d65953d47 xiaying [MNN:Bugfix] Fix bug for armv7a - android-14 + ARM82
8b68be45c xiaying [MNN:Feature] Add segment
8a8f264f5 xiaying [Vulkan:Bugfix] Remove unuseful print
025bb0fda xiaying [Converter:Bugfix] Fix bug for oneof don't support
43900251e tianbu.xsw enable setCacheFile python API
ebfb05c74 tianbu.xsw [Metal Feature] support metallib obtain from walle transfer task
9665c0a79 弗人 add check for path in json file
c66fef224 xiaying [Converter:Bugfix] Fix bug for oneof don't support
42f192852 xiaying [MNN:Bugfix] Fix bug for not set output / saveTensor into origin Schedule's outputs
1b95354ff 雁行 [Feature]: Support shape compute for SetDiff1D, and null input for Prod.
83966d043 xiaying [Test:Feature] Add test for static module
42d1be933 xiaying [Converter:Bugfix] Fix bug for mnn convert and static model add more outputs for origin model
9067531c3 xiaying [Converter:Refractor] formatLicence
99558bed9 xiaying [Converter:Bugfix] Count the op for unuseful and controlflow
4f6da0fa7 allen.lk [Feature:GRUMultiOutput] fix multi output dimension type
c6b219bce xiaying [Converter:Feature] Turn torch converter to object
dd4e68a37 xiaying [Converter:Feature] Support dump supported ops
80b6a60a3 xiaying [Converter:Info] If has output name, print output name instead of computed
015278fc3 xiaying [MNN:Refractor] Revert IfModule's debug info
23ac967c4 xiaying Don't transform for multi-input convolution/deconvolution
b02b0d4de xiaying Fix bug for multi-input for conv1d
254d8b1d4 xiaying Fix bug for Conv1dSqueezeMove for multi input convolution 1d
d47d0b9ca xiaying Fix bug for CPURaster's fuse nc4hw4
357c5bd33 xiaying Fix ConvBiasAdd for conv's inputs op > 1
55b1f0c9c xiaying [Converter:Bugfix] Don't transform for multi-input convolution/deconvolution
1902a30f5 xiaying [Converter:Bugfix] Fix bug for Conv1dSqueezeMove for multi input convolution 1d
c23fe617b xiaying [MNN:Bugfix] Fix bug for multi-input for conv1d
8ff018426 xiaying [MNN:Bugfix] Fix bug for CPURaster's fuse nc4hw4
d4e8cd602 xiaying [Converter:Bugfix] Fix ConvBiasAdd for conv's inputs op > 1
846266b42 tianbu.xsw return when program and tune both nullptr
fd67c76a9 xiaying [Converter:Bugfix] DepthwiseConvWeightMerge only valid for tflite
e77a242c4 xiaying [Converter:Feature] Support tflite's half pixel
be054c377 tianbu.xsw [OpenCL Bugfix] do not rewrite cache when binary program is produced
51e65aa35 xiaying [Converter:Feature] Support tflite for fp16 and multi-input convolution
1ccdfdeb5 tianbu.xsw redefine svm macro name
31234d372 tianbu.xsw [OpenCL SVM] add macro for only use wrapper
d739e35da xiaying [MNN:Bugfix] Fix compile bug for grid op
24ab13c79 Joker feat(arm82): add GridSample op support in arm82 backend, AVX(by xiaying)
7b142978e xiaying [AVX512:Speed] Optimize for e <= 8
5f6febe7b tianbu.xsw code refactor
998d91b57 xiaying [Express:Speed] Merge submodule for speed
22c89146f tianhang.yth fix alpha div by zero bug and arm server compile bug
8f829a170 tianbu.xsw [OpenCL Pad] unify conv/deconv pad computing
4a28f603e xiaying [Express:Speed] Shared Const for All Submodule
c74cf28f3 xiaying [MNN:Refractor] Seperate Const init and schedule
2a1eebb7a xiaying [Tools:Bugfix] Fix bug for modelTest.py count size
72f04008c xiaying [MNN:Refractor] Delete unuseful const op
1e735d03c xiaying [Converter:Bugfix] Fix bug for static module gen
4dfadbc6e xiaying [MNN:Refractor] Rewrite const init mode
1fcf0417a xiaying [MNN:Bugfix] Fix bug for deconvolutin multi-input for multi-batch
41d429cfd xiaying [Train:Bugfix] Revert convert NCHW for mnistTrain
f947a5f01 xiaying [Test:Feature] Add testTrain
dad59b6f6 tianbu.xsw move realize code from Backend.hpp to Tensor.cpp
cf4473ad1 xiaying [Train:Bugfix] Support pad for GeometryPoolGrad
91ab13734 xiaying [MNN:Bugfix] Fix compile bug for avx512
742e80f47 xiaying [MNN:Refractor] Opt the logic for checknan judge
12543b841 xiaying [ARM82:Bugfix] Fix compile bug for ios
3a2b0a49f xiaying [ARM82:Speed] Opt Pack / Unpack for armv8
c0f1995cd xiaying [ARM82:Speed] Opt MNNPackC8FP16 and MNNUnpackC8FP16 by asm
e0fc77dcf xiaying [MNN:Speed] Fix bug for DeconvolutionWithStride for C4HW4, open it
584bec578 xiaying [MNN:Bugfix] Fix bug for format set error for onnx
d5bd4148d xiaying [MNN:Bugfix] Fix bug for format set error for onnx
b00265841 xiaying [MNN:Bugfix] Fix bug for SparseConvolutionTiledExecutor
bb09188ac xiaying [Test:Bugfix] Fix bug for run into sparse auto
426d1babd xiaying [MNN:Refractor] Small bugfix for Group convolution and pack
7d0ea1c46 tianbu.xsw [testModel Feature] support testModel.out input resize
4169c54ce xiaying [MNN:Bugfix] Fix bug for checkNAN for origin
412a82222 xiaying [Test:Bugfix] Fix bug for CheckNAN's error of matmul
319b1d425 xiaying [MNN:Bugfix] Fix bug for multi-batch for ConvInt8
050b728a6 xiaying [Test:Bugfix] Use NCHW for ConvInt8Test
7db3423a1 xiaying [OpenCL:Bugfix] Fix bug for opencl::image,opencl::buffer for C4HW4
adcec6a7f xiaying [Vulkan:Bugfix] Fix bug for invalid tensor size limit
d2a7cf4e9 xiaying [Vulkan:Bugfix] Fix bug for onCopyBuffer of nc4hw4
557bebdd3 xiaying [MNN:Bugfix] Fix bug for BF16-ARM32
bbe186649 tianbu.xsw [Update AUTO mode]: fix MNN_FORWARD_AUTO choose priority
6deb23439 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
b137590e4 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
7003558ea xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
b5f8cae5a xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
29b09e125 xiaying [MNN:Bugfix] Fix bug for arm64-bf16
42ce00770 xiaying [MNN:Bugfix] Fix bug for ARM64 - float
a2d89fc18 雁行 [Converter:Feature] Support Binary Unary for Torch.
7f1c0deb1 xiaying [MNN:Bugfix] Fix bug for Raster for Int8
8335a6f18 tianbu.xsw [OpenCL Shared Memory] modify data_format method
b359e031b xiaying [ARM82:Bugfix] Fix bug for arm82 and speed up pack / unpack c8
24bf3fc88 雁行 [Convert:Feature] Support LayerNormFuse without gamma beta.
3e629624b xiaying [MNN:Bugfix] Fix bug for float - armv7a
2b7908ec7 tianbu.xsw modify workItemSize
3cee0d413 xiaying [MNN:Bugfix] test wrong clear
9cbbfb998 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
2d7a44484 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
eb7d0cb53 xiaying [Test:Bugfix] Don't test for NC4HW4 directly
7b40ca8d1 xiaying [MNN:Bugfix] Fix bug for ConvolutionGroup
2694d8a91 xiaying [MNN:Bugfix] Fix bug for CPUGridSample
f89af60f6 xiaying [MNN:Bugfix] Fix compile bug for arm
a151abcdd xiaying [MNN:Bugfix] Fix bug for convert for int8 / int16
b254dbe61 雁行 [MNN:Bugfix] Bugfix for Conv onClone.
d08150631 xiaying [MNN:Bugfix] Fix bug for fast rcnn
e5568a0df xiaying [MNN:Bugfix] Fix bug for CPURaster treat NC4HW4 fast blit
128318933 雁行 [Raster:Bugfix] bugfix for Raster merge onResize.
03caacbea xiaying [MNN:Bugfix] fix bug for CPUDeconvolution and Convolution1x1Strassen for iw != ow
e1e3c245c xiaying [MNN:Bugfix] Fix bug for ConvolutionWinograd
2524cbc6d xiaying [MNN:Bugfix] Fix bug for CPUSoftmax
44ec79b8f xiaying [MNN:Bugfix] Fix bug for CPUConvolutionDepthwise / Scale / DeconvolutionDW
21ae956ce xiaying [MNN:Bugfix] Fix bug for Multi-Batch-TiledExecutor
09a5069c7 xiaying [MNN:Speed] Add offset for src and dst
6776c6784 xiaying [MNN:Bugfix] Fix bug for trainable model
cc83ae30b xiaying [MNN:Bugfix] Fix bug for trainable model
2021-07-29 11:46:59 +08:00
|
|
|
vst1q_s16(dstHeight + ci * 8, vld1q_s16(srcHeight + 8 * ci * srcAreaOffset));
|
2021-04-08 15:34:23 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
int cReamin = c - cAlign;
|
[MNN:Sync] Sync internal github
Commits:
8148ae75c 弗人 bugfix
14cb8ec7f 弗人 [Converter:Bugfix] bugfix for onnx depthwise convtranspose
476fbcd90 雁行 [MNN:Feature] Open AVX cast and bugfix for contentCFG.
5e26b9fd3 雁行 [Test:Feature] Add android test.
37e147b25 雁行 [MNN:Bugfix] Bugfix for floordiv.
144c185f5 tianbu.xsw hangxing fix hiai
b4fd429d6 tianbu.xsw updateCacheFile bugfix -- update cache size
d4ba572a8 雁行 [MNN:Bugfix] Support int8 in AVX2 and some Bugfix.
43061f07e xiaying [MNN:Bugfix] Fix bug for module mode run part of model
398cc5ab6 tianhang.yth refactor demo
736380600 xiaying [Express:Bugfix] Fix memory leak for copy branch
b8dab0a27 tianhang.yth MNNFloat2Int8 sizeQuad=0 crash fix
94b95bfed ghz [BugFix]1.Better method for fast pack valid check
6a921f85e xiaying [Converter:Bugfix] Fix bug for Fuseconsttosubgraph
5f77ae889 tianhang.yth numThread bugfix
a807ef879 tianhang.yth add createSession(configs, runtimeinfo) API, add pymnn demo, pymnn logcat bugfix
ad05409d3 xiaying [MNN:Bugfix] Fix bug for StaticModule's sizecompute overflow, add error print for module mode
9d81b8299 xiaying [MNN:Bugfix] Fix bug for Unique op for output size = 1
03b15e9af xiaying [Test:Feature] Add MatMulBConst Test, Fix bug for single Convert
c944a76ee tianhang.yth add auto backend and getSessionInfo @tianbu
91fa7267b ghz [BugFix]1.fix the error in eP check
bf0041f77 ghz [BugFix]1.Fix the logic error in eP check. 2.Fix the sp align error
693871672 雁行 [CPU:Bugfix] rm adrp instruction for clang compiler bug.
1b8f6b3d8 ghz 1.Fix the wronly use of r13 in arm32 version. 2.Fix the missing callee register save and restore process.
feb7ecc4c 弗人 modify log of python offline quant
040c04811 ghz [BufFix]1.replace platform-related regs. 2.fix the same problem in arm32 version
609f37db8 弗人 add log for python quant, python convert
5511dd30a ghz [BugFix]1.Add testcases in SparseConv to check all functional code branch. 2. Fix the bug in "MNNPackC4ForMatMul_A.S" in arm64, which is caused by the missing check of eReal parameter.
a93ff9280 tianhang.yth add tf.Unique op support
9729ff773 allen.lk [Bugfix] Fix one arm32 instruction syntax that clang works but gcc DOES NOT work. use index instruction instead.
297c1ad14 雁行 [Expr:Bugfix] bugfix for tensor content used by shape compute.
ef8c369e3 弗人 catch exception
07c2dd670 弗人 add dependence to setup, base64 encode url, add time log
177e590c1 弗人 [Python:Feature] add aliyun log for python quant tool
40a7928cf allen.lk [Debug:Sparse] 1.Add group parameter in torchscript converter. 2. Stop split running to avoid memory corruption when check failed in TransformGroupConvolution 3. fix Op split issue in TransformGroupConvolution
3bdea84a1 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
c3c6fbdbd allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
bc590eee4 雁行 [Converter:Bugfix] bugfix for onnx instancenormalization convert.
d8918593f tianhang.yth add auto backend and getSessionInfo @tianbu
83a198ed7 杭行 update
d0dd3e09b 杭行 update
99540202e xiaying [Converter:Optimize] Opt the tensor convert insert
333d8db82 allen.lk [Debug:Sparse] Fix All platform-register r9 / x18 issue on arm32 and arm64.
db5994672 杭行 merge
6293de7b8 tianbu.xsw fix pymnn updateCacheFile
5c2e11cb1 tianbu.xsw do updateCache in createSession
6e7641ff4 tianbu.xsw do not limit cacheFile for a model
5287a65e4 tianbu.xsw bugfix
52ba53a91 tianbu.xsw revert pymnn api
60284d830 tianbu.xsw bugfix
6d8077490 tianbu.xsw rename updateCacheFile api params
3cb172710 tianhang.yth updateCacheFile API size default value is 0
c5b69aabf tianbu.xsw updateCacheFile python api fix
5d5da7aa5 tianbu.xsw reflector code
5707877a4 雁行 [MNN:Speed] Speedup for softmax in x86 and arm.
2a211825c tianbu.xsw reflector code for updateCacheFile
76db3a835 tianbu.xsw [Cache Feature]: Add updateCacheFile API for increment cache
b06b0fd43 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
e68bfa495 雁行 [Converter:Feature] Add UUID when model convert.
a9cb935dc xiaying [MNN:Speed] Support c4nhwc for more fastblit
019f40353 xiaying [Converter:Refractor] Reduce memory used by MNNConvert(bert from 5G -> 1G)
d2a6d3d05 xiaying [MNN:Bugfix] Fix bug for identity output not find
604d0801b xiaying [Converter:Bugfix] Fix bug for FuseGeLu
4bada2367 xiaying [MNN:Refractor] SegmentMean rewrite as segment
82070e708 xiaying [MNN:Bugfix] Fix bug for GeometryBinary
e8ea4266e xiaying Fix bug for ShapeTensorConvert compute for dim = 1 error
1f1cf1991 xiaying [Tools:Bugfix] Fix system compability for fastTestOnnx
6f422efe2 xiaying [Tools:Bugfix] Remove color for checkDir for easy to dump
968f7ec88 xiaying [MNN:Speed] Support turn broadcast binary to loop
3e7aaf46f xiaying [MNN:Refractor] Set Convolution1x1Strassen support variable input/output ptr
1f65ab163 xiaying [MNN:Bugfix] Fix bug for mini mnn can't convert model
d65953d47 xiaying [MNN:Bugfix] Fix bug for armv7a - android-14 + ARM82
8b68be45c xiaying [MNN:Feature] Add segment
8a8f264f5 xiaying [Vulkan:Bugfix] Remove unuseful print
025bb0fda xiaying [Converter:Bugfix] Fix bug for oneof don't support
43900251e tianbu.xsw enable setCacheFile python API
ebfb05c74 tianbu.xsw [Metal Feature] support metallib obtain from walle transfer task
9665c0a79 弗人 add check for path in json file
c66fef224 xiaying [Converter:Bugfix] Fix bug for oneof don't support
42f192852 xiaying [MNN:Bugfix] Fix bug for not set output / saveTensor into origin Schedule's outputs
1b95354ff 雁行 [Feature]: Support shape compute for SetDiff1D, and null input for Prod.
83966d043 xiaying [Test:Feature] Add test for static module
42d1be933 xiaying [Converter:Bugfix] Fix bug for mnn convert and static model add more outputs for origin model
9067531c3 xiaying [Converter:Refractor] formatLicence
99558bed9 xiaying [Converter:Bugfix] Count the op for unuseful and controlflow
4f6da0fa7 allen.lk [Feature:GRUMultiOutput] fix multi output dimension type
c6b219bce xiaying [Converter:Feature] Turn torch converter to object
dd4e68a37 xiaying [Converter:Feature] Support dump supported ops
80b6a60a3 xiaying [Converter:Info] If has output name, print output name instead of computed
015278fc3 xiaying [MNN:Refractor] Revert IfModule's debug info
23ac967c4 xiaying Don't transform for multi-input convolution/deconvolution
b02b0d4de xiaying Fix bug for multi-input for conv1d
254d8b1d4 xiaying Fix bug for Conv1dSqueezeMove for multi input convolution 1d
d47d0b9ca xiaying Fix bug for CPURaster's fuse nc4hw4
357c5bd33 xiaying Fix ConvBiasAdd for conv's inputs op > 1
55b1f0c9c xiaying [Converter:Bugfix] Don't transform for multi-input convolution/deconvolution
1902a30f5 xiaying [Converter:Bugfix] Fix bug for Conv1dSqueezeMove for multi input convolution 1d
c23fe617b xiaying [MNN:Bugfix] Fix bug for multi-input for conv1d
8ff018426 xiaying [MNN:Bugfix] Fix bug for CPURaster's fuse nc4hw4
d4e8cd602 xiaying [Converter:Bugfix] Fix ConvBiasAdd for conv's inputs op > 1
846266b42 tianbu.xsw return when program and tune both nullptr
fd67c76a9 xiaying [Converter:Bugfix] DepthwiseConvWeightMerge only valid for tflite
e77a242c4 xiaying [Converter:Feature] Support tflite's half pixel
be054c377 tianbu.xsw [OpenCL Bugfix] do not rewrite cache when binary program is produced
51e65aa35 xiaying [Converter:Feature] Support tflite for fp16 and multi-input convolution
1ccdfdeb5 tianbu.xsw redefine svm macro name
31234d372 tianbu.xsw [OpenCL SVM] add macro for only use wrapper
d739e35da xiaying [MNN:Bugfix] Fix compile bug for grid op
24ab13c79 Joker feat(arm82): add GridSample op support in arm82 backend, AVX(by xiaying)
7b142978e xiaying [AVX512:Speed] Optimize for e <= 8
5f6febe7b tianbu.xsw code refactor
998d91b57 xiaying [Express:Speed] Merge submodule for speed
22c89146f tianhang.yth fix alpha div by zero bug and arm server compile bug
8f829a170 tianbu.xsw [OpenCL Pad] unify conv/deconv pad computing
4a28f603e xiaying [Express:Speed] Shared Const for All Submodule
c74cf28f3 xiaying [MNN:Refractor] Seperate Const init and schedule
2a1eebb7a xiaying [Tools:Bugfix] Fix bug for modelTest.py count size
72f04008c xiaying [MNN:Refractor] Delete unuseful const op
1e735d03c xiaying [Converter:Bugfix] Fix bug for static module gen
4dfadbc6e xiaying [MNN:Refractor] Rewrite const init mode
1fcf0417a xiaying [MNN:Bugfix] Fix bug for deconvolutin multi-input for multi-batch
41d429cfd xiaying [Train:Bugfix] Revert convert NCHW for mnistTrain
f947a5f01 xiaying [Test:Feature] Add testTrain
dad59b6f6 tianbu.xsw move realize code from Backend.hpp to Tensor.cpp
cf4473ad1 xiaying [Train:Bugfix] Support pad for GeometryPoolGrad
91ab13734 xiaying [MNN:Bugfix] Fix compile bug for avx512
742e80f47 xiaying [MNN:Refractor] Opt the logic for checknan judge
12543b841 xiaying [ARM82:Bugfix] Fix compile bug for ios
3a2b0a49f xiaying [ARM82:Speed] Opt Pack / Unpack for armv8
c0f1995cd xiaying [ARM82:Speed] Opt MNNPackC8FP16 and MNNUnpackC8FP16 by asm
e0fc77dcf xiaying [MNN:Speed] Fix bug for DeconvolutionWithStride for C4HW4, open it
584bec578 xiaying [MNN:Bugfix] Fix bug for format set error for onnx
d5bd4148d xiaying [MNN:Bugfix] Fix bug for format set error for onnx
b00265841 xiaying [MNN:Bugfix] Fix bug for SparseConvolutionTiledExecutor
bb09188ac xiaying [Test:Bugfix] Fix bug for run into sparse auto
426d1babd xiaying [MNN:Refractor] Small bugfix for Group convolution and pack
7d0ea1c46 tianbu.xsw [testModel Feature] support testModel.out input resize
4169c54ce xiaying [MNN:Bugfix] Fix bug for checkNAN for origin
412a82222 xiaying [Test:Bugfix] Fix bug for CheckNAN's error of matmul
319b1d425 xiaying [MNN:Bugfix] Fix bug for multi-batch for ConvInt8
050b728a6 xiaying [Test:Bugfix] Use NCHW for ConvInt8Test
7db3423a1 xiaying [OpenCL:Bugfix] Fix bug for opencl::image,opencl::buffer for C4HW4
adcec6a7f xiaying [Vulkan:Bugfix] Fix bug for invalid tensor size limit
d2a7cf4e9 xiaying [Vulkan:Bugfix] Fix bug for onCopyBuffer of nc4hw4
557bebdd3 xiaying [MNN:Bugfix] Fix bug for BF16-ARM32
bbe186649 tianbu.xsw [Update AUTO mode]: fix MNN_FORWARD_AUTO choose priority
6deb23439 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
b137590e4 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
7003558ea xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
b5f8cae5a xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
29b09e125 xiaying [MNN:Bugfix] Fix bug for arm64-bf16
42ce00770 xiaying [MNN:Bugfix] Fix bug for ARM64 - float
a2d89fc18 雁行 [Converter:Feature] Support Binary Unary for Torch.
7f1c0deb1 xiaying [MNN:Bugfix] Fix bug for Raster for Int8
8335a6f18 tianbu.xsw [OpenCL Shared Memory] modify data_format method
b359e031b xiaying [ARM82:Bugfix] Fix bug for arm82 and speed up pack / unpack c8
24bf3fc88 雁行 [Convert:Feature] Support LayerNormFuse without gamma beta.
3e629624b xiaying [MNN:Bugfix] Fix bug for float - armv7a
2b7908ec7 tianbu.xsw modify workItemSize
3cee0d413 xiaying [MNN:Bugfix] test wrong clear
9cbbfb998 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
2d7a44484 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
eb7d0cb53 xiaying [Test:Bugfix] Don't test for NC4HW4 directly
7b40ca8d1 xiaying [MNN:Bugfix] Fix bug for ConvolutionGroup
2694d8a91 xiaying [MNN:Bugfix] Fix bug for CPUGridSample
f89af60f6 xiaying [MNN:Bugfix] Fix compile bug for arm
a151abcdd xiaying [MNN:Bugfix] Fix bug for convert for int8 / int16
b254dbe61 雁行 [MNN:Bugfix] Bugfix for Conv onClone.
d08150631 xiaying [MNN:Bugfix] Fix bug for fast rcnn
e5568a0df xiaying [MNN:Bugfix] Fix bug for CPURaster treat NC4HW4 fast blit
128318933 雁行 [Raster:Bugfix] bugfix for Raster merge onResize.
03caacbea xiaying [MNN:Bugfix] fix bug for CPUDeconvolution and Convolution1x1Strassen for iw != ow
e1e3c245c xiaying [MNN:Bugfix] Fix bug for ConvolutionWinograd
2524cbc6d xiaying [MNN:Bugfix] Fix bug for CPUSoftmax
44ec79b8f xiaying [MNN:Bugfix] Fix bug for CPUConvolutionDepthwise / Scale / DeconvolutionDW
21ae956ce xiaying [MNN:Bugfix] Fix bug for Multi-Batch-TiledExecutor
09a5069c7 xiaying [MNN:Speed] Add offset for src and dst
6776c6784 xiaying [MNN:Bugfix] Fix bug for trainable model
cc83ae30b xiaying [MNN:Bugfix] Fix bug for trainable model
2021-07-29 11:46:59 +08:00
|
|
|
auto srcAlign = src + srcAreaOffset * cAlign;
|
2021-04-08 15:34:23 +08:00
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auto dstAlign = dst + cAlign;
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|
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for (int hi = 0; hi < area; ++hi) {
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auto srcHeight = srcAlign + hi * 8;
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auto dstHeight = dstAlign + hi * c;
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for (int ci = 0; ci < cReamin; ++ci) {
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dstHeight[ci] = srcHeight[ci];
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}
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}
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}
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|
[MNN:Sync] Sync internal github
Commits:
8148ae75c 弗人 bugfix
14cb8ec7f 弗人 [Converter:Bugfix] bugfix for onnx depthwise convtranspose
476fbcd90 雁行 [MNN:Feature] Open AVX cast and bugfix for contentCFG.
5e26b9fd3 雁行 [Test:Feature] Add android test.
37e147b25 雁行 [MNN:Bugfix] Bugfix for floordiv.
144c185f5 tianbu.xsw hangxing fix hiai
b4fd429d6 tianbu.xsw updateCacheFile bugfix -- update cache size
d4ba572a8 雁行 [MNN:Bugfix] Support int8 in AVX2 and some Bugfix.
43061f07e xiaying [MNN:Bugfix] Fix bug for module mode run part of model
398cc5ab6 tianhang.yth refactor demo
736380600 xiaying [Express:Bugfix] Fix memory leak for copy branch
b8dab0a27 tianhang.yth MNNFloat2Int8 sizeQuad=0 crash fix
94b95bfed ghz [BugFix]1.Better method for fast pack valid check
6a921f85e xiaying [Converter:Bugfix] Fix bug for Fuseconsttosubgraph
5f77ae889 tianhang.yth numThread bugfix
a807ef879 tianhang.yth add createSession(configs, runtimeinfo) API, add pymnn demo, pymnn logcat bugfix
ad05409d3 xiaying [MNN:Bugfix] Fix bug for StaticModule's sizecompute overflow, add error print for module mode
9d81b8299 xiaying [MNN:Bugfix] Fix bug for Unique op for output size = 1
03b15e9af xiaying [Test:Feature] Add MatMulBConst Test, Fix bug for single Convert
c944a76ee tianhang.yth add auto backend and getSessionInfo @tianbu
91fa7267b ghz [BugFix]1.fix the error in eP check
bf0041f77 ghz [BugFix]1.Fix the logic error in eP check. 2.Fix the sp align error
693871672 雁行 [CPU:Bugfix] rm adrp instruction for clang compiler bug.
1b8f6b3d8 ghz 1.Fix the wronly use of r13 in arm32 version. 2.Fix the missing callee register save and restore process.
feb7ecc4c 弗人 modify log of python offline quant
040c04811 ghz [BufFix]1.replace platform-related regs. 2.fix the same problem in arm32 version
609f37db8 弗人 add log for python quant, python convert
5511dd30a ghz [BugFix]1.Add testcases in SparseConv to check all functional code branch. 2. Fix the bug in "MNNPackC4ForMatMul_A.S" in arm64, which is caused by the missing check of eReal parameter.
a93ff9280 tianhang.yth add tf.Unique op support
9729ff773 allen.lk [Bugfix] Fix one arm32 instruction syntax that clang works but gcc DOES NOT work. use index instruction instead.
297c1ad14 雁行 [Expr:Bugfix] bugfix for tensor content used by shape compute.
ef8c369e3 弗人 catch exception
07c2dd670 弗人 add dependence to setup, base64 encode url, add time log
177e590c1 弗人 [Python:Feature] add aliyun log for python quant tool
40a7928cf allen.lk [Debug:Sparse] 1.Add group parameter in torchscript converter. 2. Stop split running to avoid memory corruption when check failed in TransformGroupConvolution 3. fix Op split issue in TransformGroupConvolution
3bdea84a1 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
c3c6fbdbd allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
bc590eee4 雁行 [Converter:Bugfix] bugfix for onnx instancenormalization convert.
d8918593f tianhang.yth add auto backend and getSessionInfo @tianbu
83a198ed7 杭行 update
d0dd3e09b 杭行 update
99540202e xiaying [Converter:Optimize] Opt the tensor convert insert
333d8db82 allen.lk [Debug:Sparse] Fix All platform-register r9 / x18 issue on arm32 and arm64.
db5994672 杭行 merge
6293de7b8 tianbu.xsw fix pymnn updateCacheFile
5c2e11cb1 tianbu.xsw do updateCache in createSession
6e7641ff4 tianbu.xsw do not limit cacheFile for a model
5287a65e4 tianbu.xsw bugfix
52ba53a91 tianbu.xsw revert pymnn api
60284d830 tianbu.xsw bugfix
6d8077490 tianbu.xsw rename updateCacheFile api params
3cb172710 tianhang.yth updateCacheFile API size default value is 0
c5b69aabf tianbu.xsw updateCacheFile python api fix
5d5da7aa5 tianbu.xsw reflector code
5707877a4 雁行 [MNN:Speed] Speedup for softmax in x86 and arm.
2a211825c tianbu.xsw reflector code for updateCacheFile
76db3a835 tianbu.xsw [Cache Feature]: Add updateCacheFile API for increment cache
b06b0fd43 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
e68bfa495 雁行 [Converter:Feature] Add UUID when model convert.
a9cb935dc xiaying [MNN:Speed] Support c4nhwc for more fastblit
019f40353 xiaying [Converter:Refractor] Reduce memory used by MNNConvert(bert from 5G -> 1G)
d2a6d3d05 xiaying [MNN:Bugfix] Fix bug for identity output not find
604d0801b xiaying [Converter:Bugfix] Fix bug for FuseGeLu
4bada2367 xiaying [MNN:Refractor] SegmentMean rewrite as segment
82070e708 xiaying [MNN:Bugfix] Fix bug for GeometryBinary
e8ea4266e xiaying Fix bug for ShapeTensorConvert compute for dim = 1 error
1f1cf1991 xiaying [Tools:Bugfix] Fix system compability for fastTestOnnx
6f422efe2 xiaying [Tools:Bugfix] Remove color for checkDir for easy to dump
968f7ec88 xiaying [MNN:Speed] Support turn broadcast binary to loop
3e7aaf46f xiaying [MNN:Refractor] Set Convolution1x1Strassen support variable input/output ptr
1f65ab163 xiaying [MNN:Bugfix] Fix bug for mini mnn can't convert model
d65953d47 xiaying [MNN:Bugfix] Fix bug for armv7a - android-14 + ARM82
8b68be45c xiaying [MNN:Feature] Add segment
8a8f264f5 xiaying [Vulkan:Bugfix] Remove unuseful print
025bb0fda xiaying [Converter:Bugfix] Fix bug for oneof don't support
43900251e tianbu.xsw enable setCacheFile python API
ebfb05c74 tianbu.xsw [Metal Feature] support metallib obtain from walle transfer task
9665c0a79 弗人 add check for path in json file
c66fef224 xiaying [Converter:Bugfix] Fix bug for oneof don't support
42f192852 xiaying [MNN:Bugfix] Fix bug for not set output / saveTensor into origin Schedule's outputs
1b95354ff 雁行 [Feature]: Support shape compute for SetDiff1D, and null input for Prod.
83966d043 xiaying [Test:Feature] Add test for static module
42d1be933 xiaying [Converter:Bugfix] Fix bug for mnn convert and static model add more outputs for origin model
9067531c3 xiaying [Converter:Refractor] formatLicence
99558bed9 xiaying [Converter:Bugfix] Count the op for unuseful and controlflow
4f6da0fa7 allen.lk [Feature:GRUMultiOutput] fix multi output dimension type
c6b219bce xiaying [Converter:Feature] Turn torch converter to object
dd4e68a37 xiaying [Converter:Feature] Support dump supported ops
80b6a60a3 xiaying [Converter:Info] If has output name, print output name instead of computed
015278fc3 xiaying [MNN:Refractor] Revert IfModule's debug info
23ac967c4 xiaying Don't transform for multi-input convolution/deconvolution
b02b0d4de xiaying Fix bug for multi-input for conv1d
254d8b1d4 xiaying Fix bug for Conv1dSqueezeMove for multi input convolution 1d
d47d0b9ca xiaying Fix bug for CPURaster's fuse nc4hw4
357c5bd33 xiaying Fix ConvBiasAdd for conv's inputs op > 1
55b1f0c9c xiaying [Converter:Bugfix] Don't transform for multi-input convolution/deconvolution
1902a30f5 xiaying [Converter:Bugfix] Fix bug for Conv1dSqueezeMove for multi input convolution 1d
c23fe617b xiaying [MNN:Bugfix] Fix bug for multi-input for conv1d
8ff018426 xiaying [MNN:Bugfix] Fix bug for CPURaster's fuse nc4hw4
d4e8cd602 xiaying [Converter:Bugfix] Fix ConvBiasAdd for conv's inputs op > 1
846266b42 tianbu.xsw return when program and tune both nullptr
fd67c76a9 xiaying [Converter:Bugfix] DepthwiseConvWeightMerge only valid for tflite
e77a242c4 xiaying [Converter:Feature] Support tflite's half pixel
be054c377 tianbu.xsw [OpenCL Bugfix] do not rewrite cache when binary program is produced
51e65aa35 xiaying [Converter:Feature] Support tflite for fp16 and multi-input convolution
1ccdfdeb5 tianbu.xsw redefine svm macro name
31234d372 tianbu.xsw [OpenCL SVM] add macro for only use wrapper
d739e35da xiaying [MNN:Bugfix] Fix compile bug for grid op
24ab13c79 Joker feat(arm82): add GridSample op support in arm82 backend, AVX(by xiaying)
7b142978e xiaying [AVX512:Speed] Optimize for e <= 8
5f6febe7b tianbu.xsw code refactor
998d91b57 xiaying [Express:Speed] Merge submodule for speed
22c89146f tianhang.yth fix alpha div by zero bug and arm server compile bug
8f829a170 tianbu.xsw [OpenCL Pad] unify conv/deconv pad computing
4a28f603e xiaying [Express:Speed] Shared Const for All Submodule
c74cf28f3 xiaying [MNN:Refractor] Seperate Const init and schedule
2a1eebb7a xiaying [Tools:Bugfix] Fix bug for modelTest.py count size
72f04008c xiaying [MNN:Refractor] Delete unuseful const op
1e735d03c xiaying [Converter:Bugfix] Fix bug for static module gen
4dfadbc6e xiaying [MNN:Refractor] Rewrite const init mode
1fcf0417a xiaying [MNN:Bugfix] Fix bug for deconvolutin multi-input for multi-batch
41d429cfd xiaying [Train:Bugfix] Revert convert NCHW for mnistTrain
f947a5f01 xiaying [Test:Feature] Add testTrain
dad59b6f6 tianbu.xsw move realize code from Backend.hpp to Tensor.cpp
cf4473ad1 xiaying [Train:Bugfix] Support pad for GeometryPoolGrad
91ab13734 xiaying [MNN:Bugfix] Fix compile bug for avx512
742e80f47 xiaying [MNN:Refractor] Opt the logic for checknan judge
12543b841 xiaying [ARM82:Bugfix] Fix compile bug for ios
3a2b0a49f xiaying [ARM82:Speed] Opt Pack / Unpack for armv8
c0f1995cd xiaying [ARM82:Speed] Opt MNNPackC8FP16 and MNNUnpackC8FP16 by asm
e0fc77dcf xiaying [MNN:Speed] Fix bug for DeconvolutionWithStride for C4HW4, open it
584bec578 xiaying [MNN:Bugfix] Fix bug for format set error for onnx
d5bd4148d xiaying [MNN:Bugfix] Fix bug for format set error for onnx
b00265841 xiaying [MNN:Bugfix] Fix bug for SparseConvolutionTiledExecutor
bb09188ac xiaying [Test:Bugfix] Fix bug for run into sparse auto
426d1babd xiaying [MNN:Refractor] Small bugfix for Group convolution and pack
7d0ea1c46 tianbu.xsw [testModel Feature] support testModel.out input resize
4169c54ce xiaying [MNN:Bugfix] Fix bug for checkNAN for origin
412a82222 xiaying [Test:Bugfix] Fix bug for CheckNAN's error of matmul
319b1d425 xiaying [MNN:Bugfix] Fix bug for multi-batch for ConvInt8
050b728a6 xiaying [Test:Bugfix] Use NCHW for ConvInt8Test
7db3423a1 xiaying [OpenCL:Bugfix] Fix bug for opencl::image,opencl::buffer for C4HW4
adcec6a7f xiaying [Vulkan:Bugfix] Fix bug for invalid tensor size limit
d2a7cf4e9 xiaying [Vulkan:Bugfix] Fix bug for onCopyBuffer of nc4hw4
557bebdd3 xiaying [MNN:Bugfix] Fix bug for BF16-ARM32
bbe186649 tianbu.xsw [Update AUTO mode]: fix MNN_FORWARD_AUTO choose priority
6deb23439 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
b137590e4 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
7003558ea xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
b5f8cae5a xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
29b09e125 xiaying [MNN:Bugfix] Fix bug for arm64-bf16
42ce00770 xiaying [MNN:Bugfix] Fix bug for ARM64 - float
a2d89fc18 雁行 [Converter:Feature] Support Binary Unary for Torch.
7f1c0deb1 xiaying [MNN:Bugfix] Fix bug for Raster for Int8
8335a6f18 tianbu.xsw [OpenCL Shared Memory] modify data_format method
b359e031b xiaying [ARM82:Bugfix] Fix bug for arm82 and speed up pack / unpack c8
24bf3fc88 雁行 [Convert:Feature] Support LayerNormFuse without gamma beta.
3e629624b xiaying [MNN:Bugfix] Fix bug for float - armv7a
2b7908ec7 tianbu.xsw modify workItemSize
3cee0d413 xiaying [MNN:Bugfix] test wrong clear
9cbbfb998 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
2d7a44484 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
eb7d0cb53 xiaying [Test:Bugfix] Don't test for NC4HW4 directly
7b40ca8d1 xiaying [MNN:Bugfix] Fix bug for ConvolutionGroup
2694d8a91 xiaying [MNN:Bugfix] Fix bug for CPUGridSample
f89af60f6 xiaying [MNN:Bugfix] Fix compile bug for arm
a151abcdd xiaying [MNN:Bugfix] Fix bug for convert for int8 / int16
b254dbe61 雁行 [MNN:Bugfix] Bugfix for Conv onClone.
d08150631 xiaying [MNN:Bugfix] Fix bug for fast rcnn
e5568a0df xiaying [MNN:Bugfix] Fix bug for CPURaster treat NC4HW4 fast blit
128318933 雁行 [Raster:Bugfix] bugfix for Raster merge onResize.
03caacbea xiaying [MNN:Bugfix] fix bug for CPUDeconvolution and Convolution1x1Strassen for iw != ow
e1e3c245c xiaying [MNN:Bugfix] Fix bug for ConvolutionWinograd
2524cbc6d xiaying [MNN:Bugfix] Fix bug for CPUSoftmax
44ec79b8f xiaying [MNN:Bugfix] Fix bug for CPUConvolutionDepthwise / Scale / DeconvolutionDW
21ae956ce xiaying [MNN:Bugfix] Fix bug for Multi-Batch-TiledExecutor
09a5069c7 xiaying [MNN:Speed] Add offset for src and dst
6776c6784 xiaying [MNN:Bugfix] Fix bug for trainable model
cc83ae30b xiaying [MNN:Bugfix] Fix bug for trainable model
2021-07-29 11:46:59 +08:00
|
|
|
void MNNPackTransposeInt16C8(int16_t* dst, const int16_t* src, size_t area, size_t depth, int32_t* areaOffset) {
|
2021-04-08 15:34:23 +08:00
|
|
|
if (depth == 8) {
|
|
|
|
::memcpy(dst, src, area * depth * sizeof(int16_t));
|
|
|
|
return;
|
|
|
|
}
|
[MNN:Sync] Sync internal github
Commits:
8148ae75c 弗人 bugfix
14cb8ec7f 弗人 [Converter:Bugfix] bugfix for onnx depthwise convtranspose
476fbcd90 雁行 [MNN:Feature] Open AVX cast and bugfix for contentCFG.
5e26b9fd3 雁行 [Test:Feature] Add android test.
37e147b25 雁行 [MNN:Bugfix] Bugfix for floordiv.
144c185f5 tianbu.xsw hangxing fix hiai
b4fd429d6 tianbu.xsw updateCacheFile bugfix -- update cache size
d4ba572a8 雁行 [MNN:Bugfix] Support int8 in AVX2 and some Bugfix.
43061f07e xiaying [MNN:Bugfix] Fix bug for module mode run part of model
398cc5ab6 tianhang.yth refactor demo
736380600 xiaying [Express:Bugfix] Fix memory leak for copy branch
b8dab0a27 tianhang.yth MNNFloat2Int8 sizeQuad=0 crash fix
94b95bfed ghz [BugFix]1.Better method for fast pack valid check
6a921f85e xiaying [Converter:Bugfix] Fix bug for Fuseconsttosubgraph
5f77ae889 tianhang.yth numThread bugfix
a807ef879 tianhang.yth add createSession(configs, runtimeinfo) API, add pymnn demo, pymnn logcat bugfix
ad05409d3 xiaying [MNN:Bugfix] Fix bug for StaticModule's sizecompute overflow, add error print for module mode
9d81b8299 xiaying [MNN:Bugfix] Fix bug for Unique op for output size = 1
03b15e9af xiaying [Test:Feature] Add MatMulBConst Test, Fix bug for single Convert
c944a76ee tianhang.yth add auto backend and getSessionInfo @tianbu
91fa7267b ghz [BugFix]1.fix the error in eP check
bf0041f77 ghz [BugFix]1.Fix the logic error in eP check. 2.Fix the sp align error
693871672 雁行 [CPU:Bugfix] rm adrp instruction for clang compiler bug.
1b8f6b3d8 ghz 1.Fix the wronly use of r13 in arm32 version. 2.Fix the missing callee register save and restore process.
feb7ecc4c 弗人 modify log of python offline quant
040c04811 ghz [BufFix]1.replace platform-related regs. 2.fix the same problem in arm32 version
609f37db8 弗人 add log for python quant, python convert
5511dd30a ghz [BugFix]1.Add testcases in SparseConv to check all functional code branch. 2. Fix the bug in "MNNPackC4ForMatMul_A.S" in arm64, which is caused by the missing check of eReal parameter.
a93ff9280 tianhang.yth add tf.Unique op support
9729ff773 allen.lk [Bugfix] Fix one arm32 instruction syntax that clang works but gcc DOES NOT work. use index instruction instead.
297c1ad14 雁行 [Expr:Bugfix] bugfix for tensor content used by shape compute.
ef8c369e3 弗人 catch exception
07c2dd670 弗人 add dependence to setup, base64 encode url, add time log
177e590c1 弗人 [Python:Feature] add aliyun log for python quant tool
40a7928cf allen.lk [Debug:Sparse] 1.Add group parameter in torchscript converter. 2. Stop split running to avoid memory corruption when check failed in TransformGroupConvolution 3. fix Op split issue in TransformGroupConvolution
3bdea84a1 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
c3c6fbdbd allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
bc590eee4 雁行 [Converter:Bugfix] bugfix for onnx instancenormalization convert.
d8918593f tianhang.yth add auto backend and getSessionInfo @tianbu
83a198ed7 杭行 update
d0dd3e09b 杭行 update
99540202e xiaying [Converter:Optimize] Opt the tensor convert insert
333d8db82 allen.lk [Debug:Sparse] Fix All platform-register r9 / x18 issue on arm32 and arm64.
db5994672 杭行 merge
6293de7b8 tianbu.xsw fix pymnn updateCacheFile
5c2e11cb1 tianbu.xsw do updateCache in createSession
6e7641ff4 tianbu.xsw do not limit cacheFile for a model
5287a65e4 tianbu.xsw bugfix
52ba53a91 tianbu.xsw revert pymnn api
60284d830 tianbu.xsw bugfix
6d8077490 tianbu.xsw rename updateCacheFile api params
3cb172710 tianhang.yth updateCacheFile API size default value is 0
c5b69aabf tianbu.xsw updateCacheFile python api fix
5d5da7aa5 tianbu.xsw reflector code
5707877a4 雁行 [MNN:Speed] Speedup for softmax in x86 and arm.
2a211825c tianbu.xsw reflector code for updateCacheFile
76db3a835 tianbu.xsw [Cache Feature]: Add updateCacheFile API for increment cache
b06b0fd43 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
e68bfa495 雁行 [Converter:Feature] Add UUID when model convert.
a9cb935dc xiaying [MNN:Speed] Support c4nhwc for more fastblit
019f40353 xiaying [Converter:Refractor] Reduce memory used by MNNConvert(bert from 5G -> 1G)
d2a6d3d05 xiaying [MNN:Bugfix] Fix bug for identity output not find
604d0801b xiaying [Converter:Bugfix] Fix bug for FuseGeLu
4bada2367 xiaying [MNN:Refractor] SegmentMean rewrite as segment
82070e708 xiaying [MNN:Bugfix] Fix bug for GeometryBinary
e8ea4266e xiaying Fix bug for ShapeTensorConvert compute for dim = 1 error
1f1cf1991 xiaying [Tools:Bugfix] Fix system compability for fastTestOnnx
6f422efe2 xiaying [Tools:Bugfix] Remove color for checkDir for easy to dump
968f7ec88 xiaying [MNN:Speed] Support turn broadcast binary to loop
3e7aaf46f xiaying [MNN:Refractor] Set Convolution1x1Strassen support variable input/output ptr
1f65ab163 xiaying [MNN:Bugfix] Fix bug for mini mnn can't convert model
d65953d47 xiaying [MNN:Bugfix] Fix bug for armv7a - android-14 + ARM82
8b68be45c xiaying [MNN:Feature] Add segment
8a8f264f5 xiaying [Vulkan:Bugfix] Remove unuseful print
025bb0fda xiaying [Converter:Bugfix] Fix bug for oneof don't support
43900251e tianbu.xsw enable setCacheFile python API
ebfb05c74 tianbu.xsw [Metal Feature] support metallib obtain from walle transfer task
9665c0a79 弗人 add check for path in json file
c66fef224 xiaying [Converter:Bugfix] Fix bug for oneof don't support
42f192852 xiaying [MNN:Bugfix] Fix bug for not set output / saveTensor into origin Schedule's outputs
1b95354ff 雁行 [Feature]: Support shape compute for SetDiff1D, and null input for Prod.
83966d043 xiaying [Test:Feature] Add test for static module
42d1be933 xiaying [Converter:Bugfix] Fix bug for mnn convert and static model add more outputs for origin model
9067531c3 xiaying [Converter:Refractor] formatLicence
99558bed9 xiaying [Converter:Bugfix] Count the op for unuseful and controlflow
4f6da0fa7 allen.lk [Feature:GRUMultiOutput] fix multi output dimension type
c6b219bce xiaying [Converter:Feature] Turn torch converter to object
dd4e68a37 xiaying [Converter:Feature] Support dump supported ops
80b6a60a3 xiaying [Converter:Info] If has output name, print output name instead of computed
015278fc3 xiaying [MNN:Refractor] Revert IfModule's debug info
23ac967c4 xiaying Don't transform for multi-input convolution/deconvolution
b02b0d4de xiaying Fix bug for multi-input for conv1d
254d8b1d4 xiaying Fix bug for Conv1dSqueezeMove for multi input convolution 1d
d47d0b9ca xiaying Fix bug for CPURaster's fuse nc4hw4
357c5bd33 xiaying Fix ConvBiasAdd for conv's inputs op > 1
55b1f0c9c xiaying [Converter:Bugfix] Don't transform for multi-input convolution/deconvolution
1902a30f5 xiaying [Converter:Bugfix] Fix bug for Conv1dSqueezeMove for multi input convolution 1d
c23fe617b xiaying [MNN:Bugfix] Fix bug for multi-input for conv1d
8ff018426 xiaying [MNN:Bugfix] Fix bug for CPURaster's fuse nc4hw4
d4e8cd602 xiaying [Converter:Bugfix] Fix ConvBiasAdd for conv's inputs op > 1
846266b42 tianbu.xsw return when program and tune both nullptr
fd67c76a9 xiaying [Converter:Bugfix] DepthwiseConvWeightMerge only valid for tflite
e77a242c4 xiaying [Converter:Feature] Support tflite's half pixel
be054c377 tianbu.xsw [OpenCL Bugfix] do not rewrite cache when binary program is produced
51e65aa35 xiaying [Converter:Feature] Support tflite for fp16 and multi-input convolution
1ccdfdeb5 tianbu.xsw redefine svm macro name
31234d372 tianbu.xsw [OpenCL SVM] add macro for only use wrapper
d739e35da xiaying [MNN:Bugfix] Fix compile bug for grid op
24ab13c79 Joker feat(arm82): add GridSample op support in arm82 backend, AVX(by xiaying)
7b142978e xiaying [AVX512:Speed] Optimize for e <= 8
5f6febe7b tianbu.xsw code refactor
998d91b57 xiaying [Express:Speed] Merge submodule for speed
22c89146f tianhang.yth fix alpha div by zero bug and arm server compile bug
8f829a170 tianbu.xsw [OpenCL Pad] unify conv/deconv pad computing
4a28f603e xiaying [Express:Speed] Shared Const for All Submodule
c74cf28f3 xiaying [MNN:Refractor] Seperate Const init and schedule
2a1eebb7a xiaying [Tools:Bugfix] Fix bug for modelTest.py count size
72f04008c xiaying [MNN:Refractor] Delete unuseful const op
1e735d03c xiaying [Converter:Bugfix] Fix bug for static module gen
4dfadbc6e xiaying [MNN:Refractor] Rewrite const init mode
1fcf0417a xiaying [MNN:Bugfix] Fix bug for deconvolutin multi-input for multi-batch
41d429cfd xiaying [Train:Bugfix] Revert convert NCHW for mnistTrain
f947a5f01 xiaying [Test:Feature] Add testTrain
dad59b6f6 tianbu.xsw move realize code from Backend.hpp to Tensor.cpp
cf4473ad1 xiaying [Train:Bugfix] Support pad for GeometryPoolGrad
91ab13734 xiaying [MNN:Bugfix] Fix compile bug for avx512
742e80f47 xiaying [MNN:Refractor] Opt the logic for checknan judge
12543b841 xiaying [ARM82:Bugfix] Fix compile bug for ios
3a2b0a49f xiaying [ARM82:Speed] Opt Pack / Unpack for armv8
c0f1995cd xiaying [ARM82:Speed] Opt MNNPackC8FP16 and MNNUnpackC8FP16 by asm
e0fc77dcf xiaying [MNN:Speed] Fix bug for DeconvolutionWithStride for C4HW4, open it
584bec578 xiaying [MNN:Bugfix] Fix bug for format set error for onnx
d5bd4148d xiaying [MNN:Bugfix] Fix bug for format set error for onnx
b00265841 xiaying [MNN:Bugfix] Fix bug for SparseConvolutionTiledExecutor
bb09188ac xiaying [Test:Bugfix] Fix bug for run into sparse auto
426d1babd xiaying [MNN:Refractor] Small bugfix for Group convolution and pack
7d0ea1c46 tianbu.xsw [testModel Feature] support testModel.out input resize
4169c54ce xiaying [MNN:Bugfix] Fix bug for checkNAN for origin
412a82222 xiaying [Test:Bugfix] Fix bug for CheckNAN's error of matmul
319b1d425 xiaying [MNN:Bugfix] Fix bug for multi-batch for ConvInt8
050b728a6 xiaying [Test:Bugfix] Use NCHW for ConvInt8Test
7db3423a1 xiaying [OpenCL:Bugfix] Fix bug for opencl::image,opencl::buffer for C4HW4
adcec6a7f xiaying [Vulkan:Bugfix] Fix bug for invalid tensor size limit
d2a7cf4e9 xiaying [Vulkan:Bugfix] Fix bug for onCopyBuffer of nc4hw4
557bebdd3 xiaying [MNN:Bugfix] Fix bug for BF16-ARM32
bbe186649 tianbu.xsw [Update AUTO mode]: fix MNN_FORWARD_AUTO choose priority
6deb23439 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
b137590e4 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
7003558ea xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
b5f8cae5a xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
29b09e125 xiaying [MNN:Bugfix] Fix bug for arm64-bf16
42ce00770 xiaying [MNN:Bugfix] Fix bug for ARM64 - float
a2d89fc18 雁行 [Converter:Feature] Support Binary Unary for Torch.
7f1c0deb1 xiaying [MNN:Bugfix] Fix bug for Raster for Int8
8335a6f18 tianbu.xsw [OpenCL Shared Memory] modify data_format method
b359e031b xiaying [ARM82:Bugfix] Fix bug for arm82 and speed up pack / unpack c8
24bf3fc88 雁行 [Convert:Feature] Support LayerNormFuse without gamma beta.
3e629624b xiaying [MNN:Bugfix] Fix bug for float - armv7a
2b7908ec7 tianbu.xsw modify workItemSize
3cee0d413 xiaying [MNN:Bugfix] test wrong clear
9cbbfb998 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
2d7a44484 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
eb7d0cb53 xiaying [Test:Bugfix] Don't test for NC4HW4 directly
7b40ca8d1 xiaying [MNN:Bugfix] Fix bug for ConvolutionGroup
2694d8a91 xiaying [MNN:Bugfix] Fix bug for CPUGridSample
f89af60f6 xiaying [MNN:Bugfix] Fix compile bug for arm
a151abcdd xiaying [MNN:Bugfix] Fix bug for convert for int8 / int16
b254dbe61 雁行 [MNN:Bugfix] Bugfix for Conv onClone.
d08150631 xiaying [MNN:Bugfix] Fix bug for fast rcnn
e5568a0df xiaying [MNN:Bugfix] Fix bug for CPURaster treat NC4HW4 fast blit
128318933 雁行 [Raster:Bugfix] bugfix for Raster merge onResize.
03caacbea xiaying [MNN:Bugfix] fix bug for CPUDeconvolution and Convolution1x1Strassen for iw != ow
e1e3c245c xiaying [MNN:Bugfix] Fix bug for ConvolutionWinograd
2524cbc6d xiaying [MNN:Bugfix] Fix bug for CPUSoftmax
44ec79b8f xiaying [MNN:Bugfix] Fix bug for CPUConvolutionDepthwise / Scale / DeconvolutionDW
21ae956ce xiaying [MNN:Bugfix] Fix bug for Multi-Batch-TiledExecutor
09a5069c7 xiaying [MNN:Speed] Add offset for src and dst
6776c6784 xiaying [MNN:Bugfix] Fix bug for trainable model
cc83ae30b xiaying [MNN:Bugfix] Fix bug for trainable model
2021-07-29 11:46:59 +08:00
|
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int dstAreaOffset = areaOffset[1];
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2021-04-08 15:34:23 +08:00
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int c = (int)depth;
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int cDiv4 = c / 8;
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int cAlign = cDiv4 * 8;
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for (int hi = 0; hi < area; ++hi) {
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auto srcHeight = (src + hi * c);
|
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auto dstHeight = (dst + hi * 8);
|
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|
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for (int ci = 0; ci < cDiv4; ++ci) {
|
[MNN:Sync] Sync internal github
Commits:
8148ae75c 弗人 bugfix
14cb8ec7f 弗人 [Converter:Bugfix] bugfix for onnx depthwise convtranspose
476fbcd90 雁行 [MNN:Feature] Open AVX cast and bugfix for contentCFG.
5e26b9fd3 雁行 [Test:Feature] Add android test.
37e147b25 雁行 [MNN:Bugfix] Bugfix for floordiv.
144c185f5 tianbu.xsw hangxing fix hiai
b4fd429d6 tianbu.xsw updateCacheFile bugfix -- update cache size
d4ba572a8 雁行 [MNN:Bugfix] Support int8 in AVX2 and some Bugfix.
43061f07e xiaying [MNN:Bugfix] Fix bug for module mode run part of model
398cc5ab6 tianhang.yth refactor demo
736380600 xiaying [Express:Bugfix] Fix memory leak for copy branch
b8dab0a27 tianhang.yth MNNFloat2Int8 sizeQuad=0 crash fix
94b95bfed ghz [BugFix]1.Better method for fast pack valid check
6a921f85e xiaying [Converter:Bugfix] Fix bug for Fuseconsttosubgraph
5f77ae889 tianhang.yth numThread bugfix
a807ef879 tianhang.yth add createSession(configs, runtimeinfo) API, add pymnn demo, pymnn logcat bugfix
ad05409d3 xiaying [MNN:Bugfix] Fix bug for StaticModule's sizecompute overflow, add error print for module mode
9d81b8299 xiaying [MNN:Bugfix] Fix bug for Unique op for output size = 1
03b15e9af xiaying [Test:Feature] Add MatMulBConst Test, Fix bug for single Convert
c944a76ee tianhang.yth add auto backend and getSessionInfo @tianbu
91fa7267b ghz [BugFix]1.fix the error in eP check
bf0041f77 ghz [BugFix]1.Fix the logic error in eP check. 2.Fix the sp align error
693871672 雁行 [CPU:Bugfix] rm adrp instruction for clang compiler bug.
1b8f6b3d8 ghz 1.Fix the wronly use of r13 in arm32 version. 2.Fix the missing callee register save and restore process.
feb7ecc4c 弗人 modify log of python offline quant
040c04811 ghz [BufFix]1.replace platform-related regs. 2.fix the same problem in arm32 version
609f37db8 弗人 add log for python quant, python convert
5511dd30a ghz [BugFix]1.Add testcases in SparseConv to check all functional code branch. 2. Fix the bug in "MNNPackC4ForMatMul_A.S" in arm64, which is caused by the missing check of eReal parameter.
a93ff9280 tianhang.yth add tf.Unique op support
9729ff773 allen.lk [Bugfix] Fix one arm32 instruction syntax that clang works but gcc DOES NOT work. use index instruction instead.
297c1ad14 雁行 [Expr:Bugfix] bugfix for tensor content used by shape compute.
ef8c369e3 弗人 catch exception
07c2dd670 弗人 add dependence to setup, base64 encode url, add time log
177e590c1 弗人 [Python:Feature] add aliyun log for python quant tool
40a7928cf allen.lk [Debug:Sparse] 1.Add group parameter in torchscript converter. 2. Stop split running to avoid memory corruption when check failed in TransformGroupConvolution 3. fix Op split issue in TransformGroupConvolution
3bdea84a1 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
c3c6fbdbd allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
bc590eee4 雁行 [Converter:Bugfix] bugfix for onnx instancenormalization convert.
d8918593f tianhang.yth add auto backend and getSessionInfo @tianbu
83a198ed7 杭行 update
d0dd3e09b 杭行 update
99540202e xiaying [Converter:Optimize] Opt the tensor convert insert
333d8db82 allen.lk [Debug:Sparse] Fix All platform-register r9 / x18 issue on arm32 and arm64.
db5994672 杭行 merge
6293de7b8 tianbu.xsw fix pymnn updateCacheFile
5c2e11cb1 tianbu.xsw do updateCache in createSession
6e7641ff4 tianbu.xsw do not limit cacheFile for a model
5287a65e4 tianbu.xsw bugfix
52ba53a91 tianbu.xsw revert pymnn api
60284d830 tianbu.xsw bugfix
6d8077490 tianbu.xsw rename updateCacheFile api params
3cb172710 tianhang.yth updateCacheFile API size default value is 0
c5b69aabf tianbu.xsw updateCacheFile python api fix
5d5da7aa5 tianbu.xsw reflector code
5707877a4 雁行 [MNN:Speed] Speedup for softmax in x86 and arm.
2a211825c tianbu.xsw reflector code for updateCacheFile
76db3a835 tianbu.xsw [Cache Feature]: Add updateCacheFile API for increment cache
b06b0fd43 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
e68bfa495 雁行 [Converter:Feature] Add UUID when model convert.
a9cb935dc xiaying [MNN:Speed] Support c4nhwc for more fastblit
019f40353 xiaying [Converter:Refractor] Reduce memory used by MNNConvert(bert from 5G -> 1G)
d2a6d3d05 xiaying [MNN:Bugfix] Fix bug for identity output not find
604d0801b xiaying [Converter:Bugfix] Fix bug for FuseGeLu
4bada2367 xiaying [MNN:Refractor] SegmentMean rewrite as segment
82070e708 xiaying [MNN:Bugfix] Fix bug for GeometryBinary
e8ea4266e xiaying Fix bug for ShapeTensorConvert compute for dim = 1 error
1f1cf1991 xiaying [Tools:Bugfix] Fix system compability for fastTestOnnx
6f422efe2 xiaying [Tools:Bugfix] Remove color for checkDir for easy to dump
968f7ec88 xiaying [MNN:Speed] Support turn broadcast binary to loop
3e7aaf46f xiaying [MNN:Refractor] Set Convolution1x1Strassen support variable input/output ptr
1f65ab163 xiaying [MNN:Bugfix] Fix bug for mini mnn can't convert model
d65953d47 xiaying [MNN:Bugfix] Fix bug for armv7a - android-14 + ARM82
8b68be45c xiaying [MNN:Feature] Add segment
8a8f264f5 xiaying [Vulkan:Bugfix] Remove unuseful print
025bb0fda xiaying [Converter:Bugfix] Fix bug for oneof don't support
43900251e tianbu.xsw enable setCacheFile python API
ebfb05c74 tianbu.xsw [Metal Feature] support metallib obtain from walle transfer task
9665c0a79 弗人 add check for path in json file
c66fef224 xiaying [Converter:Bugfix] Fix bug for oneof don't support
42f192852 xiaying [MNN:Bugfix] Fix bug for not set output / saveTensor into origin Schedule's outputs
1b95354ff 雁行 [Feature]: Support shape compute for SetDiff1D, and null input for Prod.
83966d043 xiaying [Test:Feature] Add test for static module
42d1be933 xiaying [Converter:Bugfix] Fix bug for mnn convert and static model add more outputs for origin model
9067531c3 xiaying [Converter:Refractor] formatLicence
99558bed9 xiaying [Converter:Bugfix] Count the op for unuseful and controlflow
4f6da0fa7 allen.lk [Feature:GRUMultiOutput] fix multi output dimension type
c6b219bce xiaying [Converter:Feature] Turn torch converter to object
dd4e68a37 xiaying [Converter:Feature] Support dump supported ops
80b6a60a3 xiaying [Converter:Info] If has output name, print output name instead of computed
015278fc3 xiaying [MNN:Refractor] Revert IfModule's debug info
23ac967c4 xiaying Don't transform for multi-input convolution/deconvolution
b02b0d4de xiaying Fix bug for multi-input for conv1d
254d8b1d4 xiaying Fix bug for Conv1dSqueezeMove for multi input convolution 1d
d47d0b9ca xiaying Fix bug for CPURaster's fuse nc4hw4
357c5bd33 xiaying Fix ConvBiasAdd for conv's inputs op > 1
55b1f0c9c xiaying [Converter:Bugfix] Don't transform for multi-input convolution/deconvolution
1902a30f5 xiaying [Converter:Bugfix] Fix bug for Conv1dSqueezeMove for multi input convolution 1d
c23fe617b xiaying [MNN:Bugfix] Fix bug for multi-input for conv1d
8ff018426 xiaying [MNN:Bugfix] Fix bug for CPURaster's fuse nc4hw4
d4e8cd602 xiaying [Converter:Bugfix] Fix ConvBiasAdd for conv's inputs op > 1
846266b42 tianbu.xsw return when program and tune both nullptr
fd67c76a9 xiaying [Converter:Bugfix] DepthwiseConvWeightMerge only valid for tflite
e77a242c4 xiaying [Converter:Feature] Support tflite's half pixel
be054c377 tianbu.xsw [OpenCL Bugfix] do not rewrite cache when binary program is produced
51e65aa35 xiaying [Converter:Feature] Support tflite for fp16 and multi-input convolution
1ccdfdeb5 tianbu.xsw redefine svm macro name
31234d372 tianbu.xsw [OpenCL SVM] add macro for only use wrapper
d739e35da xiaying [MNN:Bugfix] Fix compile bug for grid op
24ab13c79 Joker feat(arm82): add GridSample op support in arm82 backend, AVX(by xiaying)
7b142978e xiaying [AVX512:Speed] Optimize for e <= 8
5f6febe7b tianbu.xsw code refactor
998d91b57 xiaying [Express:Speed] Merge submodule for speed
22c89146f tianhang.yth fix alpha div by zero bug and arm server compile bug
8f829a170 tianbu.xsw [OpenCL Pad] unify conv/deconv pad computing
4a28f603e xiaying [Express:Speed] Shared Const for All Submodule
c74cf28f3 xiaying [MNN:Refractor] Seperate Const init and schedule
2a1eebb7a xiaying [Tools:Bugfix] Fix bug for modelTest.py count size
72f04008c xiaying [MNN:Refractor] Delete unuseful const op
1e735d03c xiaying [Converter:Bugfix] Fix bug for static module gen
4dfadbc6e xiaying [MNN:Refractor] Rewrite const init mode
1fcf0417a xiaying [MNN:Bugfix] Fix bug for deconvolutin multi-input for multi-batch
41d429cfd xiaying [Train:Bugfix] Revert convert NCHW for mnistTrain
f947a5f01 xiaying [Test:Feature] Add testTrain
dad59b6f6 tianbu.xsw move realize code from Backend.hpp to Tensor.cpp
cf4473ad1 xiaying [Train:Bugfix] Support pad for GeometryPoolGrad
91ab13734 xiaying [MNN:Bugfix] Fix compile bug for avx512
742e80f47 xiaying [MNN:Refractor] Opt the logic for checknan judge
12543b841 xiaying [ARM82:Bugfix] Fix compile bug for ios
3a2b0a49f xiaying [ARM82:Speed] Opt Pack / Unpack for armv8
c0f1995cd xiaying [ARM82:Speed] Opt MNNPackC8FP16 and MNNUnpackC8FP16 by asm
e0fc77dcf xiaying [MNN:Speed] Fix bug for DeconvolutionWithStride for C4HW4, open it
584bec578 xiaying [MNN:Bugfix] Fix bug for format set error for onnx
d5bd4148d xiaying [MNN:Bugfix] Fix bug for format set error for onnx
b00265841 xiaying [MNN:Bugfix] Fix bug for SparseConvolutionTiledExecutor
bb09188ac xiaying [Test:Bugfix] Fix bug for run into sparse auto
426d1babd xiaying [MNN:Refractor] Small bugfix for Group convolution and pack
7d0ea1c46 tianbu.xsw [testModel Feature] support testModel.out input resize
4169c54ce xiaying [MNN:Bugfix] Fix bug for checkNAN for origin
412a82222 xiaying [Test:Bugfix] Fix bug for CheckNAN's error of matmul
319b1d425 xiaying [MNN:Bugfix] Fix bug for multi-batch for ConvInt8
050b728a6 xiaying [Test:Bugfix] Use NCHW for ConvInt8Test
7db3423a1 xiaying [OpenCL:Bugfix] Fix bug for opencl::image,opencl::buffer for C4HW4
adcec6a7f xiaying [Vulkan:Bugfix] Fix bug for invalid tensor size limit
d2a7cf4e9 xiaying [Vulkan:Bugfix] Fix bug for onCopyBuffer of nc4hw4
557bebdd3 xiaying [MNN:Bugfix] Fix bug for BF16-ARM32
bbe186649 tianbu.xsw [Update AUTO mode]: fix MNN_FORWARD_AUTO choose priority
6deb23439 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
b137590e4 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
7003558ea xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
b5f8cae5a xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
29b09e125 xiaying [MNN:Bugfix] Fix bug for arm64-bf16
42ce00770 xiaying [MNN:Bugfix] Fix bug for ARM64 - float
a2d89fc18 雁行 [Converter:Feature] Support Binary Unary for Torch.
7f1c0deb1 xiaying [MNN:Bugfix] Fix bug for Raster for Int8
8335a6f18 tianbu.xsw [OpenCL Shared Memory] modify data_format method
b359e031b xiaying [ARM82:Bugfix] Fix bug for arm82 and speed up pack / unpack c8
24bf3fc88 雁行 [Convert:Feature] Support LayerNormFuse without gamma beta.
3e629624b xiaying [MNN:Bugfix] Fix bug for float - armv7a
2b7908ec7 tianbu.xsw modify workItemSize
3cee0d413 xiaying [MNN:Bugfix] test wrong clear
9cbbfb998 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
2d7a44484 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
eb7d0cb53 xiaying [Test:Bugfix] Don't test for NC4HW4 directly
7b40ca8d1 xiaying [MNN:Bugfix] Fix bug for ConvolutionGroup
2694d8a91 xiaying [MNN:Bugfix] Fix bug for CPUGridSample
f89af60f6 xiaying [MNN:Bugfix] Fix compile bug for arm
a151abcdd xiaying [MNN:Bugfix] Fix bug for convert for int8 / int16
b254dbe61 雁行 [MNN:Bugfix] Bugfix for Conv onClone.
d08150631 xiaying [MNN:Bugfix] Fix bug for fast rcnn
e5568a0df xiaying [MNN:Bugfix] Fix bug for CPURaster treat NC4HW4 fast blit
128318933 雁行 [Raster:Bugfix] bugfix for Raster merge onResize.
03caacbea xiaying [MNN:Bugfix] fix bug for CPUDeconvolution and Convolution1x1Strassen for iw != ow
e1e3c245c xiaying [MNN:Bugfix] Fix bug for ConvolutionWinograd
2524cbc6d xiaying [MNN:Bugfix] Fix bug for CPUSoftmax
44ec79b8f xiaying [MNN:Bugfix] Fix bug for CPUConvolutionDepthwise / Scale / DeconvolutionDW
21ae956ce xiaying [MNN:Bugfix] Fix bug for Multi-Batch-TiledExecutor
09a5069c7 xiaying [MNN:Speed] Add offset for src and dst
6776c6784 xiaying [MNN:Bugfix] Fix bug for trainable model
cc83ae30b xiaying [MNN:Bugfix] Fix bug for trainable model
2021-07-29 11:46:59 +08:00
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vst1q_s16(dstHeight + ci * dstAreaOffset * 8, vld1q_s16(srcHeight + 8 * ci));
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2021-04-08 15:34:23 +08:00
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}
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}
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if (cAlign == c) {
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return;
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}
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int cReamin = c - cAlign;
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auto srcAlign = src + cAlign;
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[MNN:Sync] Sync internal github
Commits:
8148ae75c 弗人 bugfix
14cb8ec7f 弗人 [Converter:Bugfix] bugfix for onnx depthwise convtranspose
476fbcd90 雁行 [MNN:Feature] Open AVX cast and bugfix for contentCFG.
5e26b9fd3 雁行 [Test:Feature] Add android test.
37e147b25 雁行 [MNN:Bugfix] Bugfix for floordiv.
144c185f5 tianbu.xsw hangxing fix hiai
b4fd429d6 tianbu.xsw updateCacheFile bugfix -- update cache size
d4ba572a8 雁行 [MNN:Bugfix] Support int8 in AVX2 and some Bugfix.
43061f07e xiaying [MNN:Bugfix] Fix bug for module mode run part of model
398cc5ab6 tianhang.yth refactor demo
736380600 xiaying [Express:Bugfix] Fix memory leak for copy branch
b8dab0a27 tianhang.yth MNNFloat2Int8 sizeQuad=0 crash fix
94b95bfed ghz [BugFix]1.Better method for fast pack valid check
6a921f85e xiaying [Converter:Bugfix] Fix bug for Fuseconsttosubgraph
5f77ae889 tianhang.yth numThread bugfix
a807ef879 tianhang.yth add createSession(configs, runtimeinfo) API, add pymnn demo, pymnn logcat bugfix
ad05409d3 xiaying [MNN:Bugfix] Fix bug for StaticModule's sizecompute overflow, add error print for module mode
9d81b8299 xiaying [MNN:Bugfix] Fix bug for Unique op for output size = 1
03b15e9af xiaying [Test:Feature] Add MatMulBConst Test, Fix bug for single Convert
c944a76ee tianhang.yth add auto backend and getSessionInfo @tianbu
91fa7267b ghz [BugFix]1.fix the error in eP check
bf0041f77 ghz [BugFix]1.Fix the logic error in eP check. 2.Fix the sp align error
693871672 雁行 [CPU:Bugfix] rm adrp instruction for clang compiler bug.
1b8f6b3d8 ghz 1.Fix the wronly use of r13 in arm32 version. 2.Fix the missing callee register save and restore process.
feb7ecc4c 弗人 modify log of python offline quant
040c04811 ghz [BufFix]1.replace platform-related regs. 2.fix the same problem in arm32 version
609f37db8 弗人 add log for python quant, python convert
5511dd30a ghz [BugFix]1.Add testcases in SparseConv to check all functional code branch. 2. Fix the bug in "MNNPackC4ForMatMul_A.S" in arm64, which is caused by the missing check of eReal parameter.
a93ff9280 tianhang.yth add tf.Unique op support
9729ff773 allen.lk [Bugfix] Fix one arm32 instruction syntax that clang works but gcc DOES NOT work. use index instruction instead.
297c1ad14 雁行 [Expr:Bugfix] bugfix for tensor content used by shape compute.
ef8c369e3 弗人 catch exception
07c2dd670 弗人 add dependence to setup, base64 encode url, add time log
177e590c1 弗人 [Python:Feature] add aliyun log for python quant tool
40a7928cf allen.lk [Debug:Sparse] 1.Add group parameter in torchscript converter. 2. Stop split running to avoid memory corruption when check failed in TransformGroupConvolution 3. fix Op split issue in TransformGroupConvolution
3bdea84a1 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
c3c6fbdbd allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
bc590eee4 雁行 [Converter:Bugfix] bugfix for onnx instancenormalization convert.
d8918593f tianhang.yth add auto backend and getSessionInfo @tianbu
83a198ed7 杭行 update
d0dd3e09b 杭行 update
99540202e xiaying [Converter:Optimize] Opt the tensor convert insert
333d8db82 allen.lk [Debug:Sparse] Fix All platform-register r9 / x18 issue on arm32 and arm64.
db5994672 杭行 merge
6293de7b8 tianbu.xsw fix pymnn updateCacheFile
5c2e11cb1 tianbu.xsw do updateCache in createSession
6e7641ff4 tianbu.xsw do not limit cacheFile for a model
5287a65e4 tianbu.xsw bugfix
52ba53a91 tianbu.xsw revert pymnn api
60284d830 tianbu.xsw bugfix
6d8077490 tianbu.xsw rename updateCacheFile api params
3cb172710 tianhang.yth updateCacheFile API size default value is 0
c5b69aabf tianbu.xsw updateCacheFile python api fix
5d5da7aa5 tianbu.xsw reflector code
5707877a4 雁行 [MNN:Speed] Speedup for softmax in x86 and arm.
2a211825c tianbu.xsw reflector code for updateCacheFile
76db3a835 tianbu.xsw [Cache Feature]: Add updateCacheFile API for increment cache
b06b0fd43 allen.lk [Debug:Sparse] Fix and warning one kind of segmentfault cause by memory corruption when resize ConvolutionWinograd. Avoid to use some registers as arm restriction.
e68bfa495 雁行 [Converter:Feature] Add UUID when model convert.
a9cb935dc xiaying [MNN:Speed] Support c4nhwc for more fastblit
019f40353 xiaying [Converter:Refractor] Reduce memory used by MNNConvert(bert from 5G -> 1G)
d2a6d3d05 xiaying [MNN:Bugfix] Fix bug for identity output not find
604d0801b xiaying [Converter:Bugfix] Fix bug for FuseGeLu
4bada2367 xiaying [MNN:Refractor] SegmentMean rewrite as segment
82070e708 xiaying [MNN:Bugfix] Fix bug for GeometryBinary
e8ea4266e xiaying Fix bug for ShapeTensorConvert compute for dim = 1 error
1f1cf1991 xiaying [Tools:Bugfix] Fix system compability for fastTestOnnx
6f422efe2 xiaying [Tools:Bugfix] Remove color for checkDir for easy to dump
968f7ec88 xiaying [MNN:Speed] Support turn broadcast binary to loop
3e7aaf46f xiaying [MNN:Refractor] Set Convolution1x1Strassen support variable input/output ptr
1f65ab163 xiaying [MNN:Bugfix] Fix bug for mini mnn can't convert model
d65953d47 xiaying [MNN:Bugfix] Fix bug for armv7a - android-14 + ARM82
8b68be45c xiaying [MNN:Feature] Add segment
8a8f264f5 xiaying [Vulkan:Bugfix] Remove unuseful print
025bb0fda xiaying [Converter:Bugfix] Fix bug for oneof don't support
43900251e tianbu.xsw enable setCacheFile python API
ebfb05c74 tianbu.xsw [Metal Feature] support metallib obtain from walle transfer task
9665c0a79 弗人 add check for path in json file
c66fef224 xiaying [Converter:Bugfix] Fix bug for oneof don't support
42f192852 xiaying [MNN:Bugfix] Fix bug for not set output / saveTensor into origin Schedule's outputs
1b95354ff 雁行 [Feature]: Support shape compute for SetDiff1D, and null input for Prod.
83966d043 xiaying [Test:Feature] Add test for static module
42d1be933 xiaying [Converter:Bugfix] Fix bug for mnn convert and static model add more outputs for origin model
9067531c3 xiaying [Converter:Refractor] formatLicence
99558bed9 xiaying [Converter:Bugfix] Count the op for unuseful and controlflow
4f6da0fa7 allen.lk [Feature:GRUMultiOutput] fix multi output dimension type
c6b219bce xiaying [Converter:Feature] Turn torch converter to object
dd4e68a37 xiaying [Converter:Feature] Support dump supported ops
80b6a60a3 xiaying [Converter:Info] If has output name, print output name instead of computed
015278fc3 xiaying [MNN:Refractor] Revert IfModule's debug info
23ac967c4 xiaying Don't transform for multi-input convolution/deconvolution
b02b0d4de xiaying Fix bug for multi-input for conv1d
254d8b1d4 xiaying Fix bug for Conv1dSqueezeMove for multi input convolution 1d
d47d0b9ca xiaying Fix bug for CPURaster's fuse nc4hw4
357c5bd33 xiaying Fix ConvBiasAdd for conv's inputs op > 1
55b1f0c9c xiaying [Converter:Bugfix] Don't transform for multi-input convolution/deconvolution
1902a30f5 xiaying [Converter:Bugfix] Fix bug for Conv1dSqueezeMove for multi input convolution 1d
c23fe617b xiaying [MNN:Bugfix] Fix bug for multi-input for conv1d
8ff018426 xiaying [MNN:Bugfix] Fix bug for CPURaster's fuse nc4hw4
d4e8cd602 xiaying [Converter:Bugfix] Fix ConvBiasAdd for conv's inputs op > 1
846266b42 tianbu.xsw return when program and tune both nullptr
fd67c76a9 xiaying [Converter:Bugfix] DepthwiseConvWeightMerge only valid for tflite
e77a242c4 xiaying [Converter:Feature] Support tflite's half pixel
be054c377 tianbu.xsw [OpenCL Bugfix] do not rewrite cache when binary program is produced
51e65aa35 xiaying [Converter:Feature] Support tflite for fp16 and multi-input convolution
1ccdfdeb5 tianbu.xsw redefine svm macro name
31234d372 tianbu.xsw [OpenCL SVM] add macro for only use wrapper
d739e35da xiaying [MNN:Bugfix] Fix compile bug for grid op
24ab13c79 Joker feat(arm82): add GridSample op support in arm82 backend, AVX(by xiaying)
7b142978e xiaying [AVX512:Speed] Optimize for e <= 8
5f6febe7b tianbu.xsw code refactor
998d91b57 xiaying [Express:Speed] Merge submodule for speed
22c89146f tianhang.yth fix alpha div by zero bug and arm server compile bug
8f829a170 tianbu.xsw [OpenCL Pad] unify conv/deconv pad computing
4a28f603e xiaying [Express:Speed] Shared Const for All Submodule
c74cf28f3 xiaying [MNN:Refractor] Seperate Const init and schedule
2a1eebb7a xiaying [Tools:Bugfix] Fix bug for modelTest.py count size
72f04008c xiaying [MNN:Refractor] Delete unuseful const op
1e735d03c xiaying [Converter:Bugfix] Fix bug for static module gen
4dfadbc6e xiaying [MNN:Refractor] Rewrite const init mode
1fcf0417a xiaying [MNN:Bugfix] Fix bug for deconvolutin multi-input for multi-batch
41d429cfd xiaying [Train:Bugfix] Revert convert NCHW for mnistTrain
f947a5f01 xiaying [Test:Feature] Add testTrain
dad59b6f6 tianbu.xsw move realize code from Backend.hpp to Tensor.cpp
cf4473ad1 xiaying [Train:Bugfix] Support pad for GeometryPoolGrad
91ab13734 xiaying [MNN:Bugfix] Fix compile bug for avx512
742e80f47 xiaying [MNN:Refractor] Opt the logic for checknan judge
12543b841 xiaying [ARM82:Bugfix] Fix compile bug for ios
3a2b0a49f xiaying [ARM82:Speed] Opt Pack / Unpack for armv8
c0f1995cd xiaying [ARM82:Speed] Opt MNNPackC8FP16 and MNNUnpackC8FP16 by asm
e0fc77dcf xiaying [MNN:Speed] Fix bug for DeconvolutionWithStride for C4HW4, open it
584bec578 xiaying [MNN:Bugfix] Fix bug for format set error for onnx
d5bd4148d xiaying [MNN:Bugfix] Fix bug for format set error for onnx
b00265841 xiaying [MNN:Bugfix] Fix bug for SparseConvolutionTiledExecutor
bb09188ac xiaying [Test:Bugfix] Fix bug for run into sparse auto
426d1babd xiaying [MNN:Refractor] Small bugfix for Group convolution and pack
7d0ea1c46 tianbu.xsw [testModel Feature] support testModel.out input resize
4169c54ce xiaying [MNN:Bugfix] Fix bug for checkNAN for origin
412a82222 xiaying [Test:Bugfix] Fix bug for CheckNAN's error of matmul
319b1d425 xiaying [MNN:Bugfix] Fix bug for multi-batch for ConvInt8
050b728a6 xiaying [Test:Bugfix] Use NCHW for ConvInt8Test
7db3423a1 xiaying [OpenCL:Bugfix] Fix bug for opencl::image,opencl::buffer for C4HW4
adcec6a7f xiaying [Vulkan:Bugfix] Fix bug for invalid tensor size limit
d2a7cf4e9 xiaying [Vulkan:Bugfix] Fix bug for onCopyBuffer of nc4hw4
557bebdd3 xiaying [MNN:Bugfix] Fix bug for BF16-ARM32
bbe186649 tianbu.xsw [Update AUTO mode]: fix MNN_FORWARD_AUTO choose priority
6deb23439 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
b137590e4 xiaying [MNN:Bugfix] Fix bug for GeometryBinary don't care about NC4HW4 same size
7003558ea xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
b5f8cae5a xiaying [Converter:Bugfix] Fix bug for onnx pad for serveral case
29b09e125 xiaying [MNN:Bugfix] Fix bug for arm64-bf16
42ce00770 xiaying [MNN:Bugfix] Fix bug for ARM64 - float
a2d89fc18 雁行 [Converter:Feature] Support Binary Unary for Torch.
7f1c0deb1 xiaying [MNN:Bugfix] Fix bug for Raster for Int8
8335a6f18 tianbu.xsw [OpenCL Shared Memory] modify data_format method
b359e031b xiaying [ARM82:Bugfix] Fix bug for arm82 and speed up pack / unpack c8
24bf3fc88 雁行 [Convert:Feature] Support LayerNormFuse without gamma beta.
3e629624b xiaying [MNN:Bugfix] Fix bug for float - armv7a
2b7908ec7 tianbu.xsw modify workItemSize
3cee0d413 xiaying [MNN:Bugfix] test wrong clear
9cbbfb998 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
2d7a44484 xiaying [MNN:Bugfix] fix compile bug for c++ < 14
eb7d0cb53 xiaying [Test:Bugfix] Don't test for NC4HW4 directly
7b40ca8d1 xiaying [MNN:Bugfix] Fix bug for ConvolutionGroup
2694d8a91 xiaying [MNN:Bugfix] Fix bug for CPUGridSample
f89af60f6 xiaying [MNN:Bugfix] Fix compile bug for arm
a151abcdd xiaying [MNN:Bugfix] Fix bug for convert for int8 / int16
b254dbe61 雁行 [MNN:Bugfix] Bugfix for Conv onClone.
d08150631 xiaying [MNN:Bugfix] Fix bug for fast rcnn
e5568a0df xiaying [MNN:Bugfix] Fix bug for CPURaster treat NC4HW4 fast blit
128318933 雁行 [Raster:Bugfix] bugfix for Raster merge onResize.
03caacbea xiaying [MNN:Bugfix] fix bug for CPUDeconvolution and Convolution1x1Strassen for iw != ow
e1e3c245c xiaying [MNN:Bugfix] Fix bug for ConvolutionWinograd
2524cbc6d xiaying [MNN:Bugfix] Fix bug for CPUSoftmax
44ec79b8f xiaying [MNN:Bugfix] Fix bug for CPUConvolutionDepthwise / Scale / DeconvolutionDW
21ae956ce xiaying [MNN:Bugfix] Fix bug for Multi-Batch-TiledExecutor
09a5069c7 xiaying [MNN:Speed] Add offset for src and dst
6776c6784 xiaying [MNN:Bugfix] Fix bug for trainable model
cc83ae30b xiaying [MNN:Bugfix] Fix bug for trainable model
2021-07-29 11:46:59 +08:00
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auto dstAlign = dst + dstAreaOffset * cAlign;
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2021-04-08 15:34:23 +08:00
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for (int hi = 0; hi < area; ++hi) {
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auto srcHeight = srcAlign + hi * c;
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auto dstHeight = dstAlign + hi * 8;
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for (int i = 0; i < 8; ++i) {
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dstHeight[i] = 0;
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}
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for (int ci = 0; ci < cReamin; ++ci) {
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dstHeight[ci] = srcHeight[ci];
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}
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}
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}
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static void _MNNDeconvRunForUnitDepthWise(const FLOAT16* dst, FLOAT16* src, const FLOAT16* weight, size_t fw, size_t fh,
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size_t weight_y_step, size_t dilateX_step, size_t dilateY_step) {
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int fx, fy;
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auto src_z = src;
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auto weight_z = weight;
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Vec dstV = Vec::load(dst);
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for (fy = 0; fy < fh; ++fy) {
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auto src_y = src_z + fy * dilateY_step;
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auto weight_y = weight_z + fy * weight_y_step;
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for (fx = 0; fx < fw; ++fx) {
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Vec weight_x = Vec::load(weight_y + 8 * fx);
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Vec src_x = Vec::load(src_y + fx * dilateX_step);
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Vec::save(src_y + fx * dilateX_step, src_x + weight_x * dstV);
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}
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}
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}
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static void _MNNDeconvRunForLineDepthwise(const FLOAT16* dst, FLOAT16* src, const FLOAT16* weight, size_t width, size_t src_w_setup,
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size_t fw, size_t fh, size_t dilateX_step, size_t dilateY_step) {
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int dx;
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for (dx = 0; dx < width; ++dx) {
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auto dst_x = dst + dx * 8;
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auto src_dx = src + src_w_setup * dx;
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_MNNDeconvRunForUnitDepthWise(dst_x, src_dx, weight, fw, fh, fw * 8, dilateX_step, dilateY_step);
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}
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}
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2021-06-11 17:17:13 +08:00
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static void _MNNComputeMatMulForH_1_FP16(const float* AF, const float* BF, float* CF, const float* biasPtrF, const MatMulParam* param, size_t tId) {
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auto A = (const FLOAT16*)AF;
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auto B = (const FLOAT16*)BF;
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auto C = (FLOAT16*)CF;
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auto biasPtr = (const FLOAT16*)biasPtrF;
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int e = param->e;
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int l = param->l;
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int numberThread = param->numberThread;
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float biasValue = 0.0f;
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if (nullptr != biasPtr) {
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biasValue = biasPtr[0];
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}
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if (param->ATranspose) {
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auto eC4 = e / 8;
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auto eR = e % 8;
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for (int y=tId; y<eC4; y+=numberThread) {
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Vec sumValue = Vec(biasValue);
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auto srcY = A + y * 8;
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for (int x=0; x<l; ++x) {
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sumValue = sumValue + Vec::load(srcY + x * e) * Vec(B[x]);
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}
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Vec::save(C + 8 * y, sumValue);
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}
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if (0 == tId && eR > 0) {
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Vec sumValue = Vec(biasValue);
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auto srcY = A + eC4 * 8;
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FLOAT16 AR[8];
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for (int x=0; x<l; ++x) {
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::memcpy(AR, srcY + x * e, eR * sizeof(int16_t));
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sumValue = sumValue + Vec::load(AR) * Vec(B[x]);
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}
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FLOAT16 CR[8];
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Vec::save(CR, sumValue);
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::memcpy(C + 8 * eC4, CR, eR * sizeof(int16_t));
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}
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return;
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}
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auto lC4 = l / 8;
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auto lR = l % 8;
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for (int y=tId; y<e; y+=numberThread) {
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Vec sumValue = Vec(biasValue);
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auto srcY = A + y * l;
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for (int x=0; x<lC4; ++x) {
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sumValue = sumValue + Vec::load(srcY + 8 * x) * Vec::load(B + 8 * x);
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}
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if (lR > 0) {
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FLOAT16 AR[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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FLOAT16 BR[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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::memcpy(AR, srcY + lC4 * 8, lR * sizeof(int16_t));
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::memcpy(BR, B + 8 * lC4, lR * sizeof(int16_t));
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sumValue = sumValue + Vec::load(AR) * Vec::load(BR);
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}
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float sumSingle = sumValue[0] + sumValue[1] + sumValue[2] + sumValue[3] + sumValue[4] + sumValue[5] + sumValue[6] + sumValue[7];
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C[y] = sumSingle;
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}
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}
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static void _MNNComputeMatMulForE_1_FP16(const float* AF, const float* BF, float* CF, const float* biasPtrF, const MatMulParam* param, size_t tId) {
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auto l = param->l;
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auto h = param->h;
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auto numberThread = param->numberThread;
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auto lC4 = l / 8;
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auto lR = l % 8;
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auto A = (const FLOAT16*)AF;
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auto B = (const FLOAT16*)BF;
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auto C = (FLOAT16*)CF;
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auto biasPtr = (const FLOAT16*)biasPtrF;
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if (param->BTranspose) {
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for (int y=tId; y<h; y+=numberThread) {
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Vec sumValue = Vec(0.0f);
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auto by = B + y * l;
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for (int x=0; x<lC4; ++x) {
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sumValue = sumValue + Vec::load(A + x * 8) * Vec::load(by + x * 8);
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}
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if (lR > 0) {
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FLOAT16 AR[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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FLOAT16 BR[8] = {0, 0, 0, 0, 0, 0, 0, 0};
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::memcpy(AR, A + lC4 * 8, lR * sizeof(int16_t));
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::memcpy(BR, by + 8 * lC4, lR * sizeof(int16_t));
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sumValue = sumValue + Vec::load(AR) * Vec::load(BR);
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}
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float sumRemain = sumValue[0] + sumValue[1] + sumValue[2] + sumValue[3] + sumValue[4] + sumValue[5] + sumValue[6] + sumValue[7];
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if (nullptr != biasPtr) {
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sumRemain += biasPtr[y];
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}
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C[y] = sumRemain;
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}
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} else {
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auto hC4 = h / 8;
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auto hR = h % 8;
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for (int y=tId; y<hC4; y+=numberThread) {
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|
|
auto bs = B + 8 * y;
|
|
|
|
Vec sumValue = Vec(0.0f);
|
|
|
|
if (biasPtr != nullptr) {
|
|
|
|
sumValue = Vec::load(biasPtr + 8 * y);
|
|
|
|
}
|
|
|
|
auto srcY = A + y * l * 8;
|
|
|
|
for (int x=0; x<l; ++x) {
|
|
|
|
sumValue = sumValue + Vec(A[x]) * Vec::load(bs + h * x);
|
|
|
|
}
|
|
|
|
Vec::save(C + 8 * y, sumValue);
|
|
|
|
}
|
|
|
|
if (tId == 0 && hR > 0) {
|
|
|
|
auto bs = B + 8 * hC4;
|
|
|
|
Vec sumValue = Vec(0.0f);
|
|
|
|
if (biasPtr != nullptr) {
|
|
|
|
FLOAT16 biasTemp[8];
|
|
|
|
::memcpy(biasTemp, biasPtr + 8 * hC4, hR * sizeof(int16_t));
|
|
|
|
sumValue = Vec::load(biasTemp);
|
|
|
|
}
|
|
|
|
auto srcY = A + 8 * hC4 * l;
|
|
|
|
FLOAT16 bTemp[8];
|
|
|
|
for (int x=0; x<l; ++x) {
|
|
|
|
::memcpy(bTemp, bs + h * x, hR * sizeof(int16_t));
|
|
|
|
sumValue = sumValue + Vec(A[x]) * Vec::load(bTemp);
|
|
|
|
}
|
|
|
|
FLOAT16 cTemp[8];
|
|
|
|
Vec::save(cTemp, sumValue);
|
|
|
|
::memcpy(C + 8 * hC4, cTemp, hR * sizeof(int16_t));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-04-08 15:34:23 +08:00
|
|
|
static CoreFunctions* gInstance = nullptr;
|
2021-06-11 17:17:13 +08:00
|
|
|
|
2021-04-08 15:34:23 +08:00
|
|
|
bool Arm82Functions::init() {
|
2021-06-11 17:17:13 +08:00
|
|
|
using Vec = MNN::Math::Vec<FLOAT16, 8>;
|
2024-04-19 11:58:21 +08:00
|
|
|
auto origin = MNNGetCoreFunctions();
|
2021-06-11 17:17:13 +08:00
|
|
|
#define FUNC_PTR_ASSIGN(dst, src) dst = (decltype(dst))(src)
|
2021-04-08 15:34:23 +08:00
|
|
|
gInstance = new CoreFunctions;
|
2021-09-18 15:52:30 +08:00
|
|
|
|
2024-08-24 15:46:21 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNFp32ToFp8, MNNFp32ToFp8);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNFp16ToFp8, MNNFp16ToFp8);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNFp8ToFp32, MNNFp8ToFp32);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNFp8ToFp16, MNNFp8ToFp16);
|
|
|
|
|
2021-04-08 15:34:23 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNFp32ToLowp, MNNQuantizeFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNLowpToFp32, MNNDequantizeFP16);
|
|
|
|
gInstance->bytes = 2;
|
2021-09-18 15:52:30 +08:00
|
|
|
|
2021-04-08 15:34:23 +08:00
|
|
|
// Packed
|
|
|
|
gInstance->pack = 8;
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackCUnit, MNNPackC8FP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNUnpackCUnit, MNNUnPackC8FP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackCUnitTranspose, MNNPackTransposeInt16C8);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNUnpackCUnitTranspose, MNNUnpackTransposeInt16C8);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNConvRunForLineDepthwise, MNNConvRunForLineDepthwiseFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNAxByClampBroadcastUnit, MNNAxByClampBroadcastC8FP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNMatrixSub, MNNMatrixSubFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNMatrixAdd, MNNMatrixAddFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNStrassenMergeCFunction, ARM82StrassenMerge);
|
2024-07-22 19:51:53 +08:00
|
|
|
#ifdef MNN_LOW_MEMORY
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNDynamicUpdateConvBiasScale, origin->MNNDynamicUpdateConvBiasScale);
|
|
|
|
#endif
|
2021-04-08 15:34:23 +08:00
|
|
|
gInstance->penalty = 2.0f;
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNScaleAndAddBias, MNNScaleAndAddBiasFP16);
|
2021-06-23 14:10:31 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNGridSampleComputeCord, MNNGridSampleComputeCordFP16);
|
2023-12-04 11:12:20 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNGridSampleInterp, MNNGridSampleInterp);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNGridSampleInterpGrad, MNNGridSampleInterpGrad);
|
2024-04-19 11:58:21 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNGridSampleComputeCord3D, MNNGridSampleComputeCord3DFp16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNGridSampleInterp3D, MNNGridSampleInterp3D);
|
2022-01-29 18:03:25 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNRoiPoolingMax, MNNRoiPoolingMaxFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNRoiAlignMax, MNNRoiAlignMaxFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNRoiAlignAvg, MNNRoiAlignAvgFP16);
|
2021-04-08 15:34:23 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNCopyC4WithStride, MNNCopyC8WithStrideFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNAddC4WithStride, MNNAddC8WithStrideFP16);
|
2021-09-18 15:52:30 +08:00
|
|
|
|
2021-04-08 15:34:23 +08:00
|
|
|
// MatMul
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackedMatMul, MNNPackedMatMulFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackedMatMulRemain, MNNPackedMatMulRemainFP16);
|
2024-07-22 19:51:53 +08:00
|
|
|
#if defined(__aarch64__)
|
2024-09-12 12:57:57 +08:00
|
|
|
gInstance->supportFp16arith = origin->supportFp16arith;
|
|
|
|
gInstance->supportSDot = origin->supportSDot;
|
|
|
|
gInstance->supportI8mm = origin->supportI8mm;
|
|
|
|
#ifdef MNN_CPU_WEIGHT_DEQUANT_GEMM
|
2024-07-22 19:51:53 +08:00
|
|
|
// Weight Dequant Gemm Kernels
|
2023-06-27 10:33:16 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackedMatMul_int4, MNNPackedMatMulFP16_int4);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackedMatMulRemain_int4, MNNPackedMatMulRemainFP16_int4);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackedMatMul_int8, MNNPackedMatMulFP16_int8);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackedMatMulRemain_int8, MNNPackedMatMulRemainFP16_int8);
|
2024-09-12 12:57:57 +08:00
|
|
|
#endif
|
|
|
|
#ifdef MNN_LOW_MEMORY
|
2024-07-22 19:51:53 +08:00
|
|
|
// Dynamic Qaunt Helper Functions
|
2023-12-04 11:12:20 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNAbsMax, MNNAbsMaxFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNQuantScale, MNNQuantScaleFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNDynamicQuant, MNNDynamicQuantFP16);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNQuantSum, MNNQuantSumFP16);
|
2024-07-22 19:51:53 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNCountMaxMinValue, ARM82CountMinMaxValue);
|
|
|
|
#endif
|
2024-09-12 12:57:57 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNSumByAxisLForMatmul_A, origin->MNNSumByAxisLForMatmul_A);
|
2024-10-14 19:26:28 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNDepthwiseConvFastKernel, MNNDepthwiseConvFastKernelFP16);
|
2023-06-27 10:33:16 +08:00
|
|
|
#endif
|
2021-04-08 15:34:23 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackC4ForMatMul_A, Arm82MNNPackForMatMul_A);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNGetMatMulPackMode, Arm82MNNGetMatMulPackMode);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->MNNPackForMatMul_B, Arm82MNNPackForMatMul_B);
|
2021-06-11 17:17:13 +08:00
|
|
|
gInstance->MNNComputeMatMulForH_1 = _MNNComputeMatMulForH_1_FP16;
|
|
|
|
gInstance->MNNComputeMatMulForE_1 = _MNNComputeMatMulForE_1_FP16;
|
|
|
|
|
2021-09-18 15:52:30 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->chooseWinoSourceTransformPack, Arm82WinogradFunction::chooseWinoSourceTransformPack);
|
2022-01-04 10:50:40 +08:00
|
|
|
FUNC_PTR_ASSIGN(gInstance->chooseWinoSourceUnrollTransform, Arm82WinogradFunction::chooseSourceUnrollTransform);
|
|
|
|
FUNC_PTR_ASSIGN(gInstance->chooseWinoDestUnrollTransform, Arm82WinogradFunction::chooseWinoDestUnrollTransform);
|
2021-04-08 15:34:23 +08:00
|
|
|
|
|
|
|
gInstance->MNNDeconvRunForLineDepthwise = (decltype(gInstance->MNNDeconvRunForLineDepthwise))_MNNDeconvRunForLineDepthwise;
|
|
|
|
gInstance->MNNDeconvRunForUnitDepthWise = (decltype(gInstance->MNNDeconvRunForUnitDepthWise))_MNNDeconvRunForUnitDepthWise;
|
2021-06-11 17:17:13 +08:00
|
|
|
|
|
|
|
// Binary and Unary
|
|
|
|
gInstance->MNNSelectBinaryFunctionForFloat = Arm82BinaryFloat::select;
|
|
|
|
gInstance->MNNSelectUnaryFunctionForFloat = Arm82Unary::select;
|
|
|
|
|
|
|
|
// Relu with slope
|
|
|
|
gInstance->MNNReluWithSlopeChannel = Arm82Relu::reluWithSlopeChannel;
|
|
|
|
|
|
|
|
gInstance->MNNPoolingMax = (decltype(gInstance->MNNPoolingMax))(poolingMax<float16_t, Vec, 8, -65535>);
|
|
|
|
gInstance->MNNPoolingAvg = (decltype(gInstance->MNNPoolingAvg))(poolingAvg<float16_t, Vec, 8>);
|
2021-04-08 15:34:23 +08:00
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
CoreFunctions* Arm82Functions::get() {
|
|
|
|
return gInstance;
|
|
|
|
}
|
|
|
|
};
|
|
|
|
#endif
|