From db53f951e63ffeffd0446cef05a15103fac12d9c Mon Sep 17 00:00:00 2001 From: xiaying Date: Fri, 30 Sep 2022 10:02:52 +0800 Subject: [PATCH] [Sync] Sync Internal 2.1.2 --- CMakeLists.txt | 16 + benchmark/CMakeLists.txt | 25 +- benchmark/benchmark.cpp | 4 +- docs/_static/style.css | 3 + docs/compile/cmake.md | 2 + docs/conf.py | 3 + docs/cpp/ImageProcess.md | 2 +- docs/inference/module.md | 9 +- docs/inference/python.md | 9 + docs/inference/session.md | 2 + docs/pymnn/Tensor.md | 13 +- docs/pymnn/expr.md | 94 +- express/CMakeLists.txt | 18 +- express/Executor.cpp | 5 +- express/Expr.cpp | 1 + express/module/IfModule.cpp | 9 +- express/module/Module.cpp | 21 +- express/module/StaticModule.cpp | 34 +- include/MNN/Interpreter.hpp | 4 +- include/MNN/MNNDefine.h | 2 +- include/MNN/Tensor.hpp | 6 +- include/MNN/expr/Expr.hpp | 3 +- project/ios/MNN.xcodeproj/project.pbxproj | 12 + pymnn/pip_package/build_deps.py | 2 +- pymnn/src/MNN.cc | 23 +- pymnn/src/expr.h | 8 +- pymnn/test/unit_test.py | 4 + schema/current/TensorflowOp_generated.h | 28 +- schema/default/TensorflowOp.fbs | 3 + .../backend/coreml/execution/CoreMLBinary.cpp | 37 +- source/backend/cpu/CPUBackend.cpp | 53 +- source/backend/cpu/CPUBackend.hpp | 17 +- source/backend/cpu/CPUBinary.cpp | 24 +- source/backend/cpu/CPUBinary.hpp | 6 +- source/backend/cpu/CPUHistogram.cpp | 21 +- source/backend/cpu/CPUOPRegister.cpp | 4 +- source/backend/cpu/CPURange.cpp | 2 - source/backend/cpu/x86_x64/AVX2Functions.cpp | 2 +- .../cpu/x86_x64/FunctionDispatcher.cpp | 2 +- .../cpu/x86_x64/sse/FunctionSummary.hpp | 2 +- source/backend/cpu/x86_x64/sse/GemmInt8.cpp | 3 + .../cpu/x86_x64/sse/ImageProcessFunction.cpp | 15 +- .../backend/cpu/x86_x64/sse/MathFunctions.cpp | 10 +- source/backend/cuda/CMakeLists.txt | 20 +- source/backend/cuda/core/CUDABackend.cpp | 75 +- source/backend/cuda/core/CUDABackend.hpp | 3 +- source/backend/cuda/core/CUDATools.hpp | 167 + .../backend/cuda/core/runtime/CUDARuntime.cpp | 30 +- .../backend/cuda/execution/ArgMaxExecution.cu | 19 +- .../backend/cuda/execution/ArgMinExecution.cu | 90 + .../cuda/execution/ArgMinExecution.hpp | 33 + .../backend/cuda/execution/BinaryExecution.cu | 8 +- .../cuda/execution/BinaryExecution.hpp | 3 +- .../cuda/execution/ConvCutlassExecution.cu | 78 +- .../cuda/execution/ConvCutlassExecution.hpp | 7 +- .../cuda/execution/ConvDepthWiseExecution.cu | 328 +- .../execution/ConvSingleInputExecution.cu | 33 +- .../cuda/execution/ConvWinogradExecution.cu | 176 +- .../cuda/execution/ConvWinogradExecution.hpp | 12 +- .../cuda/execution/CutlassGemmParam.hpp | 50 +- source/backend/cuda/execution/Raster.cu | 100 +- source/backend/cuda/execution/Raster.cuh | 2 +- .../cuda/execution/RasterExecution.cpp | 141 +- .../cuda/execution/TensorCoreGemmPacked.cu | 46 +- source/backend/cuda/execution/Transpose.cu | 130 +- .../backend/cuda/execution/WinogradTrans.cuh | 155 +- source/backend/hiai/execution/NPUBinary.cpp | 99 +- source/backend/hiai/execution/NPUBinary.hpp | 2 +- source/backend/metal/AllShader.cpp | 8 +- source/backend/metal/MNNMetalContext.mm | 6 +- source/backend/metal/MetalBackend.mm | 3 +- source/backend/metal/MetalBinary.hpp | 3 +- source/backend/metal/MetalBinary.mm | 7 +- source/backend/metal/shader/MetalBinary.metal | 8 +- source/backend/nnapi/CMakeLists.txt | 20 + source/backend/nnapi/backend/NNAPIBackend.cpp | 411 ++ source/backend/nnapi/backend/NNAPIBackend.hpp | 134 + source/backend/nnapi/backend/NNAPIDefine.hpp | 23 + .../nnapi/backend/NNAPINeuralNetworks.h | 6504 +++++++++++++++++ .../backend/nnapi/backend/NNAPIOPRegister.cpp | 18 + source/backend/nnapi/backend/NNAPISymbol.cpp | 103 + source/backend/nnapi/backend/NNAPISymbol.hpp | 89 + .../backend/nnapi/execution/NNAPIBinary.cpp | 37 + .../backend/nnapi/execution/NNAPIBinary.hpp | 25 + .../nnapi/execution/NNAPICommonExecution.cpp | 53 + .../nnapi/execution/NNAPICommonExecution.hpp | 36 + .../nnapi/execution/NNAPIConvolution.cpp | 138 + .../nnapi/execution/NNAPIConvolution.hpp | 30 + source/backend/nnapi/execution/NNAPIPool.cpp | 67 + source/backend/nnapi/execution/NNAPIPool.hpp | 26 + .../backend/nnapi/execution/NNAPISoftmax.cpp | 38 + .../backend/nnapi/execution/NNAPISoftmax.hpp | 26 + source/backend/nnapi/execution/NNAPIUnary.cpp | 65 + source/backend/nnapi/execution/NNAPIUnary.hpp | 25 + .../execution/buffer/BinaryBufExecution.cpp | 6 + source/backend/opencl/execution/cl/binary.cl | 6 +- .../backend/opencl/execution/cl/binary_buf.cl | 6 +- .../opencl/execution/cl/opencl_program.cc | 192 +- .../execution/image/EltwiseExecution.cpp | 11 +- .../execution/image/EltwiseExecution.hpp | 2 +- source/backend/opengl/AllShader.cpp | 4 + source/backend/opengl/GLBinary.cpp | 2 + source/backend/opengl/GLBinary.hpp | 1 + source/backend/opengl/glsl/binary.glsl | 4 + .../backend/tensorrt/execution/TRTBinary.cpp | 10 +- .../backend/tensorrt/execution/TRTBinary.hpp | 2 + source/backend/vulkan/compiler/AllShader.cpp | 4188 ++++++----- .../backend/vulkan/execution/VulkanBinary.cpp | 11 +- .../backend/vulkan/execution/VulkanBinary.hpp | 3 +- .../vulkan/execution/glsl/binaryImage.comp | 4 + source/common/WinogradInt8Attr.hpp | 2 +- source/core/Backend.hpp | 10 +- source/core/BackendRegister.cpp | 6 + source/core/Interpreter.cpp | 5 + source/core/OpCommonUtils.cpp | 16 +- source/core/OpCommonUtils.hpp | 4 +- source/core/Pipeline.cpp | 96 +- source/core/Schedule.cpp | 8 +- source/core/Session.cpp | 29 + source/core/Session.hpp | 4 + source/core/Tensor.cpp | 12 +- source/core/WrapExecution.cpp | 79 +- source/core/WrapExecution.hpp | 4 +- source/geometry/GeometryBinary.cpp | 2 +- source/geometry/GeometryImageOp.cpp | 203 +- source/shape/ShapeConvTranspose3D.cpp | 1 - source/shape/ShapeInterp.cpp | 9 +- source/shape/ShapeInterp3D.cpp | 129 - source/shape/ShapeReduction.cpp | 31 +- source/shape/ShapeRegister.cpp | 6 +- source/shape/SizeComputer.cpp | 7 +- source/utils/InitNet.cpp | 5 +- test.sh | 2 +- test/op/ArgMaxTest.cpp | 3 + test/op/ConcatTest.cpp | 1 - .../source/optimizer/PostConverter.cpp | 3 + .../optimizer/onnxextra/OnnxUpsample.cpp | 208 +- .../postconvert/MergeReluToBinary.cpp | 53 + tools/cpp/backendTest.cpp | 3 + tools/script/register.py | 37 + 140 files changed, 12507 insertions(+), 3196 deletions(-) create mode 100644 docs/_static/style.css create mode 100644 source/backend/cuda/core/CUDATools.hpp create mode 100644 source/backend/cuda/execution/ArgMinExecution.cu create mode 100644 source/backend/cuda/execution/ArgMinExecution.hpp create mode 100644 source/backend/nnapi/CMakeLists.txt create mode 100644 source/backend/nnapi/backend/NNAPIBackend.cpp create mode 100644 source/backend/nnapi/backend/NNAPIBackend.hpp create mode 100644 source/backend/nnapi/backend/NNAPIDefine.hpp create mode 100644 source/backend/nnapi/backend/NNAPINeuralNetworks.h create mode 100644 source/backend/nnapi/backend/NNAPIOPRegister.cpp create mode 100644 source/backend/nnapi/backend/NNAPISymbol.cpp create mode 100644 source/backend/nnapi/backend/NNAPISymbol.hpp create mode 100644 source/backend/nnapi/execution/NNAPIBinary.cpp create mode 100644 source/backend/nnapi/execution/NNAPIBinary.hpp create mode 100644 source/backend/nnapi/execution/NNAPICommonExecution.cpp create mode 100644 source/backend/nnapi/execution/NNAPICommonExecution.hpp create mode 100644 source/backend/nnapi/execution/NNAPIConvolution.cpp create mode 100644 source/backend/nnapi/execution/NNAPIConvolution.hpp create mode 100644 source/backend/nnapi/execution/NNAPIPool.cpp create mode 100644 source/backend/nnapi/execution/NNAPIPool.hpp create mode 100644 source/backend/nnapi/execution/NNAPISoftmax.cpp create mode 100644 source/backend/nnapi/execution/NNAPISoftmax.hpp create mode 100644 source/backend/nnapi/execution/NNAPIUnary.cpp create mode 100644 source/backend/nnapi/execution/NNAPIUnary.hpp delete mode 100644 source/shape/ShapeInterp3D.cpp create mode 100644 tools/converter/source/optimizer/postconvert/MergeReluToBinary.cpp diff --git a/CMakeLists.txt b/CMakeLists.txt index 10071c7c2..dab02ccd3 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -186,6 +186,13 @@ option(MNN_AVX512 "Enable AVX512" OFF) option(MNN_CUDA "Enable CUDA" OFF) option(MNN_TENSORRT "Enable TensorRT" OFF) option(MNN_COREML "Enable CoreML" OFF) +option(MNN_NNAPI "Enable NNAPI" OFF) + +option(MNN_CUDA_PROFILE "Enable CUDA profile" OFF) + +if (NOT MNN_CUDA OR NOT CMAKE_SYSTEM_NAME MATCHES "^Linux") + set(MNN_CUDA_PROFILE OFF) +endif() if (MNN_USE_THREAD_POOL) message(STATUS "Use Threadpool, forbid openmp") @@ -223,12 +230,14 @@ message(STATUS "\tARM82: ${MNN_ARM82}") message(STATUS "\toneDNN: ${MNN_ONEDNN}") message(STATUS "\tTensorRT: ${MNN_TENSORRT}") message(STATUS "\tCoreML: ${MNN_COREML}") +message(STATUS "\tNNAPI: ${MNN_NNAPI}") message(STATUS "\tCUDA: ${MNN_CUDA}") message(STATUS "\tOpenMP: ${MNN_OPENMP}") message(STATUS "\tBF16: ${MNN_SUPPORT_BF16}") message(STATUS "\tThreadPool: ${MNN_USE_THREAD_POOL}") message(STATUS "\tHidden: ${MNN_HIDDEN}") message(STATUS "\tBuild Path: ${CMAKE_CURRENT_BINARY_DIR}") +message(STATUS "\tCUDA PROFILE: ${MNN_CUDA_PROFILE}") if(CMAKE_SYSTEM_NAME MATCHES "^Android" OR CMAKE_SYSTEM_NAME MATCHES "^Linux") add_definitions(-fPIC) @@ -480,6 +489,13 @@ IF(MNN_COREML) list(APPEND MNN_EXTRA_DEPENDS ${VIDEO}) ENDIF() +# NNAPI +IF(MNN_NNAPI) + add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/source/backend/nnapi/) + list(APPEND MNN_DEPS MNN_NNAPI) + list(APPEND MNN_OBJECTS_TO_LINK $) +ENDIF() + # Vulkan IF(MNN_VULKAN) add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/source/backend/vulkan/) diff --git a/benchmark/CMakeLists.txt b/benchmark/CMakeLists.txt index 43789b2b1..936dbd758 100644 --- a/benchmark/CMakeLists.txt +++ b/benchmark/CMakeLists.txt @@ -1,12 +1,31 @@ + + +set (EXTRA_INCLUDE "") +set (EXTRA_LIBS "") +set (EXTRA_OPTIONS "") + +if(MNN_CUDA_PROFILE) + set(CUDA_MIN_VERSION "9.0") + find_package(CUDA ${CUDA_MIN_VERSION}) + MESSAGE("benchmark message:CUDA_INCLUDE_DIRS:${CUDA_INCLUDE_DIRS}") + link_directories(${CUDA_INCLUDE_DIRS}/../lib/ + ${CUDA_INCLUDE_DIRS}/../lib64/) + set(EXTRA_INCLUDE ${CUDA_INCLUDE_DIRS}) + set(EXTRA_LIBS -lnvToolsExt) + set(EXTRA_OPTIONS -DMNN_CUDA_PROFILE) +endif() + + add_executable(benchmark.out ${CMAKE_CURRENT_LIST_DIR}/benchmark.cpp ${CMAKE_CURRENT_SOURCE_DIR}/tools/cpp/revertMNNModel.cpp) -target_include_directories(benchmark.out PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/tools/cpp/ ${CMAKE_CURRENT_SOURCE_DIR}/tools/) -target_link_libraries(benchmark.out ${MNN_DEPS}) +target_include_directories(benchmark.out PRIVATE ${CMAKE_CURRENT_SOURCE_DIR}/tools/cpp/ ${CMAKE_CURRENT_SOURCE_DIR}/tools/ ${EXTRA_INCLUDE}) +target_compile_options(benchmark.out PRIVATE ${EXTRA_OPTIONS}) +target_link_libraries(benchmark.out ${MNN_DEPS} ${EXTRA_LIBS}) file(GLOB_RECURSE SRC_FILES ${CMAKE_CURRENT_LIST_DIR}/exprModels/*.cpp) add_executable(benchmarkExprModels.out ${CMAKE_CURRENT_LIST_DIR}/benchmarkExprModels.cpp ${SRC_FILES}) target_include_directories(benchmarkExprModels.out PRIVATE "${CMAKE_CURRENT_LIST_DIR}/exprModels" ${CMAKE_CURRENT_SOURCE_DIR}/) target_link_libraries(benchmarkExprModels.out ${MNN_DEPS}) - + if (MSVC AND NOT MNN_BUILD_SHARED_LIBS) foreach (DEPEND ${MNN_DEPS}) target_link_options(benchmark.out PRIVATE /WHOLEARCHIVE:$) diff --git a/benchmark/benchmark.cpp b/benchmark/benchmark.cpp index c0c82dd5d..b30188c3b 100644 --- a/benchmark/benchmark.cpp +++ b/benchmark/benchmark.cpp @@ -141,6 +141,7 @@ std::vector doBench(Model& model, int loop, int warmup = 10, int forward // std::vector dims{1, 3, 224, 224}; // net->resizeTensor(input, dims); // net->resizeSession(session); + net->releaseModel(); const MNN::Backend* inBackend = net->getBackend(session, input); @@ -162,12 +163,9 @@ std::vector doBench(Model& model, int loop, int warmup = 10, int forward for (int round = 0; round < loop; round++) { auto timeBegin = getTimeInUs(); - void* host = input->map(MNN::Tensor::MAP_TENSOR_WRITE, input->getDimensionType()); input->unmap(MNN::Tensor::MAP_TENSOR_WRITE, input->getDimensionType(), host); - net->runSession(session); - host = outputTensor->map(MNN::Tensor::MAP_TENSOR_READ, outputTensor->getDimensionType()); outputTensor->unmap(MNN::Tensor::MAP_TENSOR_READ, outputTensor->getDimensionType(), host); auto timeEnd = getTimeInUs(); diff --git a/docs/_static/style.css b/docs/_static/style.css new file mode 100644 index 000000000..0b570a74a --- /dev/null +++ b/docs/_static/style.css @@ -0,0 +1,3 @@ +.wy-nav-content { + max-width: 75% !important; +} diff --git a/docs/compile/cmake.md b/docs/compile/cmake.md index 64e27229a..8af036a17 100644 --- a/docs/compile/cmake.md +++ b/docs/compile/cmake.md @@ -42,8 +42,10 @@ MNN使用CMake构建项目，CMake中的宏定义列表如下： | MNN_ONEDNN | 是否使用`oneDNN`，默认为`OFF` | | MNN_AVX512 | 是否构建`avx512`后端，默认为`OFF` | | MNN_CUDA | 是否构建`Cuda`后端，默认为`OFF` | +| MNN_CUDA_PROFILE | 是否打开CUDA profile工具，默认为`OFF` | | MNN_TENSORRT | 是否构建`TensorRT`后端，默认为`OFF` | | MNN_COREML | 是否构建`CoreML`后端，默认为`OFF` | +| MNN_NNAPI | 是否构建`NNAPI`后端，默认为`OFF` | | MNN_BUILD_BENCHMARK | 是否构建MNN的性能测试，默认为`OFF` | | MNN_BUILD_TEST | 是否构建MNN的单源测试，默认为`OFF` | | MNN_BUILD_FOR_ANDROID_COMMAND | 是否使用命令行构建`Android`，默认为`OFF` | diff --git a/docs/conf.py b/docs/conf.py index 7a5471a85..4b28cf11a 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -67,5 +67,8 @@ html_theme = 'sphinx_rtd_theme' # relative to this directory. They are copied after the builtin static files, # so a file named "default.css" will overwrite the builtin "default.css". html_static_path = ['_static'] +html_css_files = [ + 'style.css', +] needs_sphinx = '4.2.0' diff --git a/docs/cpp/ImageProcess.md b/docs/cpp/ImageProcess.md index 0065e0585..9c447b4d3 100644 --- a/docs/cpp/ImageProcess.md +++ b/docs/cpp/ImageProcess.md @@ -187,7 +187,7 @@ ErrorCode convert(const uint8_t* source, int iw, int ih, int stride, void* dest, - `oh` 输出高度 - `outputBpp` 如果是0，设置为保存和config.destFormat，默认为0 - `outputStride` 如果为0，设置为ow * outputBpp，默认为0 -- `type` 只支持halide_type_of和halide_type_of，默认为halide_type_of +- `type` 支持`halide_type_of`和`halide_type_of`，默认为`halide_type_of` 返回：结果code diff --git a/docs/inference/module.md b/docs/inference/module.md index 8f44d170f..a3d9a94b7 100644 --- a/docs/inference/module.md +++ b/docs/inference/module.md @@ -2,7 +2,7 @@ ## 概念说明 `Module`接口可以用于模型训练与模型推理 - 模型训练时用户可以继承`Module`类增加自己的实现用来训练； -- 模型推理与`Session`的区别是不需要用户显示resize，支持控制流，所以当模型中有`if``while`时必须使用`Module`推理 +- 模型推理与`Session`的区别是不需要用户显示resize，支持控制流，所以当模型中有`if`或`while`时必须使用`Module`推理 ### 相关数据结构 - `Module` Module接口的核心类，表示一个模型的虚类；实际加载模型时会创建其子类 - `Executor` 包含若干个`RuntimeManager`，提供内存管理接口，每个`Executor`必须在单线程环境下运行。默认提供全局 `Executor`，需要并发执行时，可自行创建。 @@ -10,7 +10,7 @@ - `VARP` 作为`Module`的输入输出，也是[Expr API](expr.md)中的基础数据结构 ## 工作流程 -![workflow](../_static/images/inference/Matrix.png) +创建Executor(可选) -> 创建Module -> 创建输入VARP -> 使用Module::forwad推理 -> 使用输出VARP -> 销毁Module -> 销毁Executor(可选) ### 创建Executor `Executor`给用户提供接口来配置推理后端、线程数等属性，以及做性能统计、算子执行的回调函数、内存回收等功能。 提供一个全局的Exector对象，用户不用创建或持有对象即可直接使用。 ```cpp @@ -58,7 +58,10 @@ struct Info { const Info* getInfo() const; ``` ### 执行推理 -调用`onForward`执行推理 +调用`onForward`执行推理。 + +**注意：当`Module`析构之后使用`onForward`返回的`VARP`将不可用** + ```cpp std::vector onForward(const std::vector& inputs); ``` diff --git a/docs/inference/python.md b/docs/inference/python.md index 5f4fe2050..504fc5f5d 100644 --- a/docs/inference/python.md +++ b/docs/inference/python.md @@ -1,5 +1,14 @@ # Python API使用 +## 安装 +MNN Python API可以使用[源码安装](../compile/pymnn.md)，也可以直接使用`pip`安装预编译whl包；`pip`安装用法如下： +```bash +# 外部版本安装 +pip install MNN==$version +# 公司内部版本安装 +pip install -i https://artifacts.antgroup-inc.cn/simple/ MNN-Internal==$version +``` + ## 概览 MNN在C++的基础上，增加了Python扩展。扩展单元包括两个部分： - MNN：负责推理，训练，图像处理和数值计算 diff --git a/docs/inference/session.md b/docs/inference/session.md index dbcc8be30..8eaf571a3 100644 --- a/docs/inference/session.md +++ b/docs/inference/session.md @@ -545,6 +545,8 @@ const std::map& getSessionOutputAll(const Session* session 在只有一个输出tensor时，可以在调用`getSessionOutput`时传入NULL以获取tensor。 +**注意：当`Session`析构之后使用`getSessionOutput`获取的`Tensor`将不可用** + ### 拷贝数据 **不熟悉MNN源码的用户，必须使用这种方式获取输出！！！** NCHW （适用于 Caffe / TorchScript / Onnx 转换而来的模型）示例： diff --git a/docs/pymnn/Tensor.md b/docs/pymnn/Tensor.md index b6baf7a9a..983b7fa84 100755 --- a/docs/pymnn/Tensor.md +++ b/docs/pymnn/Tensor.md @@ -62,7 +62,7 @@ Tensor是MNN V2接口中的基础数据结构，是最基本的数据封装类 ### `Tensor(shape, dtype, value_list, dimension)` 创建一个指定形状，数据类型, 数据和数据排布的Tensor, 数据拷贝自`value_list`， -能够将`list`，`tuple`，`bytes`，`ndarray`，`PyCapsule`等格式的数据转换成`Tensor` +能够将`list`，`tuple`，`bytes`，`ndarray`，`PyCapsule`，`int指针`等格式的数据转换成`Tensor` *注意：`value_list`仅在PYMNN_NUMPY_USABLE打开的情况下支持`ndarray`，移动端默认关闭* @@ -71,7 +71,7 @@ Tensor是MNN V2接口中的基础数据结构，是最基本的数据封装类 参数： - `shape:tuple` Tensor形状 - `dtype:MNN.Halide_Type_*` Tensor数据类型 -- `value_list:ndarray/tuple/list/bytes/PyCapsule` 数据 +- `value_list:ndarray/tuple/list/bytes/PyCapsule/int_addr` 数据 - `dimension:MNN.Tensor_DimensionType_*` 数据排布格式 --- @@ -176,13 +176,22 @@ Tensor是MNN V2接口中的基础数据结构，是最基本的数据封装类 ### `Example` ```python +import numpy as _np import MNN import MNN.numpy as np +data = _np.array([1., 2., 3.], dtype=_np.float32) # 创建Tensor # 通过给定的tuple创建Tensor, 参数分别为：形状，数据类型，数据，数据排布格式 t1 = MNN.Tensor((1, 3), MNN.Halide_Type_Float, (1., 2., 3.), MNN.Tensor_DimensionType_Caffe) # 通过Var创建Tensor t2 = MNN.Tensor(np.array([1., 2., 3.])) # 与t1等价 +# 通过ndarray创建Tensor +t3 = MNN.Tensor([1, 3], MNN.Halide_Type_Float, data, MNN.Tensor_DimensionType_Caffe) +# 通过bytes创建Tensor +t4 = MNN.Tensor([1, 3], MNN.Halide_Type_Float, data.tobytes(), MNN.Tensor_DimensionType_Caffe) +# 通过int类型的内存指针创建Tensor，使用该方法比直接用ndarray速度快，但是要求ndarray的内存必须连续 +t5 = MNN.Tensor([1, 3], MNN.Halide_Type_Float, data.__array_interface__['data'][0], MNN.Tensor_DimensionType_Caffe) + print(t1.getShape()) # (1, 3) print(t1.getDataType()) # print(t1.getDimensionType()) # 1 diff --git a/docs/pymnn/expr.md b/docs/pymnn/expr.md index d8ad57fd8..25b979487 100644 --- a/docs/pymnn/expr.md +++ b/docs/pymnn/expr.md @@ -18,12 +18,12 @@ expr是MNN的表达式模块，包含了一系列的表达式函数能够构造M --- ### `const(value_list, shape, data_format, dtype)` 根据输入数据创建一个`Const`类型的`Var`；该函数是创建的`Var`的最基本函数， -能够将`list`，`tuple`，`bytes`，`ndarray`，`PyCapsule`等格式的数据转换成`Var` +能够将`list`，`tuple`，`bytes`，`ndarray`，`PyCapsule`，`int指针`等格式的数据转换成`Var` *注意：`value_list`仅在PYMNN_NUMPY_USABLE打开的情况下支持`ndarray`，移动端默认关闭* 参数： -- `value_list:ndarray/list/tuple/bytes/PyCapsule` 输入数据 +- `value_list:ndarray/list/tuple/bytes/PyCapsule/int_addr` 输入数据 - `shape:[int]` 构造`Var`的形状 - `data_format:data_format` 数据排布格式，参考[data_format](Var.html#data-format) - `dtype:dtype` 数据类型，参考[dtype](Var.html#dtype) @@ -44,6 +44,8 @@ array([2, 3, 4], dtype=int32) array([97, 98, 99], dtype=uint8) >>> expr.const(MNN.Tensor([2, 3]).getData(), [2], expr.NCHW, expr.int) # PyCapsule array([2, 3], dtype=int32) +>>> expr.const(np.arange(4.0).astype(np.float32).__array_interface__['data'][0], [4], expr.NCHW, expr.float) # int_addr 该方法要求ndarray内存必须连续 +array([0., 1., 2., 3.], dtype=float32) ``` --- ### `set_thread_number(numberThread)` @@ -1336,6 +1338,94 @@ array(0) array([0, 1]) ``` +--- +### `eltwise_prod(x, y, coeff)` +逐元素对输入的变量执行乘法运算 + +参数： +- `x:Var_like` 输入变量 +- `y:Var_like` 输入变量 +- `coeff:[float]` 系数，目前仅支持`[1.,0.]`或`[]/[0.]` + +返回：`x*y`, 当`coeff=[1.,0.]`时返回`x` + +返回类型：`Var` + +示例： + +```python +>>> expr.eltwise_prod([1., 2., 3.], [2., 2., 2.], []) +array([2., 4., 6.], dtype=float32) +>>> expr.eltwise_prod([1., 2., 3.], [2., 2., 2.], [1., 0.]) +array([1., 2., 3.], dtype=float32) +``` + +--- +### `eltwise_sum(x, y, coeff)` +逐元素对输入的变量执行加法运算 + +参数： +- `x:Var_like` 输入变量 +- `y:Var_like` 输入变量 +- `coeff:[float]` 系数，目前仅支持`[1.,0.]`或`[]/[0.]` + +返回：`x+y`, 当`coeff=[1.,0.]`时返回`x` + +返回类型：`Var` + +示例： + +```python +>>> expr.eltwise_sum([1., 2., 3.], [2., 2., 2.], []) +array([3., 4., 5.], dtype=float32) +>>> expr.eltwise_sum([1., 2., 3.], [2., 2., 2.], [1., 0.]) +array([1., 2., 3.], dtype=float32) +``` + +--- +### `eltwise_sub(x, y, coeff)` +逐元素对输入的变量执行减法运算 + +参数： +- `x:Var_like` 输入变量 +- `y:Var_like` 输入变量 +- `coeff:[float]` 系数，目前仅支持`[1.,0.]`或`[]/[0.]` + +返回：`x-y`, 当`coeff=[1.,0.]`时返回`x` + +返回类型：`Var` + +示例： + +```python +>>> expr.eltwise_sub([1., 2., 3.], [2., 2., 2.], []) +array([-1., 0., 1.], dtype=float32) +>>> expr.eltwise_sub([1., 2., 3.], [2., 2., 2.], [1., 0.]) +array([1., 2., 3.], dtype=float32) +``` + +--- +### `eltwise_max(x, y, coeff)` +逐元素对输入的变量执行比较运算，取最大值 + +参数： +- `x:Var_like` 输入变量 +- `y:Var_like` 输入变量 +- `coeff:[float]` 系数，目前仅支持`[1.,0.]`或`[]/[0.]` + +返回：`max(x,y)`, 当`coeff=[1.,0.]`时返回`x` + +返回类型：`Var` + +示例： + +```python +>>> expr.eltwise_max([1., 2., 3.], [2., 2., 2.], []) +array([2., 2., 3.], dtype=float32) +>>> expr.eltwise_max([1., 2., 3.], [2., 2., 2.], [1., 0.]) +array([1., 2., 3.], dtype=float32) +``` + --- ### `cast(x, dtype=_F.float)` 返回输入数的dtype diff --git a/express/CMakeLists.txt b/express/CMakeLists.txt index 190c18ca3..c3c57938b 100644 --- a/express/CMakeLists.txt +++ b/express/CMakeLists.txt @@ -1,3 +1,17 @@ + + +set (EXTRA_LIBS "") +if(MNN_CUDA_PROFILE) + set(CUDA_MIN_VERSION "9.0") + find_package(CUDA ${CUDA_MIN_VERSION}) + + MESSAGE("cuda dir is:${CUDA_INCLUDE_DIRS}") + include_directories( + ${CUDA_INCLUDE_DIRS} + ) + set(EXTRA_LIBS ${CUDA_INCLUDE_DIRS}/../lib/libnvToolsExt.so) +endif() + file(GLOB_RECURSE MNN_EXPR_SRCS "${CMAKE_CURRENT_LIST_DIR}/*.*") option(MNN_EXPR_ENABLE_PROFILER "Support profile Expr's op cost" OFF) option(MNN_EXPR_SHAPE_EAGER "Force compute Expr's shape directly cost" OFF) @@ -17,7 +31,7 @@ IF(MNN_SEP_BUILD) else() add_library(MNN_Express SHARED ${MNN_EXPR_SRCS}) endif() - target_link_libraries(MNN_Express MNN) + target_link_libraries(MNN_Express MNN ${EXTRA_LIBS}) install(TARGETS MNN_Express LIBRARY DESTINATION lib ARCHIVE DESTINATION lib @@ -25,3 +39,5 @@ IF(MNN_SEP_BUILD) ELSE() add_library(MNN_Express OBJECT ${MNN_EXPR_SRCS}) ENDIF() + + diff --git a/express/Executor.cpp b/express/Executor.cpp index cf9609746..245f397a5 100644 --- a/express/Executor.cpp +++ b/express/Executor.cpp @@ -201,8 +201,9 @@ std::shared_ptr Executor::newExecutor(MNNForwardType type, info.type = type; info.numThread = numberThread; info.user = const_cast(&config); - std::shared_ptr bn(creator->onCreate(info)); - return std::shared_ptr(new Executor(bn, type, numberThread)); + std::shared_ptr runtime(creator->onCreate(info)); + auto executor = new Executor(runtime, type, numberThread); + return std::shared_ptr(executor); } RuntimeInfo Executor::getRuntime() { diff --git a/express/Expr.cpp b/express/Expr.cpp index 8e4131236..fc0177b81 100644 --- a/express/Expr.cpp +++ b/express/Expr.cpp @@ -638,6 +638,7 @@ void* Variable::readInternal(bool forShape) { return Executor::mapOutput(cache.get(), mFrom->mInside->mCacheOffset + mFromIndex, mFrom->mInside->mOutputTensors[mFromIndex]); } + void Variable::informDirty() { std::vector visited; mFrom->visitOutputs([&visited](EXPRP expr, int index) { diff --git a/express/module/IfModule.cpp b/express/module/IfModule.cpp index f9f9c0f55..8393d2838 100644 --- a/express/module/IfModule.cpp +++ b/express/module/IfModule.cpp @@ -8,6 +8,7 @@ #include "IfModule.hpp" #include "MNN_generated.h" + namespace MNN { namespace Express { static int _findPos(const std::vector& names, const std::string& key) { @@ -21,6 +22,8 @@ static int _findPos(const std::vector& names, const std::string& ke std::vector IfModule::onForward(const std::vector& inputs) { std::vector outputs(mOutputFromElse.size()); MNN_ASSERT(mOutputFromThen.size() == mOutputFromElse.size()); + + if (inputs[0]->readMap()[0] > 0) { std::vector subInputs(mInputForThen.size()); for (auto& p : mInputForThen) { @@ -54,12 +57,14 @@ IfModule* IfModule::create(const Op* op, const std::map& if (nullptr != op->name()) { module->setName(op->name()->str()); } + + /** Compute map index std::vector> mInputForThen; // First mElse' index, Second: inputs's index std::vector> mInputForElse; - + std::vector mOutputFromThen; std::vector mOutputFromElse; */ @@ -98,7 +103,7 @@ IfModule* IfModule::create(const Op* op, const std::map& for (int i=0; isize(); ++i) { auto data = output->GetAs(i); MNN_ASSERT(data->data()->size() == 2); - + auto thenPos = _findPos(thenG.outputs, data->data()->GetAsString(0)->str()); MNN_ASSERT(thenPos >= 0); auto elsePos = _findPos(elseG.outputs, data->data()->GetAsString(1)->str()); diff --git a/express/module/Module.cpp b/express/module/Module.cpp index f996c5d70..1b1a311c9 100644 --- a/express/module/Module.cpp +++ b/express/module/Module.cpp @@ -9,9 +9,9 @@ #include #include #include - #include "PipelineModule.hpp" #include "core/FileLoader.hpp" +#include "backend/cpu/CPUBackend.hpp" #include "MNN_generated.h" #include "Utils.hpp" #include "RuntimeAttr.hpp" @@ -202,15 +202,24 @@ public: } } #endif // MNN_INTERNAL_ENABLED + if (nullptr == mInfo->runTimeManager.get()) { + mRuntime = Executor::getRuntime().second; + } else { + mRuntime = mInfo->runTimeManager->getInside()->mRuntime.first.begin()->second; + } + } virtual ~ NetModule(){} virtual std::vector onForward(const std::vector& inputs) override { + #ifdef MNN_INTERNAL_ENABLED Timer _time; auto glo = ExecutorScope::Current(); glo->getDebugTools()->flops = 0.0f; #endif + CPURuntime* runtime = static_cast(mRuntime.get()); + runtime->clearReuseCopyTensorMap(); auto outputs = mModule->onForward(inputs); #ifdef MNN_INTERNAL_ENABLED do { @@ -237,10 +246,18 @@ public: } while(false); #endif return outputs; + } + void setRuntime(std::shared_ptr runtime) { + mRuntime = runtime; + } + virtual Module* clone(CloneContext* ctx) const override { std::shared_ptr submodule(mModule->clone(ctx)); + NetModule* module(new NetModule(submodule, mInfo, nullptr, 0, 0.0f)); + module->setRuntime(Executor::getRuntime().second); + #ifdef MNN_INTERNAL_ENABLED module->mLogInfo = mLogInfo; #endif @@ -249,9 +266,11 @@ public: const Module::Info* info() const { return mInfo.get(); } + private: std::shared_ptr mModule; std::shared_ptr mInfo; + std::shared_ptr mRuntime = nullptr; #ifdef MNN_INTERNAL_ENABLED std::map mLogInfo; #endif diff --git a/express/module/StaticModule.cpp b/express/module/StaticModule.cpp index 027886093..8d85b1edb 100644 --- a/express/module/StaticModule.cpp +++ b/express/module/StaticModule.cpp @@ -250,6 +250,7 @@ StaticModule::StaticModule(const void* buffer, size_t length, const std::vector< if (!res) { return; } + mResource->mUseContentInputs = scheduleInfo.needInputContentForShape; if (mResource->mUseContentInputs) { mResource->mModes.inputMode = Interpreter::Session_Input_User; @@ -262,6 +263,9 @@ StaticModule::StaticModule(const void* buffer, size_t length, const std::vector< mInputTensors.resize(inputs.size()); for (int i = 0; i < inputs.size(); ++i) { mInputTensors[i] = mSession->getInput(inputs[i].c_str()); +#ifdef LOG_VERBOSE + MNN_PRINT("init Staticmodule %d th input ptr:%p, hostPtr:%p, name:%s\n", i, mInputTensors[i], mInputTensors[i]->host(), inputs[i].c_str()); +#endif } mOutputTensors.resize(mResource->mOutputFromTensor.size()); for (int i = 0; i < mResource->mOutputFromTensor.size(); ++i) { @@ -274,6 +278,7 @@ StaticModule::~StaticModule() { mBackupResourceBackend = nullptr; } std::vector StaticModule::onForward(const std::vector& inputs) { + AUTOTIME; std::vector outputs(mResource->mOutputNumbers); for (auto& iter : mResource->mOutputFromInput) { @@ -315,6 +320,18 @@ std::vector StaticModule::onForward(const std::vectorbuffer().host = inputTensor->buffer().host; mInputTensors[i]->buffer().device = inputTensor->buffer().device; + + if (mResource->mUseContentInputs) { + + if (nullptr == mInputTensors[i]->buffer().host && 0 != mInputTensors[i]->buffer().device ) { + + auto exprInfo = inputs[i]->expr(); + auto inside = exprInfo.first->inside(); + auto srcPtr = inputs[i]->readMap(); + mInputTensors[i]->buffer().host = inside->mHostTensor->buffer().host; + } + } + } if (mResource->mUseContentInputs) { mSession->setNeedResize(); @@ -345,7 +362,7 @@ std::vector StaticModule::onForward(const std::vectorexpr(); - auto inside = exprInfo.first->inside(); + auto inside = exprInfo.first->inside(); auto inputTensor = inside->mOutputTensors[exprInfo.second]; if (nullptr != inside->mCache) { inputTensor = Executor::getOutput(inside->mCache.get(), inside->mCacheOffset); @@ -353,6 +370,19 @@ std::vector StaticModule::onForward(const std::vectorcopyFromHostTensor(inputTensor); } } + + +#ifdef LOG_VERBOSE + for (auto& inputTensor : mInputTensors) { + MNN_PRINT("static module, before run, input ptr:%p, hostPtr:%p, shape:", inputTensor, inputTensor->host()); + inputTensor->printShape(); + MNN_PRINT("\n"); + auto shape = inputTensor->shape(); + } + MNN_PRINT("staticmodule before run\n"); +#endif + + ErrorCode code; if (mResource->mModes.callBackMode == Interpreter::Session_Debug) { auto globalExecutor = ExecutorScope::Current(); @@ -372,6 +402,8 @@ std::vector StaticModule::onForward(const std::vectormOutputFromTensor[i]] = Express::Variable::create(Express::Expr::create(tensor, true)); } + + #ifdef MNN_INTERNAL_ENABLED auto glo = ExecutorScope::Current(); float flops = 0.0f; diff --git a/include/MNN/Interpreter.hpp b/include/MNN/Interpreter.hpp index 4a2658558..1816be125 100644 --- a/include/MNN/Interpreter.hpp +++ b/include/MNN/Interpreter.hpp @@ -94,7 +94,7 @@ protected: typedef std::function&, const std::string& /*opName*/)> TensorCallBack; typedef std::function&, const OperatorInfo*)> TensorCallBackWithInfo; -typedef std::pair>, std::shared_ptr> RuntimeInfo; +typedef std::pair< std::map>, std::shared_ptr> RuntimeInfo; /** * @brief get mnn version info. @@ -328,7 +328,7 @@ public: /** Backends in session in M, int*, length >= 1 + number of configs when create session */ BACKENDS = 2, - + /** Resize Info, int*, 0: ready to execute, 1: need malloc, 2: need resize */ RESIZE_STATUS = 3, diff --git a/include/MNN/MNNDefine.h b/include/MNN/MNNDefine.h index 5a3fee83e..eb3424ec9 100644 --- a/include/MNN/MNNDefine.h +++ b/include/MNN/MNNDefine.h @@ -69,6 +69,6 @@ MNN_ERROR("Check failed: %s ==> %s\n", #success, #log); \ #define STR(x) STR_IMP(x) #define MNN_VERSION_MAJOR 2 #define MNN_VERSION_MINOR 1 -#define MNN_VERSION_PATCH 1 +#define MNN_VERSION_PATCH 2 #define MNN_VERSION STR(MNN_VERSION_MAJOR) "." STR(MNN_VERSION_MINOR) "." STR(MNN_VERSION_PATCH) #endif /* MNNDefine_h */ diff --git a/include/MNN/Tensor.hpp b/include/MNN/Tensor.hpp index 1f08b6bb5..70cff7fe6 100644 --- a/include/MNN/Tensor.hpp +++ b/include/MNN/Tensor.hpp @@ -43,7 +43,7 @@ public: /** string handle type */ HANDLE_STRING = 1 }; - + /** Tensor map type : Read or Write*/ enum MapType { /** map Tensor for writing data*/ @@ -131,7 +131,7 @@ public: * @param deepCopy whether create new content and copy, currently only support deepCopy = false */ static Tensor* clone(const Tensor* src, bool deepCopy = false); - + /** * @brief delete tensor. * @param src tensor @@ -279,7 +279,7 @@ public: * @brief print tensor data. for DEBUG use only. */ void print() const; - + /** *@brief print tensor shape */ diff --git a/include/MNN/expr/Expr.hpp b/include/MNN/expr/Expr.hpp index e8fd51982..cc154ede9 100644 --- a/include/MNN/expr/Expr.hpp +++ b/include/MNN/expr/Expr.hpp @@ -147,7 +147,7 @@ public: static void save(const std::vector& vars, const char* fileName); static std::vector save(const std::vector& vars); static void save(const std::vector& vars, NetT* dest); - + // Pack a few Variable to compute in one pipeline static void prepareCompute(const std::vector& vars, bool forceCPU = false); static void compute(const std::vector& vars, bool forceCPU = false); @@ -158,6 +158,7 @@ public: mFrom = expr; mFromIndex = index; } + private: Variable(EXPRP expr, int index) { mFrom = expr; diff --git a/project/ios/MNN.xcodeproj/project.pbxproj b/project/ios/MNN.xcodeproj/project.pbxproj index 2203bde19..959e28187 100644 --- a/project/ios/MNN.xcodeproj/project.pbxproj +++ b/project/ios/MNN.xcodeproj/project.pbxproj @@ -736,6 +736,9 @@ C4F906B327688C3A0026B847 /* NMSModule.hpp in Headers */ = {isa = PBXBuildFile; fileRef = C4F906B127688C3A0026B847 /* NMSModule.hpp */; }; C4F906B427688C3A0026B847 /* NMSModule.cpp in Sources */ = {isa = PBXBuildFile; fileRef = C4F906B227688C3A0026B847 /* NMSModule.cpp */; }; C4FB6CB22769DF0800963B07 /* GeometryCumSum.cpp in Sources */ = {isa = PBXBuildFile; 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CEDB20E72846D07100AE9DC4 /* demo.app */ = {isa = PBXFileReference; explicitFileType = wrapper.application; includeInIndex = 0; path = demo.app; sourceTree = BUILT_PRODUCTS_DIR; }; CEDB20E92846D07100AE9DC4 /* AppDelegate.h */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.h; path = AppDelegate.h; sourceTree = ""; }; CEDB20EA2846D07100AE9DC4 /* AppDelegate.m */ = {isa = PBXFileReference; lastKnownFileType = sourcecode.c.objc; path = AppDelegate.m; sourceTree = ""; }; @@ -1818,6 +1824,8 @@ 48887410215B639D0079B12E /* cpu */ = { isa = PBXGroup; children = ( + CE9AFED428E54E3300566949 /* CPUInterp3D.cpp */, + CE9AFED528E54E3300566949 /* CPUInterp3D.hpp */, 4DCF538B2892B16300B5B393 /* CPUHistogram.cpp */, 4DCF538C2892B16400B5B393 /* CPUHistogram.hpp */, 4DF87C512887D3F20003E2D4 /* CPUSvd.hpp */, @@ -2642,6 +2650,7 @@ EBB38EC621E748B9005F76D7 /* shape */ = { isa = PBXGroup; children = ( + CE7DBFFF28E2DE6B00797689 /* ShapeConvTranspose3D.cpp */, 4DCF538F2892B17000B5B393 /* ShapeHistogram.cpp */, 4DF87C4D2887D39B0003E2D4 /* ShapeSvd.cpp */, 48925F362744AC2A00919B37 /* ShapeROIAlign.cpp */, @@ -2871,6 +2880,7 @@ 92FF03BD23AA0B5A00AC97F6 /* Int8FunctionsOpt.h in Headers */, 92FF036623AA0B5A00AC97F6 /* CPUDetectionOutput.hpp in Headers */, 92FF04BC23AA0BFB00AC97F6 /* NonCopyable.hpp in Headers */, + CE9AFED728E54E3300566949 /* CPUInterp3D.hpp in Headers */, 48FA474B23AA127B00172C3B /* Utils.hpp in Headers */, 4A224A1427D0C56E000A9260 /* ConvolutionWinogradBridge.hpp in Headers */, 4D9A935926255BDA00F9B43C /* DataStructures.pb-c.h in Headers */, @@ -3422,6 +3432,7 @@ 4D0C80E52862FC4700C7CAD6 /* CoreMLRaster.metal in Sources */, 92FF044123AA0B7100AC97F6 /* ShapeMoments.cpp in Sources */, 4D9A936026255BDA00F9B43C /* Model.pb-c.c in Sources */, + CE9AFED628E54E3300566949 /* CPUInterp3D.cpp in Sources */, 92FF03AB23AA0B5A00AC97F6 /* ConvolutionInt8Executor.cpp in Sources */, C4F906B427688C3A0026B847 /* NMSModule.cpp in Sources */, 48FA474523AA127B00172C3B /* Executor.cpp in Sources */, @@ -3483,6 +3494,7 @@ 4896D37925FE2A6B00717702 /* MNNPackedMatMulFP16.S in Sources */, 92FF02B623AA0B5A00AC97F6 /* CPUUnary.cpp in Sources */, 92FF032723AA0B5A00AC97F6 /* MNNDeconvRunForUnitDepthWise.S in Sources */, + CE7DC00028E2DE6B00797689 /* ShapeConvTranspose3D.cpp in Sources */, 92FF02CA23AA0B5A00AC97F6 /* MNNUnPackC4.S in Sources */, 48925F372744AC2A00919B37 /* ShapeROIAlign.cpp in Sources */, 92FF02E723AA0B5A00AC97F6 /* MNNDeconvRunForUnitDepthWise.S in Sources */, diff --git a/pymnn/pip_package/build_deps.py b/pymnn/pip_package/build_deps.py index 66e33e73a..29fd4c537 100644 --- a/pymnn/pip_package/build_deps.py +++ b/pymnn/pip_package/build_deps.py @@ -48,7 +48,7 @@ def build_deps(): extra_opts += ' -DMNN_INTERNAL=ON ' if IS_INTERNAL_BUILD else ' ' extra_opts += ' -DMNN_BUILD_TORCH=ON ' if IS_BUILD_TORCH else ' ' os.system('cmake ' + extra_opts + - '-DMNN_BUILD_CONVERTER=on -DMNN_BUILD_TRAIN=ON -DCMAKE_BUILD_TYPE=Debug \ + '-DMNN_BUILD_CONVERTER=on -DMNN_BUILD_TRAIN=ON -DCMAKE_BUILD_TYPE=Release \ -DMNN_BUILD_SHARED_LIBS=OFF -DMNN_AAPL_FMWK=OFF -DMNN_SEP_BUILD=OFF -DMNN_BUILD_OPENCV=ON -DMNN_IMGCODECS=ON \ -DMNN_USE_THREAD_POOL=ON -DMNN_OPENMP=OFF .. && make MNN MNNTrain MNNConvert -j4') else: diff --git a/pymnn/src/MNN.cc b/pymnn/src/MNN.cc index 76fc7851f..6d2533efe 100644 --- a/pymnn/src/MNN.cc +++ b/pymnn/src/MNN.cc @@ -1508,7 +1508,7 @@ static int PyMNNTensor_init(PyMNNTensor *self, PyObject *args, PyObject *kwds) { break; case 4: parse_res = PyArg_ParseTuple(args, "OOOl", &shape, &dataType, &data, &dimensionType) - && isInts(shape) && isVals(data); + && isInts(shape) && (isVals(data) || isInt(data)); break; default: parse_res = false; @@ -1518,7 +1518,7 @@ static int PyMNNTensor_init(PyMNNTensor *self, PyObject *args, PyObject *kwds) { "\t0. (Var)\n" "\t1. (Tensor/Var, DimensionType)\n" "\t2. ([int], DataType, DimensionType)\n" - "\t3. ([int], DataType, tuple/ndarray, DimensionType)\n"); + "\t3. ([int], DataType, ndarray/list/tuple/bytes/PyCapsule/int_addr, DimensionType)\n"); return -1; } #ifdef PYMNN_EXPR_API @@ -1589,7 +1589,7 @@ static int PyMNNTensor_init(PyMNNTensor *self, PyObject *args, PyObject *kwds) { dataSize *= i; } void *pData = NULL; - if (data && !PyCapsule_CheckExact(data)) { + if (data && !PyCapsule_CheckExact(data) && !isInt(data)) { if (PyBytes_Check(data)) { int64_t total_len = PyBytes_Size(data); if (dataSize * itemsize != total_len) { @@ -1626,15 +1626,20 @@ static int PyMNNTensor_init(PyMNNTensor *self, PyObject *args, PyObject *kwds) { } } else { // no data input, set all zeros - // pycapsule input, copy data + // pycapsule/int_addr input, copy data pData = malloc(dataSize * itemsize); - if (data && PyCapsule_CheckExact(data)) { - auto src = PyCapsule_GetPointer(data, NULL); - if (src == nullptr) { - PyMNN_ERROR_LOG("PyMNNTensor_init: PyCapsule pointer is null."); + if (data) { + void* srcPtr = nullptr; + if (PyCapsule_CheckExact(data)) { + srcPtr = PyCapsule_GetPointer(data, NULL); + } else { + srcPtr = PyLong_AsVoidPtr(data); + } + if (srcPtr == nullptr) { + PyMNN_ERROR_LOG("PyMNNTensor_init: PyCapsule/int_addr pointer is null."); return -1; } - memcpy(pData, src, dataSize * itemsize); + memcpy(pData, srcPtr, dataSize * itemsize); } else { memset(pData, 0, dataSize * itemsize); } diff --git a/pymnn/src/expr.h b/pymnn/src/expr.h index 4712f98b2..a8d7495ec 100644 --- a/pymnn/src/expr.h +++ b/pymnn/src/expr.h @@ -1243,10 +1243,10 @@ static PyObject* PyMNNExpr_const(PyObject *self, PyObject *args, PyObject *kwarg PyObject *value, *shapes, *format = nullptr /* NCHW */, *type = nullptr /* DType_FLOAT */; static char *kwlist[] = { "value_list", "shape", "data_format", "dtype", NULL }; if (!PyArg_ParseTupleAndKeywords(args, kwargs, "OO|OO", kwlist, &value, &shapes, &format, &type)) { - PyMNN_ERROR("const require args: (ndarray/list/tuple/bytes/PyCapsule, [ints], |data_format, dtype)"); + PyMNN_ERROR("const require args: (ndarray/list/tuple/bytes/PyCapsule/int_addr, [ints], |data_format, dtype)"); } - if (!isVals(value) || !isInts(shapes) || (format != nullptr && !isdata_format(format)) || (type != nullptr && !isdtype(type))) { - PyMNN_ERROR("const require args: (ndarray/list/tuple/bytes/PyCapsule, [ints], |data_format, dtype)"); + if ((!isVals(value) && !isInt(value)) || !isInts(shapes) || (format != nullptr && !isdata_format(format)) || (type != nullptr && !isdtype(type))) { + PyMNN_ERROR("const require args: (ndarray/list/tuple/bytes/PyCapsule/int_addr, [ints], |data_format, dtype)"); } auto data_format = (format == nullptr ? NCHW : toEnum(format)); auto dtype = (type == nullptr ? DType_FLOAT : toEnum(type)); @@ -1268,6 +1268,8 @@ static PyObject* PyMNNExpr_const(PyObject *self, PyObject *args, PyObject *kwarg bool need_free = false; if (PyCapsule_CheckExact(value)) { data = PyCapsule_GetPointer(value, NULL); + } else if (isInt(value)) { + data = PyLong_AsVoidPtr(value); } else if (PyBytes_Check(value)) { int64_t bytesize = PyBytes_Size(value); data = toPtr(value, DType_UINT8, bytesize); diff --git a/pymnn/test/unit_test.py b/pymnn/test/unit_test.py index cad7394bf..df7ca7a62 100644 --- a/pymnn/test/unit_test.py +++ b/pymnn/test/unit_test.py @@ -77,6 +77,8 @@ class UnitTest(unittest.TestCase): self.assertEqualArray(x.getNumpyData(), data) x = MNN.Tensor([2, 2], MNN.Halide_Type_Float, data.tobytes(), MNN.Tensor_DimensionType_Tensorflow) self.assertEqualArray(x.getNumpyData(), data) + x = MNN.Tensor([2, 2], MNN.Halide_Type_Float, data.__array_interface__['data'][0], MNN.Tensor_DimensionType_Tensorflow) + self.assertEqualArray(x.getNumpyData(), data) x = MNN.Tensor([2, 2], MNN.Halide_Type_Float, mp.array([[1., 2.], [3., 4.]]).ptr, MNN.Tensor_DimensionType_Tensorflow) self.assertEqualArray(x.getNumpyData(), data) def test_image_process(self): @@ -274,6 +276,8 @@ class UnitTest(unittest.TestCase): self.assertEqualVar(expr.const(list_data, [2, 2]), data) self.assertEqualVar(expr.const(tuple_data, [2, 2]), data) self.assertEqualVar(expr.const(data, [2, 2]), data) + self.assertEqualVar(expr.const(data.tobytes(), [2, 2]), data) + self.assertEqualVar(expr.const(data.__array_interface__['data'][0], [2, 2]), data) x = MNN.Tensor([2, 2], MNN.Halide_Type_Float, (1., 2., 3., 4.), MNN.Tensor_DimensionType_Tensorflow) self.assertEqualVar(expr.const(x.getHost(), [2, 2]), data) def test_conv2d(self): diff --git a/schema/current/TensorflowOp_generated.h b/schema/current/TensorflowOp_generated.h index 6777e5841..eadf625d1 100644 --- a/schema/current/TensorflowOp_generated.h +++ b/schema/current/TensorflowOp_generated.h @@ -586,9 +586,11 @@ struct BinaryOpT : public flatbuffers::NativeTable { typedef BinaryOp TableType; int32_t opType; DataType T; + int32_t activationType; BinaryOpT() : opType(0), - T(DataType_DT_FLOAT) { + T(DataType_DT_FLOAT), + activationType(0) { } }; @@ -603,10 +605,14 @@ struct BinaryOp FLATBUFFERS_FINAL_CLASS : private flatbuffers::Table { DataType T() const { return static_cast(GetField(6, 1)); } + int32_t activationType() const { + return GetField(8, 0); + } bool Verify(flatbuffers::Verifier &verifier) const { return VerifyTableStart(verifier) && VerifyField(verifier, 4) && VerifyField(verifier, 6) && + VerifyField(verifier, 8) && verifier.EndTable(); } BinaryOpT *UnPack(const flatbuffers::resolver_function_t *_resolver = nullptr) const; @@ -623,6 +629,9 @@ struct BinaryOpBuilder { void add_T(DataType T) { fbb_.AddElement(6, static_cast(T), 1); } + void add_activationType(int32_t activationType) { + fbb_.AddElement(8, activationType, 0); + } explicit BinaryOpBuilder(flatbuffers::FlatBufferBuilder &_fbb) : fbb_(_fbb) { start_ = fbb_.StartTable(); @@ -638,8 +647,10 @@ struct BinaryOpBuilder { inline flatbuffers::Offset CreateBinaryOp( flatbuffers::FlatBufferBuilder &_fbb, int32_t opType = 0, - DataType T = DataType_DT_FLOAT) { + DataType T = DataType_DT_FLOAT, + int32_t activationType = 0) { BinaryOpBuilder builder_(_fbb); + builder_.add_activationType(activationType); builder_.add_T(T); builder_.add_opType(opType); return builder_.Finish(); @@ -3481,6 +3492,7 @@ inline void BinaryOp::UnPackTo(BinaryOpT *_o, const flatbuffers::resolver_functi (void)_resolver; { auto _e = opType(); _o->opType = _e; }; { auto _e = T(); _o->T = _e; }; + { auto _e = activationType(); _o->activationType = _e; }; } inline flatbuffers::Offset BinaryOp::Pack(flatbuffers::FlatBufferBuilder &_fbb, const BinaryOpT* _o, const flatbuffers::rehasher_function_t *_rehasher) { @@ -3493,10 +3505,12 @@ inline flatbuffers::Offset CreateBinaryOp(flatbuffers::FlatBufferBuild struct _VectorArgs { flatbuffers::FlatBufferBuilder *__fbb; const BinaryOpT* __o; const flatbuffers::rehasher_function_t *__rehasher; } _va = { &_fbb, _o, _rehasher}; (void)_va; auto _opType = _o->opType; auto _T = _o->T; + auto _activationType = _o->activationType; return MNN::CreateBinaryOp( _fbb, _opType, - _T); + _T, + _activationType); } inline PackParamT *PackParam::UnPack(const flatbuffers::resolver_function_t *_resolver) const { @@ -4932,17 +4946,19 @@ inline const flatbuffers::TypeTable *PadValueModeTypeTable() { inline const flatbuffers::TypeTable *BinaryOpTypeTable() { static const flatbuffers::TypeCode type_codes[] = { { flatbuffers::ET_INT, 0, -1 }, - { flatbuffers::ET_INT, 0, 0 } + { flatbuffers::ET_INT, 0, 0 }, + { flatbuffers::ET_INT, 0, -1 } }; static const flatbuffers::TypeFunction type_refs[] = { DataTypeTypeTable }; static const char * const names[] = { "opType", - "T" + "T", + "activationType" }; static const flatbuffers::TypeTable tt = { - flatbuffers::ST_TABLE, 2, type_codes, type_refs, nullptr, names + flatbuffers::ST_TABLE, 3, type_codes, type_refs, nullptr, names }; return &tt; } diff --git a/schema/default/TensorflowOp.fbs b/schema/default/TensorflowOp.fbs index 33a2db096..02690ba7c 100644 --- a/schema/default/TensorflowOp.fbs +++ b/schema/default/TensorflowOp.fbs @@ -35,6 +35,9 @@ enum BinaryOpOperation : byte { table BinaryOp { opType:int; T:DataType=DT_FLOAT; + // 0 -> No Activation + // 1 -> Relu + activationType:int=0; } table PackParam { diff --git a/source/backend/coreml/execution/CoreMLBinary.cpp b/source/backend/coreml/execution/CoreMLBinary.cpp index 36d43df56..9595f52ca 100644 --- a/source/backend/coreml/execution/CoreMLBinary.cpp +++ b/source/backend/coreml/execution/CoreMLBinary.cpp @@ -182,12 +182,43 @@ ErrorCode CoreMLBinary::onResize(const std::vector &inputs, const std: MNN_ERROR("NPU Binary not support %s\n", MNN::EnumNameBinaryOpOperation(binaryType)); break; } - if (oneInput) { - setLayerInputsAndOutputs(mLayer_, {mCoreMLBackend->getTensorName(input)}, {mCoreMLBackend->getTensorName(outputs[0])}); + + std::string binartInputName; + if(oneInput) { + binartInputName = mCoreMLBackend->getTensorName(input); } else { - setLayerInputsAndOutputs(mLayer_, {mCoreMLBackend->getTensorName(inputs[0]), mCoreMLBackend->getTensorName(inputs[1])}, {mCoreMLBackend->getTensorName(outputs[0])}); + binartInputName = mCoreMLBackend->getTensorName(inputs[0]); + } + std::string binaryOutputName = mCoreMLBackend->getTensorName(outputs[0]); + int activationType = 0; + if(mOp->type() == OpType_BinaryOp) { + activationType = mOp->main_as_BinaryOp()->activationType(); + } + if (activationType == 1) { + binaryOutputName = binartInputName + "-" + binaryOutputName + "-Relu"; + } + + if (oneInput) { + setLayerInputsAndOutputs(mLayer_, {mCoreMLBackend->getTensorName(input)}, {binaryOutputName}); + } else { + setLayerInputsAndOutputs(mLayer_, {mCoreMLBackend->getTensorName(inputs[0]), mCoreMLBackend->getTensorName(inputs[1])}, {binaryOutputName}); } mCoreMLBackend->addLayer(mLayer_); + + if (activationType == 1) { + auto reluLayer = mCoreMLBackend->create(); + core_ml__specification__neural_network_layer__init(reluLayer); + mCoreMLBackend->setLayerName(reluLayer, "BinaryRelu"); + reluLayer->layer_case = CORE_ML__SPECIFICATION__NEURAL_NETWORK_LAYER__LAYER_ACTIVATION; + reluLayer->activation = mCoreMLBackend->create(); + core_ml__specification__activation_params__init(reluLayer->activation); + reluLayer->activation->nonlinearity_type_case = CORE_ML__SPECIFICATION__ACTIVATION_PARAMS__NONLINEARITY_TYPE_RE_LU; + reluLayer->activation->relu = mCoreMLBackend->create(); + core_ml__specification__activation_re_lu__init(reluLayer->activation->relu); + setLayerInputsAndOutputs(reluLayer, {binaryOutputName}, {mCoreMLBackend->getTensorName(outputs[0])}); + mCoreMLBackend->addLayer(reluLayer); + } + return NO_ERROR; } diff --git a/source/backend/cpu/CPUBackend.cpp b/source/backend/cpu/CPUBackend.cpp index 694b4254b..fbee3e971 100644 --- a/source/backend/cpu/CPUBackend.cpp +++ b/source/backend/cpu/CPUBackend.cpp @@ -82,6 +82,9 @@ CPURuntime::CPURuntime(const Backend::Info& info) { ThreadPool::active(); } #endif +#ifdef LOG_VERBOSE + MNN_PRINT("create CPURuntime:%p\n", this); +#endif } CPURuntime:: ~ CPURuntime() { #ifdef MNN_USE_THREAD_POOL @@ -96,6 +99,9 @@ float CPURuntime::onGetMemoryInMB() { return staticMemoryInMB; } + + + Backend* CPURuntime::onCreate(const BackendConfig* config) const { auto precision = mPrecision; size_t flags = mFlags; @@ -103,6 +109,10 @@ Backend* CPURuntime::onCreate(const BackendConfig* config) const { precision = config->precision; flags = config->flags; } +#ifdef LOG_VERBOSE + MNN_PRINT("cpu backend was created by runtime:%p\n", this); +#endif + #ifdef MNN_USE_ARMV82 auto core = MNNGetCoreFunctions(); if (core->supportFp16arith && precision == BackendConfig::Precision_Low) { @@ -122,6 +132,7 @@ Backend* CPURuntime::onCreate(const BackendConfig* config) const { return new AVX2Backend(this, flags); } #endif + return new CPUBackend(this, precision, MNN_FORWARD_CPU, flags); } @@ -148,6 +159,21 @@ void CPURuntime::onGabageCollect(int level) { mStaticAllocator->release(false); } + +ReuseCopyTensorMap& CPURuntime::getReuseCopyTensorMap() { + return mReuseCopyTensorMap; +} + +void CPURuntime::clearReuseCopyTensorMap() { + for (auto& iter : mReuseCopyTensorMap) { + Tensor* tensor = std::get<2>(iter.second); + if (TensorUtils::getDescribe(tensor)->useCount > 0) { + TensorUtils::getDescribe(tensor)->useCount--; + } + } + mReuseCopyTensorMap.clear(); +} + void CPURuntime::onConcurrencyBegin() const { #ifdef MNN_USE_THREAD_POOL if (mThreadNumber > 1 && mPower != BackendConfig::Power_High) { @@ -189,7 +215,10 @@ bool CPUBackend::addCreator(OpType t, Creator* c) { } CPUBackend::CPUBackend(const CPURuntime* runtime, BackendConfig::PrecisionMode precision, MNNForwardType type, size_t flags) : Backend(type) { - mRuntime = runtime; +#ifdef LOG_VERBOSE + MNN_PRINT("cpu backend create\n"); +#endif + mRuntime = const_cast(runtime); std::shared_ptr defaultAlloc(BufferAllocator::Allocator::createRecurse(runtime->mStaticAllocator.get())); mDynamicAllocator.reset(new BufferAllocator(defaultAlloc)); mStaticAllocator = runtime->mStaticAllocator; @@ -485,6 +514,9 @@ Execution* CPUBackend::onCreate(const std::vector& inputs, const std::v } return exe; } +const Runtime* CPUBackend::getRuntime() { + return mRuntime; +} bool CPUBackend::onClearBuffer() { mCache->reset(); @@ -540,6 +572,16 @@ void CPUBackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) wrapTensor->setType(dstType); } wrapTensor->buffer().host = (uint8_t*)MNNMemoryAllocAlign(getTensorSize(wrapTensor.get()) * wrapTensor->getType().bytes(), MNN_MEMORY_ALIGN_DEFAULT); + +#ifdef LOG_VERBOSE + MNN_PRINT("CPU backend copy tensor ptr:%p -> ptr:%p hostPtr:%p -> %p, format %d -> %d, dims: [", + srcTensor, dstTensor, srcTensor->host(), dstTensor->host(), TensorUtils::getDescribe(srcTensor)->dimensionFormat, TensorUtils::getDescribe(dstTensor)->dimensionFormat); + for (int i=0; idimensions(); ++i) { + MNN_PRINT("%d ", srcTensor->length(i)); + } + MNN_PRINT("]\n"); +#endif + TensorUtils::getDescribe(wrapTensor.get())->memoryType = Tensor::InsideDescribe::MEMORY_HOST; auto code = CPUCastCreator::cast(srcTensor, wrapTensor.get(), this, convertType); if (NO_ERROR != code) { @@ -556,6 +598,15 @@ void CPUBackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) } } +ReuseCopyTensorMap& CPUBackend::getReuseCopyTensorMap() { + return mRuntime->getReuseCopyTensorMap(); +} + +void CPUBackend::clearReuseCopyTensorMap() { + mRuntime->clearReuseCopyTensorMap(); +} + + class CPURuntimeCreator : public RuntimeCreator { public: virtual Runtime* onCreate(const Backend::Info& info) const override { diff --git a/source/backend/cpu/CPUBackend.hpp b/source/backend/cpu/CPUBackend.hpp index a98f4ded5..8e983efdc 100644 --- a/source/backend/cpu/CPUBackend.hpp +++ b/source/backend/cpu/CPUBackend.hpp @@ -29,6 +29,9 @@ public: virtual CompilerType onGetCompilerType() const override { return Compiler_Loop; } + MNN_PUBLIC ReuseCopyTensorMap& getReuseCopyTensorMap(); + + MNN_PUBLIC void clearReuseCopyTensorMap(); void onConcurrencyBegin() const; void onConcurrencyEnd() const; @@ -39,6 +42,7 @@ private: BackendConfig::MemoryMode mMemory; BackendConfig::PowerMode mPower; BackendConfig::PrecisionMode mPrecision; + ReuseCopyTensorMap mReuseCopyTensorMap; // Backend features // CPU features @@ -71,7 +75,6 @@ public: const CoreFunctions* functions() const { return mCoreFunctions; } - // Return element size for Tensor, conside pack int getTensorSize(const Tensor* tensor, bool multiBytes = false) const; const CoreInt8Functions* int8Functions() const { @@ -106,12 +109,22 @@ public: CPUResizeCache* getCache() const { return mCache; } + + virtual const Runtime* getRuntime() override; + + ReuseCopyTensorMap& getReuseCopyTensorMap(); + + void clearReuseCopyTensorMap(); + + #ifdef MNN_USE_THREAD_POOL inline int taskIndex() const {return mRuntime->mTaskIndex;} #endif static void initCreatorMap(); static int getBytes(const Backend* backend, const Tensor* output); static DataType getDataType(const Tensor* tensor); + + protected: MemObj* allocBuffer(int size, Tensor* dest, StorageType storageType); const CoreFunctions* mCoreFunctions; @@ -119,7 +132,7 @@ protected: private: std::shared_ptr mStaticAllocator; std::shared_ptr mDynamicAllocator; - const CPURuntime* mRuntime; + CPURuntime* mRuntime; BackendConfig::PrecisionMode mPrecisionMode; static std::map* gCreator; std::map mCachedCastTensor; diff --git a/source/backend/cpu/CPUBinary.cpp b/source/backend/cpu/CPUBinary.cpp index 43a62d942..81b3b4fc8 100644 --- a/source/backend/cpu/CPUBinary.cpp +++ b/source/backend/cpu/CPUBinary.cpp @@ -33,6 +33,11 @@ ErrorCode CPUBinary::onResize(const std::vector& inputs, const std::vec mTotalSize = input0DataCount; } MNN_ASSERT(mTotalSize == outputs[0]->elementSize()); + + if(mActivationType == 1 && outputs[0]->getType().code == halide_type_float) { + mActivationExe.reset(new CPURelu(backend(), 0.0)); + mActivationExe->onResize(outputs, outputs); + } return NO_ERROR; } @@ -59,7 +64,9 @@ ErrorCode CPUBinary::onExecute(const std::vector& inputs, const std::ve auto schedule = ((CPUBackend*)backend())->multiThreadDivide(mTotalSize); auto input0Ptr = input->host(); auto input1Ptr = input1->host(); - auto outputPtr = output->host(); + + auto outputPtr = outputs[0]->host(); + int inpBytes = input->getType().bytes(); int outBytes = output->getType().bytes(); if (halide_type_float == input->getType().code) { @@ -85,9 +92,20 @@ ErrorCode CPUBinary::onExecute(const std::vector& inputs, const std::ve } auto out = outputPtr + start * outBytes; mProc(out, inp0, inp1, realSize, mNeedBroadcastIndex); + if(mActivationType == 1 && output->getType().code == halide_type_int) { + for(int i=0; i 0 ? val : 0; + ((int32_t *)out)[i] = res; + } + } } } MNN_CONCURRENCY_END(); + + if(mActivationType == 1 && output->getType().code == halide_type_float) { + mActivationExe->onExecute(outputs, outputs);; + } return NO_ERROR; } @@ -215,13 +233,13 @@ public: if (nullptr == func) { return nullptr; } - return new CPUBinary(backend, func); + return new CPUBinary(backend, func, op->main_as_BinaryOp()->activationType()); } else if (dataType.code == halide_type_float) { auto func = core->MNNSelectBinaryFunctionForFloat(type); if (nullptr == func) { return nullptr; } - return new CPUBinary(backend, func); + return new CPUBinary(backend, func, op->main_as_BinaryOp()->activationType()); } } MNN_ERROR("CpuBinary: unsupported data type (bits: %d, code: %d)\n", diff --git a/source/backend/cpu/CPUBinary.hpp b/source/backend/cpu/CPUBinary.hpp index 0697c6e18..8c5a952ec 100644 --- a/source/backend/cpu/CPUBinary.hpp +++ b/source/backend/cpu/CPUBinary.hpp @@ -10,12 +10,14 @@ #define CPUBinary_hpp #include "core/Execution.hpp" +#include "backend/cpu/CPURelu.hpp" #include "compute/CommonOptFunction.h" namespace MNN { class CPUBinary : public Execution { public: - CPUBinary(Backend *b, MNNBinaryExecute proc) : Execution(b) { + CPUBinary(Backend *b, MNNBinaryExecute proc, int activationType) : Execution(b) { mProc = proc; + mActivationType = activationType; } virtual ~CPUBinary() = default; virtual ErrorCode onResize(const std::vector &inputs, const std::vector &outputs) override; @@ -26,6 +28,8 @@ private: MNNBinaryExecute mProc; int mNeedBroadcastIndex = -1; int mTotalSize; + int mActivationType = 0; + std::shared_ptr mActivationExe; }; } // namespace MNN #endif /* CPUBinary_hpp */ diff --git a/source/backend/cpu/CPUHistogram.cpp b/source/backend/cpu/CPUHistogram.cpp index ccd53bce8..b3210264f 100644 --- a/source/backend/cpu/CPUHistogram.cpp +++ b/source/backend/cpu/CPUHistogram.cpp @@ -29,24 +29,13 @@ ErrorCode CPUHistogram::histogram(Tensor* input, Tensor* output) { auto iptr = input->host() + mChannel; auto optr = output->host(); memset(optr, 0, mBinNum * sizeof(float)); - auto numberThread = ((CPUBackend*)backend())->threadNumber(); - int sizeDivide = mSize / numberThread; - MNN_CONCURRENCY_BEGIN(tId, numberThread) { - int number = sizeDivide; - if (tId == numberThread - 1) { - number = mSize - tId * sizeDivide; - } - auto src = iptr + tId * sizeDivide * mStride * sizeof(T); - auto dst = optr + tId * sizeDivide * mStride * sizeof(float); - for (int i = 0; i < number; i++) { - T val = src[i * mStride]; - if (val >= mMin && val <= mMax) { - const int bin = (int)(val * mAlpha - mBeta); - dst[std::min(bin, mBinNum -1)]++; - } + for (int i = 0; i < mSize; i++) { + T val = iptr[i * mStride]; + if (val >= mMin && val <= mMax) { + const int bin = (int)(val * mAlpha - mBeta); + optr[std::min(bin, mBinNum -1)]++; } } - MNN_CONCURRENCY_END(); return NO_ERROR; } diff --git a/source/backend/cpu/CPUOPRegister.cpp b/source/backend/cpu/CPUOPRegister.cpp index 2856b76f8..5f6f9a74a 100644 --- a/source/backend/cpu/CPUOPRegister.cpp +++ b/source/backend/cpu/CPUOPRegister.cpp @@ -54,6 +54,7 @@ extern void ___CPURasterFactory__OpType_While__(); extern void ___CPUConvolutionDepthwiseCreator__OpType_ConvolutionDepthwise__(); extern void ___CPURangeCreator__OpType_Range__(); extern void ___CPUTFQuantizedConv2DCreator__OpType_TfQuantizedConv2D__(); +extern void ___CPUInterp3DCreator__OpType_Interp3D__(); extern void ___CPUQuantizedAvgPoolCreator__OpType_QuantizedAvgPool__(); extern void ___ConvolutionFactory__OpType_Convolution__(); extern void ___CPUConvInt8Creator__OpType_ConvInt8__(); @@ -65,7 +66,6 @@ extern void ___CPUSetDiff1DCreator__OpType_SetDiff1D__(); extern void ___CPUEltwiseInt8Creator__OpType_EltwiseInt8__(); extern void ___CPUSvdCreator__OpType_Svd__(); extern void ___CPULayerNormCreator__OpType_LayerNorm__(); -extern void ___CPUInterp3DCreator__OpType_Interp3D__(); void registerCPUOps() { ___CPUCropAndResizeCreator__OpType_CropAndResize__(); @@ -122,6 +122,7 @@ ___CPURasterFactory__OpType_While__(); ___CPUConvolutionDepthwiseCreator__OpType_ConvolutionDepthwise__(); ___CPURangeCreator__OpType_Range__(); ___CPUTFQuantizedConv2DCreator__OpType_TfQuantizedConv2D__(); +___CPUInterp3DCreator__OpType_Interp3D__(); ___CPUQuantizedAvgPoolCreator__OpType_QuantizedAvgPool__(); ___ConvolutionFactory__OpType_Convolution__(); ___CPUConvInt8Creator__OpType_ConvInt8__(); @@ -133,6 +134,5 @@ ___CPUSetDiff1DCreator__OpType_SetDiff1D__(); ___CPUEltwiseInt8Creator__OpType_EltwiseInt8__(); ___CPUSvdCreator__OpType_Svd__(); ___CPULayerNormCreator__OpType_LayerNorm__(); -___CPUInterp3DCreator__OpType_Interp3D__(); } } diff --git a/source/backend/cpu/CPURange.cpp b/source/backend/cpu/CPURange.cpp index c795d9a0c..45267f568 100644 --- a/source/backend/cpu/CPURange.cpp +++ b/source/backend/cpu/CPURange.cpp @@ -21,9 +21,7 @@ template ErrorCode CPURange::onExecute(const std::vector& inputs, const std::vector& outputs) { const T start = inputs[0]->host()[0]; const T delta = inputs[2]->host()[0]; - int32_t outputSize = outputs[0]->buffer().dim[0].extent; - auto flat = outputs[0]->host(); T val = start; for (int32_t i = 0; i < outputSize; ++i) { diff --git a/source/backend/cpu/x86_x64/AVX2Functions.cpp b/source/backend/cpu/x86_x64/AVX2Functions.cpp index ae66d3d3b..4ec34c725 100644 --- a/source/backend/cpu/x86_x64/AVX2Functions.cpp +++ b/source/backend/cpu/x86_x64/AVX2Functions.cpp @@ -57,7 +57,7 @@ bool AVX2Functions::init(int cpuFlags) { _AVX_ExtraInitFMA(coreFunction); } // For ImageProcess Functions - _SSE_ImageProcessInit(coreFunction); + _SSE_ImageProcessInit(coreFunction, cpuFlags); #ifdef MNN_AVX512 if ((cpuFlags & libyuv::kCpuHasAVX512VNNI) || (cpuFlags & libyuv::kCpuHasAVX512VL) diff --git a/source/backend/cpu/x86_x64/FunctionDispatcher.cpp b/source/backend/cpu/x86_x64/FunctionDispatcher.cpp index e3ccc12f2..65611bc64 100644 --- a/source/backend/cpu/x86_x64/FunctionDispatcher.cpp +++ b/source/backend/cpu/x86_x64/FunctionDispatcher.cpp @@ -69,7 +69,7 @@ void MNNFunctionInit() { void MNNInt8FunctionInit() { auto cpuFlags = libyuv::InitCpuFlags(); auto core = MNN::MNNGetInt8CoreFunctions(); - if (cpuFlags & libyuv::kCpuHasSSSE3) { + if (cpuFlags & libyuv::kCpuHasSSE41) { core->MNNFloat2Int8 = _SSE_MNNFloat2Int8; core->MNNInt8ScaleToFloat = _SSE_MNNInt8ScaleToFloat; core->Int8GemmKernel = _SSE_MNNGemmInt8AddBiasScale_16x4_Unit; diff --git a/source/backend/cpu/x86_x64/sse/FunctionSummary.hpp b/source/backend/cpu/x86_x64/sse/FunctionSummary.hpp index 020625aa5..12f1660b2 100644 --- a/source/backend/cpu/x86_x64/sse/FunctionSummary.hpp +++ b/source/backend/cpu/x86_x64/sse/FunctionSummary.hpp @@ -68,4 +68,4 @@ void _SSE_MNNReluInt8(int8_t* dst, const int8_t* src, size_t size); void _SSE_MNNSoftmax(float* dest, const float* source, size_t size); void _SSE_ExtraInit(void* functions); void _SSE_MNNNorm(float *dst, const float *src, const float *gamma, const float *beta, float epsilon, size_t size); -void _SSE_ImageProcessInit(void* functions); +void _SSE_ImageProcessInit(void* functions, int cpuFlags); diff --git a/source/backend/cpu/x86_x64/sse/GemmInt8.cpp b/source/backend/cpu/x86_x64/sse/GemmInt8.cpp index c1014d08a..63cc5f92d 100644 --- a/source/backend/cpu/x86_x64/sse/GemmInt8.cpp +++ b/source/backend/cpu/x86_x64/sse/GemmInt8.cpp @@ -13,6 +13,7 @@ #include #include +// require SSE 4.1 void _SSE_MNNGemmInt8AddBiasScale_16x4_Unit(int8_t* dst, const int8_t* src, const int8_t* weight, size_t src_depth_quad, size_t dst_step, size_t dst_depth_quad, const QuanPostTreatParameters* post, size_t realDst) { const auto dst_step_tmp = dst_step / sizeof(int8_t); @@ -231,6 +232,7 @@ void _SSE_MNNReluInt8(int8_t* dst, const int8_t* src, size_t size) { } } +// require SSE 4.1 void _SSE_MNNFloat2Int8(const float* src, int8_t* dst, size_t sizeQuad, const float* scalep, ssize_t minV, ssize_t maxV, ssize_t zeroPoint) { __m128i zero = _mm_set1_epi32(0); __m128 minValue = _mm_set1_ps(minV); @@ -325,6 +327,7 @@ void _SSE_MNNInt8ScaleToFloat(float* dst, const int8_t* src, const float* scale, } } +// require SSE 4.1 void _SSE_MNNLineDepthWiseInt8AddBiasScaleUnit(int8_t* dstO, const int8_t* srcO, const int8_t* weightO, const QuanPostTreatParameters* parameters, size_t width, size_t src_w_step, size_t fw, size_t fh, size_t dilateX_step, size_t dilateY_step) { auto dst = dstO; auto src = (const int16_t*)srcO; diff --git a/source/backend/cpu/x86_x64/sse/ImageProcessFunction.cpp b/source/backend/cpu/x86_x64/sse/ImageProcessFunction.cpp index ef5108724..c777142f1 100644 --- a/source/backend/cpu/x86_x64/sse/ImageProcessFunction.cpp +++ b/source/backend/cpu/x86_x64/sse/ImageProcessFunction.cpp @@ -9,6 +9,7 @@ #include #include "FunctionSummary.hpp" #include "core/Macro.h" +#include "backend/cpu/x86_x64/cpu_id.h" #define MNN_SSE_YUV_INIT \ countUnit -= 1;\ @@ -245,6 +246,7 @@ void _SSE_MNNNV21ToBGR(const unsigned char* source, unsigned char* dest, size_t } } +// require SSE 4.1 void _SSE_MNNC1ToFloatC1(const unsigned char* source, float* dest, const float* mean, const float* normal, size_t count) { int remain = 0; int countC16 = count / 16; @@ -275,6 +277,7 @@ void _SSE_MNNC1ToFloatC1(const unsigned char* source, float* dest, const float* } } +// require SSE 4.1 void _SSE_MNNC3ToFloatC3(const unsigned char* source, float* dest, const float* mean, const float* normal, size_t count) { int remain = 0; @@ -316,6 +319,7 @@ void _SSE_MNNC3ToFloatC3(const unsigned char* source, float* dest, const float* } } +// require SSE 4.1 void _SSE_MNNC1ToFloatRGBA(const unsigned char* source, float* dest, const float* mean, const float* normal, size_t count) { ::memset(dest, 0, 4 * sizeof(float) * count); @@ -382,6 +386,7 @@ void _SSE_MNNC1ToFloatRGBA(const unsigned char* source, float* dest, const float } } +// require SSE 4.1 void _SSE_MNNC3ToFloatRGBA(const unsigned char* source, float* dest, const float* mean, const float* normal, size_t count) { int remain = 0; int countC4 = count / 4; @@ -424,14 +429,16 @@ void _SSE_MNNC3ToFloatRGBA(const unsigned char* source, float* dest, const float } } -void _SSE_ImageProcessInit(void* functions) { +void _SSE_ImageProcessInit(void* functions, int cpuFlags) { auto coreFunction = static_cast(functions); coreFunction->MNNRGBAToBGRA = _SSE_MNNRGBAToBGRA; coreFunction->MNNNV21ToRGBA = _SSE_MNNNV21ToRGBA; coreFunction->MNNNV21ToRGB = _SSE_MNNNV21ToRGB; coreFunction->MNNNV21ToBGRA = _SSE_MNNNV21ToBGRA; coreFunction->MNNNV21ToBGR = _SSE_MNNNV21ToBGR; - coreFunction->MNNC1ToFloatC1 = _SSE_MNNC1ToFloatC1; - coreFunction->MNNC3ToFloatC3 = _SSE_MNNC3ToFloatC3; - coreFunction->MNNC3ToFloatRGBA = _SSE_MNNC3ToFloatRGBA; + if (cpuFlags & libyuv::kCpuHasSSE41) { + coreFunction->MNNC1ToFloatC1 = _SSE_MNNC1ToFloatC1; + coreFunction->MNNC3ToFloatC3 = _SSE_MNNC3ToFloatC3; + coreFunction->MNNC3ToFloatRGBA = _SSE_MNNC3ToFloatRGBA; + } } diff --git a/source/backend/cpu/x86_x64/sse/MathFunctions.cpp b/source/backend/cpu/x86_x64/sse/MathFunctions.cpp index f8beec23f..02c609041 100644 --- a/source/backend/cpu/x86_x64/sse/MathFunctions.cpp +++ b/source/backend/cpu/x86_x64/sse/MathFunctions.cpp @@ -27,7 +27,7 @@ void _SSE_MNNExpC8(float* dest, const float* source, const float* offset, const auto p7 = _mm_set1_ps(parameters[7]); auto xMax = _mm_set1_ps(87); auto xMin = _mm_set1_ps(-87); - auto basic = _mm_set1_epi32(1 << 23); + // auto basic = _mm_set1_epi32(1 << 23); for (int i = 0; i < count; ++i) { auto x = _mm_mul_ps(_mm_loadu_ps(source + i * 4), A); x = _mm_max_ps(x, xMin); @@ -36,7 +36,8 @@ void _SSE_MNNExpC8(float* dest, const float* source, const float* offset, const auto divInt = _mm_cvtps_epi32(div); div = _mm_cvtepi32_ps(divInt); auto div2 = _mm_add_epi32(divInt, _mm_set1_epi32(127)); - div2 = _mm_mullo_epi32(div2, basic); + // div2 = _mm_mullo_epi32(div2, basic); + div2 = _mm_slli_epi32(div2, 23); auto expBasic = _mm_castsi128_ps(div2); auto xReamin = _mm_sub_ps(x, _mm_mul_ps(div, p0)); auto t = xReamin; @@ -89,7 +90,7 @@ void _SSE_MNNSoftmax(float* dest, const float* source, size_t size) { auto p7 = _mm_set1_ps(0.008333333333333333); auto xMax = _mm_set1_ps(87); auto xMin = _mm_set1_ps(-87); - auto basic = _mm_set1_epi32(1 << 23); + // auto basic = _mm_set1_epi32(1 << 23); for (int i = 0; i < count; ++i) { auto x = _mm_sub_ps(_mm_loadu_ps(source + i * 4), _mm_set1_ps(maxValue)); x = _mm_max_ps(x, xMin); @@ -98,7 +99,8 @@ void _SSE_MNNSoftmax(float* dest, const float* source, size_t size) { auto divInt = _mm_cvtps_epi32(div); div = _mm_cvtepi32_ps(divInt); auto div2 = _mm_add_epi32(divInt, _mm_set1_epi32(127)); - div2 = _mm_mullo_epi32(div2, basic); + // div2 = _mm_mullo_epi32(div2, basic); + div2 = _mm_slli_epi32(div2, 23); auto expBasic = _mm_castsi128_ps(div2); auto xReamin = _mm_sub_ps(x, _mm_mul_ps(div, p0)); auto t = xReamin; diff --git a/source/backend/cuda/CMakeLists.txt b/source/backend/cuda/CMakeLists.txt index 138ac31a0..d34818598 100644 --- a/source/backend/cuda/CMakeLists.txt +++ b/source/backend/cuda/CMakeLists.txt @@ -1,8 +1,14 @@ set(CUDA_MIN_VERSION "9.0") find_package(CUDA ${CUDA_MIN_VERSION}) +set (EXTRA_LIBS "") +if(MNN_CUDA_PROFILE) + set(EXTRA_LIBS -lnvToolsExt) +endif() + + if(CUDA_FOUND) - set(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS} -D_FORCE_INLINES -Wno-deprecated-gpu-targets -w") + set(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS} -D_FORCE_INLINES -Wno-deprecated-gpu-targets -w ${EXTRA_LIBS}") if(CMAKE_BUILD_TYPE MATCHES Debug) set(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS} -O0") else() @@ -15,6 +21,7 @@ if(CUDA_FOUND) include(${CMAKE_CURRENT_SOURCE_DIR}/SelectCudaComputeArch.cmake) CUDA_SELECT_NVCC_ARCH_FLAGS(CUDA_ARCH_FLAGS ${CUDA_ARCHS}) + IF ((CUDA_VERSION VERSION_GREATER "9.0") OR (CUDA_VERSION VERSION_EQUAL "9.0")) set(CUDA_NVCC_FLAGS "${CUDA_NVCC_FLAGS} -gencode arch=compute_70,code=sm_70") ENDIF() @@ -34,13 +41,20 @@ else() endif() file(GLOB_RECURSE MNN_CUDA_SRC ${CMAKE_CURRENT_LIST_DIR}/core/* ${CMAKE_CURRENT_SOURCE_DIR}/execution/*) -message(STATUS "message ${CUDA_NVCC_FLAGS} !!!!!!!!!!!") +message(STATUS "message ${CUDA_NVCC_FLAGS} !!!!!!!!!!! ${CUDA_INCLUDE_DIRS}") + if(WIN32) cuda_add_library(MNN_CUDA STATIC Register.cpp ${MNN_CUDA_SRC}) set(MNN_CUDA_LIBS MNN_CUDA ${CUDA_LIBRARIES} PARENT_SCOPE) else() + cuda_add_library(MNN_Cuda_Main SHARED ${MNN_CUDA_SRC}) + if(MNN_CUDA_PROFILE) + target_compile_options(MNN_Cuda_Main PRIVATE -DMNN_CUDA_PROFILE) + target_link_libraries(MNN_Cuda_Main ${CUDA_INCLUDE_DIRS}/../lib/libnvToolsExt.so) + endif() + set(MNN_CUDA_LIBS MNN_Cuda_Main PARENT_SCOPE) add_library(MNN_CUDA OBJECT Register.cpp) endif() @@ -52,3 +66,5 @@ include_directories( ${CMAKE_CURRENT_SOURCE_DIR}/../../../3rd_party/cutlass/include ) + + diff --git a/source/backend/cuda/core/CUDABackend.cpp b/source/backend/cuda/core/CUDABackend.cpp index ca11b4758..254cff5a3 100644 --- a/source/backend/cuda/core/CUDABackend.cpp +++ b/source/backend/cuda/core/CUDABackend.cpp @@ -18,6 +18,8 @@ #include "execution/Transpose.cuh" #include "execution/MNNCUDADefine.hpp" +#include "CUDATools.hpp" + // #define MNN_CUDA_COPY_DEBUG namespace MNN { @@ -47,6 +49,9 @@ private: CUDARuntimeWrapper::CUDARuntimeWrapper(BackendConfig::PrecisionMode precision, BackendConfig::PowerMode power) { // TODO: Search CUDA Device info and use best one mCUDARuntime.reset(new CUDARuntime(-1)); +#ifdef LOG_VERBOSE + MNN_PRINT("create cuda runtime:%p\n", mCUDARuntime.get()); +#endif if (mCUDARuntime.get()) { if (mCUDARuntime->isCreateError() == true) { mIsCreateError = true; @@ -66,6 +71,9 @@ float CUDARuntimeWrapper::onGetMemoryInMB() { } Backend* CUDARuntimeWrapper::onCreate(const BackendConfig* config) const { +#ifdef LOG_VERBOSE + MNN_PRINT("cudaruntime:%p, create CUDABackend\n", this); +#endif auto mode = mDefaultPrecision; if (nullptr != config) { mode = config->precision; @@ -78,9 +86,13 @@ void CUDARuntimeWrapper::onGabageCollect(int level) { mBufferPool->release(false); } + CUDABackend::CUDABackend(std::shared_ptr st, std::shared_ptr rt, bool useFp16AsFp32) : Backend(MNN_FORWARD_CUDA) { +#ifdef LOG_VERBOSE + MNN_PRINT("cuda backend create\n"); +#endif mBufferPool.reset(new BufferAllocator(BufferAllocator::Allocator::createRecurse(st.get()))); mStaticBufferPool = st; mCUDARuntime = rt; @@ -97,6 +109,9 @@ CUDARuntime* CUDABackend::getCUDARuntime() { MNN_ASSERT(nullptr != mCUDARuntime.get()); return mCUDARuntime.get(); } +const Runtime* CUDABackend::getRuntime() { + return (const Runtime*)mCUDARuntime.get(); +} bool CUDABackend::useFp16() const { return mUseFp16AsFp32; } @@ -128,6 +143,7 @@ CPUResizeCache* CUDABackend::getCache() { } Backend::MemObj* CUDABackend::onAcquire(const Tensor* nativeTensor, StorageType storageType) { + // MNN_PRINT("onAcquire CUDA memory for tensor:%p\n", nativeTensor); #ifdef LOG_VERBOSE MNN_PRINT("Start CUDABackend::onAcquireBuffer !\n"); #endif @@ -181,17 +197,16 @@ size_t CUDABackend::realSize(const Tensor* tensor) { Execution* CUDABackend::onCreate(const std::vector& inputs, const std::vector& outputs, const MNN::Op* op) { -#ifdef LOG_VERBOSE - MNN_PRINT("Start CUDABackend::onCreate \n"); -#endif +// #ifdef LOG_VERBOSE + // MNN_PRINT("Start CUDABackend::onCreate useFp16:%d\n", useFp16()); +// #endif auto creators = gCreator(); auto iter = creators->find(op->type()); - if (iter == creators->end()) { if (nullptr != op->name()) { - MNN_PRINT("Don't support type %s, %s\n", EnumNameOpType(op->type()), op->name()->c_str()); + MNN_PRINT("CUDABackend Don't support type %s, %s\n", EnumNameOpType(op->type()), op->name()->c_str()); } else { - MNN_PRINT("Don't support type %s\n", EnumNameOpType(op->type())); + MNN_PRINT("CUDABackend Don't support type %s\n", EnumNameOpType(op->type())); } return NULL; } @@ -199,9 +214,9 @@ Execution* CUDABackend::onCreate(const std::vector& inputs, const std:: auto exe = iter->second->onCreate(inputs, outputs, op, this); if (NULL == exe) { if (nullptr != op->name()) { - MNN_PRINT("The Creator Don't support type %s, %s\n", EnumNameOpType(op->type()), op->name()->c_str()); + MNN_PRINT("CUDABackend The Creator Don't support type %s, %s\n", EnumNameOpType(op->type()), op->name()->c_str()); } else { - MNN_PRINT("The Creator Don't support type %s\n", EnumNameOpType(op->type())); + MNN_PRINT("CUDABackend The Creator Don't support type %s\n", EnumNameOpType(op->type())); } return NULL; } @@ -222,6 +237,7 @@ void CUDABackend::onExecuteBegin() const { void CUDABackend::onExecuteEnd() const { } + static void _computeStride(MNN_DATA_FORMAT srcDimensionFormat, int* srcStride, int batch, int plane, int channel, int srcPack) { if (srcDimensionFormat == MNN_DATA_FORMAT_NC4HW4) { srcStride[0] = plane * srcPack; @@ -283,9 +299,11 @@ static PackInfo _computePackInfo(MNN_DATA_FORMAT srcDimensionFormat, int batch, } void CUDABackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) const { - + auto srcDimensionFormat = TensorUtils::getDescribe(srcTensor)->dimensionFormat; auto dstDimensionFormat = TensorUtils::getDescribe(dstTensor)->dimensionFormat; + auto srcIndex = TensorUtils::getDescribe(srcTensor)->index; + auto dstIndex = TensorUtils::getDescribe(dstTensor)->index; auto srcDevice = srcTensor->deviceId() != 0; auto dstDevice = dstTensor->deviceId() != 0; MNN_ASSERT(srcDevice || dstDevice); @@ -293,18 +311,6 @@ void CUDABackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) std::pair tempSrcStorage; auto bytes = getBytes(srcTensor); auto type = srcTensor->getType(); -#ifdef MNN_CUDA_COPY_DEBUG - checkKernelErrors; - MNN_PRINT("CUDA Bn copy: %d -> %d, format %d -> %d, dims: [", srcDevice, dstDevice, srcDimensionFormat, dstDimensionFormat); - for (int i=0; idimensions(); ++i) { - MNN_PRINT("%d ", srcTensor->length(i)); - if(srcDevice && !dstDevice) { - printf("\n"); - } - } - MNN_PRINT("], "); - MNN_PRINT("addr:%p %p\n", srcTensor->deviceId(), dstTensor->deviceId()); -#endif //printf("%d-%d\n", srcTensor->dimensions(), dstTensor->dimensions()); bool directCopy = (srcDimensionFormat == dstDimensionFormat && dstDimensionFormat != MNN_DATA_FORMAT_NC4HW4) || srcTensor->dimensions() <= 1; @@ -315,17 +321,40 @@ void CUDABackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) } } } + +#ifdef MNN_CUDA_COPY_DEBUG + checkKernelErrors; + MNN_PRINT("CUDA Bn copy tensor ptr:%p -> ptr:%p deviceId:%d -> %d, hostPtr:%p -> %p, graphIndex: %d -> %d, format %d -> %d, directCopy: %d, dims: [", + srcTensor, dstTensor, srcTensor->deviceId(), dstTensor->deviceId(), srcTensor->host(), dstTensor->host(), srcIndex, dstIndex, srcDimensionFormat, dstDimensionFormat, directCopy); + + for (int i=0; idimensions(); ++i) { + MNN_PRINT("%d ", srcTensor->length(i)); + if(srcDevice && !dstDevice) { + printf("\n"); + } + } + MNN_PRINT("], "); + MNN_PRINT("addr:%p %p\n", srcTensor->deviceId(), dstTensor->deviceId()); +#endif + + if (directCopy) { auto gpuSize = realSize(srcTensor) * getBytes(srcTensor); if (srcDevice && dstDevice) { + NVTX_PUSH("DtoD"); mCUDARuntime->memcpy((void*)(dstTensor->deviceId()), (void*)(srcTensor->deviceId()), gpuSize, MNNMemcpyDeviceToDevice, true); + NVTX_POP(); } else if (srcDevice && (!dstDevice)) { + NVTX_PUSH("DtoH"); mCUDARuntime->memcpy((void*)(dstTensor->host()), (void*)(srcTensor->deviceId()), gpuSize, MNNMemcpyDeviceToHost, true); + NVTX_POP(); } else if ((!srcDevice) && (dstDevice)) { + NVTX_PUSH("HtoD"); mCUDARuntime->memcpy((void*)(dstTensor->deviceId()), (void*)(srcTensor->host()), gpuSize, MNNMemcpyHostToDevice, true); + NVTX_POP(); } return; } @@ -348,6 +377,7 @@ void CUDABackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) dstPtr = (uint8_t*)dstTensor->deviceId(); } + NVTX_PUSH("copy convert"); // Format convert int batch, plane, channel; _computeBCA(batch, plane, channel, srcDimensionFormat, srcTensor); @@ -368,8 +398,9 @@ void CUDABackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) auto cpuSize = dstTensor->size(); mCUDARuntime->memcpy(dstTensor->host(), dstPtr, cpuSize, MNNMemcpyDeviceToHost, true); - mStaticBufferPool->free(tempDstStorage); + mStaticBufferPool->free(tempDstStorage); } + NVTX_POP(); return; } diff --git a/source/backend/cuda/core/CUDABackend.hpp b/source/backend/cuda/core/CUDABackend.hpp index 4fb0c50b3..ccae82705 100644 --- a/source/backend/cuda/core/CUDABackend.hpp +++ b/source/backend/cuda/core/CUDABackend.hpp @@ -36,7 +36,7 @@ public: private: std::shared_ptr mBufferPool; - std::shared_ptr mCUDARuntime; + std::shared_ptr mCUDARuntime; bool mIsCreateError{false}; BackendConfig::PrecisionMode mDefaultPrecision; }; @@ -47,6 +47,7 @@ public: ~CUDABackend(); CUDARuntime *getCUDARuntime(); + virtual const Runtime* getRuntime() override; virtual Backend::MemObj* onAcquire(const Tensor *nativeTensor, StorageType storageType) override; virtual bool onClearBuffer() override; diff --git a/source/backend/cuda/core/CUDATools.hpp b/source/backend/cuda/core/CUDATools.hpp new file mode 100644 index 000000000..a1e8fa9f6 --- /dev/null +++ b/source/backend/cuda/core/CUDATools.hpp @@ -0,0 +1,167 @@ +// CUDATools.hpp +// MNN +// +// Created by MNN on b'2022/09/05'. +// Copyright © 2022, Alibaba Group Holding Limited +// + +#ifndef CUDATools_hpp + + +/* + +use nvprof by open the MACRO 'MNN_CUDA_PROFILE'. + cmake .. -DMNN_CUDA_PROFILE=ON -DMNN_CUDA=ON + +*/ +#ifdef MNN_CUDA_PROFILE + #include "nvToolsExt.h" + #define NVTX_PUSH(...) nvtxRangePushA(__VA_ARGS__) + #define NVTX_POP(...) nvtxRangePop(__VA_ARGS__) +#else + #define NVTX_PUSH(...) + #define NVTX_POP(...) +#endif + + +#ifdef MNN_CUDA_PROFILE +#include +#include +#include +#include +#include +#include +#include + +// print stack trace log +class MNNLogMessage { +public: + MNNLogMessage(const char* file, int line, const char* function) + : + log_stream_(std::cout) + { + const char* pos = file; + const char* onlyName = file; + while (*pos != 0) { + if (*pos == '/') { + onlyName = pos + 1; + } + pos++; + } + log_stream_ << onlyName << ":" + << line << ":" + << function << ": "; + } + ~MNNLogMessage() { + log_stream_ << '\n'; + } + std::ostream& stream() { + return log_stream_; + } + std::string GetCachedString() { + return ""; + } + +protected: + std::ostream& log_stream_; + +private: + MNNLogMessage(const MNNLogMessage&); + void operator=(const MNNLogMessage&); +}; +#if !defined(MNN_BUILD_FOR_ANDROID) +inline std::string +Demangle(char const* msg_str, std::ostringstream& os) { + using std::string; + string msg(msg_str); + size_t symbol_start = string::npos; + size_t symbol_end = string::npos; + if (((symbol_start = msg.find("_Z")) != string::npos) && + (symbol_end = msg.find_first_of(" +", symbol_start))) { + string left_of_symbol(msg, 0, symbol_start); + string symbol(msg, symbol_start, symbol_end - symbol_start); + string right_of_symbol(msg, symbol_end); + + int status = 0; + size_t length = string::npos; + std::unique_ptr demangled_symbol = { + abi::__cxa_demangle(symbol.c_str(), 0, &length, &status), &std::free}; + if (demangled_symbol && status == 0 && length > 0) { + string symbol_str(demangled_symbol.get()); + os << left_of_symbol << symbol_str << right_of_symbol; + return os.str(); + } + } + return string(msg_str); +} + +// By default skip the first frame because +// that belongs to ~FatalLogMessage +inline std::string +StackTrace(size_t start_frame = 2, const size_t stack_size = 12) { + using std::string; + std::ostringstream stacktrace_os; + std::vector stack(stack_size); + int nframes = backtrace(stack.data(), static_cast(stack_size)); + stacktrace_os << "Stack trace:\n"; + char** msgs = backtrace_symbols(stack.data(), nframes); + if (msgs != nullptr) { + for (int frameno = start_frame; frameno < nframes; ++frameno) { + stacktrace_os << " [bt] (" << frameno - start_frame << ") "; + string msg = Demangle(msgs[frameno], stacktrace_os); + stacktrace_os << "\n"; + } + } + free(msgs); + string stack_trace = stacktrace_os.str(); + return stack_trace; +} + + +class TraceMNNLogMessage : public MNNLogMessage { +public: + TraceMNNLogMessage(const char* file, int line, const char* function) : MNNLogMessage(file, line, function) {} + ~TraceMNNLogMessage() { + log_stream_ << "\n" << StackTrace(1); + } +}; + +#define MNN_LOG_TRACE TraceMNNLogMessage(__FILE__, __LINE__, __FUNCTION__) + +#else +#define MNN_LOG_TRACE MNNLogMessage(__FILE__, __LINE__, __FUNCTION__) +#endif + +#define MNN_LOG_INFO MNNLogMessage(__FILE__, __LINE__, __FUNCTION__) +#define MNN_LOG(severity) MNN_LOG_##severity.stream() +#define MNN_LOG_IF(severity, condition) \ + !(condition) ? (void)0 : MNNLogMessageVoidify() & MNN_LOG(severity) + +// deal with release/debug +// release mode +#if !defined(NDEBUG) +#define MNN_DLOG(severity) MNN_LOG(severity) +#define MNN_DLOG_IF(severity, condition) MNN_LOG_IF(severity, (condition)) + +// debug mode, all MNN_DLOG() code would be compiled as empty. +#else +#define MNN_DLOG(severity) MNN_LOG_IF(severity, false) +#define MNN_DLOG_IF(severity, condition) MNN_LOG_IF(severity, false) + +#endif + +// This class is used to explicitly ignore values in the conditional +// logging macros. This avoids compiler warnings like "value computed +// is not used" and "statement has no effect". +class MNNLogMessageVoidify { +public: + MNNLogMessageVoidify() {} + // This has to be an operator with a precedence lower than << but + // higher than "?:". See its usage. + void operator&(std::ostream&) {} +}; + +#endif +#endif + + diff --git a/source/backend/cuda/core/runtime/CUDARuntime.cpp b/source/backend/cuda/core/runtime/CUDARuntime.cpp index df68519d8..add0a764b 100644 --- a/source/backend/cuda/core/runtime/CUDARuntime.cpp +++ b/source/backend/cuda/core/runtime/CUDARuntime.cpp @@ -15,14 +15,9 @@ #include #include #include "core/Macro.h" -// #define MNN_CUDA_USE_BLAS + //#define MNN_OPEN_TIME_TRACE #include -#define STR_HELPER(x) #x -#define STR(x) STR_HELPER(x) - -#undef STR -#undef STR_HELPER namespace MNN { @@ -32,7 +27,7 @@ bool CUDARuntime::isCreateError() const { CUDARuntime::CUDARuntime(int device_id) { #ifdef LOG_VERBOSE - MNN_PRINT("start CUDARuntime !\n"); + MNN_PRINT("start CUDARuntime id:%d\n", device_id); #endif int version; cuda_check(cudaRuntimeGetVersion(&version)); @@ -40,6 +35,7 @@ CUDARuntime::CUDARuntime(int device_id) { if (id < 0) { cuda_check(cudaGetDevice(&id)); } + // printf("use GPU device id:%d\n", id); // id = selectDeviceMaxFreeMemory(); // cuda_check(cudaSetDevice(id)); @@ -68,23 +64,24 @@ int CUDARuntime::selectDeviceMaxFreeMemory() { cudaDeviceProp deviceProp; int deviceCount; cuda_check(cudaGetDeviceCount(&deviceCount)); - + // Check id:0 card info int id = 0; cuda_check(cudaSetDevice(0)); - size_t total_size, free_size_max; - cuda_check(cudaMemGetInfo(&free_size_max, &total_size)); - //printf("card:0, free:%zu, total:%zu\n", free_size_max, total_size); + size_t total_size = 0, free_size_max = 0; + cudaError_t memStatus = cudaMemGetInfo(&free_size_max, &total_size); + cuda_check(memStatus); + // printf("card:0, free:%zu, total:%zu, memStatusSuccess:%d\n", free_size_max, total_size, memStatus == cudaSuccess); for(int i = 1; i < deviceCount; i++) { cuda_check(cudaSetDevice(i)); size_t free_size; - cuda_check(cudaMemGetInfo(&free_size, &total_size)); + cuda_check(cudaMemGetInfo(&free_size, &total_size)); if(free_size > free_size_max) { free_size_max = free_size; id = i; - } - //printf("card:%d, free:%zu, total:%zu\n", i, free_size, total_size); + } + // printf("card:%d, free:%zu, total:%zu\n", i, free_size, total_size); } return id; } @@ -102,7 +99,7 @@ size_t CUDARuntime::blocks_num(const size_t total_threads) { // } else { // mThreadPerBlock = 128; // } - + mThreadPerBlock = 128; return (total_threads + mThreadPerBlock - 1) / mThreadPerBlock; } @@ -170,4 +167,7 @@ void CUDARuntime::memset(void *dst, int value, size_t size_in_bytes) { cuda_check(cudaMemset(dst, value, size_in_bytes)); checkKernelErrors; } + + + } // namespace MNN diff --git a/source/backend/cuda/execution/ArgMaxExecution.cu b/source/backend/cuda/execution/ArgMaxExecution.cu index 2c1b37670..de228e9ab 100644 --- a/source/backend/cuda/execution/ArgMaxExecution.cu +++ b/source/backend/cuda/execution/ArgMaxExecution.cu @@ -1,4 +1,5 @@ #include "ArgMaxExecution.hpp" +#include "ArgMinExecution.hpp" #include "core/TensorUtils.hpp" namespace MNN { @@ -14,9 +15,9 @@ __global__ void ARGMAX(const int count, const int outside, const int inside, con int* outPtr = output + inside * o; const T* inpPtr = input + inside * dim * o; int index = 0; - T maxValue = inpPtr[n+0*inside]; + T maxValue = inpPtr[n + 0 * inside]; for(int j=1; j &inputs, const auto input = (void *)inputs[0]->deviceId(); auto output = (void *)outputs[0]->deviceId(); - int count = mOutside * mInside; int block_num = runtime->blocks_num(count); int thread_num = runtime->threads_num(); + auto bytes = static_cast(backend())->getBytes(inputs[0]); if(bytes == 4) { @@ -73,7 +75,7 @@ ErrorCode ArgMaxExecution::onExecute(const std::vector &inputs, const ARGMAX<<>>(count, mOutside, mInside, mDim, (const half*)input,(int *)output); checkKernelErrors; } - + return NO_ERROR; } class ArgMaxCreator : public CUDABackend::Creator { @@ -84,10 +86,17 @@ public: if (TensorUtils::getDescribe(input)->dimensionFormat == MNN_DATA_FORMAT_NC4HW4) { return nullptr; } - return new ArgMaxExecution(op, backend); + if (op->type() == OpType_ArgMax) { + return new ArgMaxExecution(op, backend); + } else { + return new ArgMinExecution(op, backend); + } + } }; static CUDACreatorRegister __init(OpType_ArgMax); +static CUDACreatorRegister __init_op2(OpType_ArgMin); + } } diff --git a/source/backend/cuda/execution/ArgMinExecution.cu b/source/backend/cuda/execution/ArgMinExecution.cu new file mode 100644 index 000000000..21346edf8 --- /dev/null +++ b/source/backend/cuda/execution/ArgMinExecution.cu @@ -0,0 +1,90 @@ +// +// ArgMinExecution.cpp +// MNN +// +// Created by MNN on 2022/06/29. +// Copyright © 2018 - 2022, Alibaba Group Holding Limited +// +#include "ArgMinExecution.hpp" +#include "core/TensorUtils.hpp" +#include + +namespace MNN { +namespace CUDA { + +template +__global__ void ARGMIN(const int count, const int outside, const int inside, const int dim, + const T *input, int *output) { + + for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < (count); i += blockDim.x * gridDim.x) { + const int o = i / inside; + const int n = i % inside; + + int* outPtr = output + inside * o; + const T* inpPtr = input + inside * dim * o; + int index = 0; + T minValue = inpPtr[n + 0 * inside]; + for(int j=1; j value) { + index = j; + minValue = value; + } + } + outPtr[n] = index; + } + return; +} +ArgMinExecution::ArgMinExecution(const Op* op, Backend *backend) : Execution(backend) { + mOp = op; + mAxis = mOp->main_as_ArgMax()->axis(); +} + +ArgMinExecution::~ArgMinExecution(){ + // Do nothing +} + +ErrorCode ArgMinExecution::onResize(const std::vector &inputs, const std::vector &outputs) { + auto input = inputs[0]; + auto output = outputs[0]; + + if (mAxis < 0) { + mAxis = input->dimensions() + mAxis; + } + + mInside = 1; + mOutside = 1; + for (int i=0; ilength(i); + } + for (int i=mAxis+1; idimensions(); ++i) { + mInside *= input->length(i); + } + mDim = input->length(mAxis); + + return NO_ERROR; +} + +ErrorCode ArgMinExecution::onExecute(const std::vector &inputs, const std::vector &outputs) { + auto runtime = static_cast(backend())->getCUDARuntime(); + + auto input = (void *)inputs[0]->deviceId(); + auto output = (void *)outputs[0]->deviceId(); + int count = mOutside * mInside; + int block_num = runtime->blocks_num(count); + int thread_num = runtime->threads_num(); + + auto bytes = static_cast(backend())->getBytes(inputs[0]); + + if(bytes == 4) { + ARGMIN<<>>(count, mOutside, mInside, mDim, (const float*)input,(int *)output); + checkKernelErrors; + } else { + ARGMIN<<>>(count, mOutside, mInside, mDim, (const half*)input,(int *)output); + checkKernelErrors; + } + return NO_ERROR; +} + +} +} diff --git a/source/backend/cuda/execution/ArgMinExecution.hpp b/source/backend/cuda/execution/ArgMinExecution.hpp new file mode 100644 index 000000000..32d15ba77 --- /dev/null +++ b/source/backend/cuda/execution/ArgMinExecution.hpp @@ -0,0 +1,33 @@ +// +// ArgMinExecution.hpp +// MNN +// +// Created by MNN on 2022/06/29. +// Copyright © 2018 - 2022, Alibaba Group Holding Limited +// + +#ifndef ArgMinExecution_hpp +#define ArgMinExecution_hpp +#include +#include "backend/cuda/core/CUDABackend.hpp" +#include "core/Execution.hpp" +namespace MNN { +namespace CUDA { +class ArgMinExecution : public Execution { +public: + ArgMinExecution(const Op* op, Backend *backend); + virtual ~ArgMinExecution(); + virtual ErrorCode onResize(const std::vector &inputs, const std::vector &outputs) override; + virtual ErrorCode onExecute(const std::vector &inputs, const std::vector &outputs) override; + +private: + const Op* mOp; + int mAxis; + int mInside; + int mOutside; + int mDim; +}; +} // namespace CUDA +} // namespace MNN + +#endif diff --git a/source/backend/cuda/execution/BinaryExecution.cu b/source/backend/cuda/execution/BinaryExecution.cu index 8f0ec238e..18b3df375 100644 --- a/source/backend/cuda/execution/BinaryExecution.cu +++ b/source/backend/cuda/execution/BinaryExecution.cu @@ -32,8 +32,9 @@ __global__ void LOGICALOR(const T *input0, const T* input1, T *output, size_t co } return; } -BinaryExecution::BinaryExecution(int opType, Backend *backend) : Execution(backend) { +BinaryExecution::BinaryExecution(int opType, Backend *backend, int activationType) : Execution(backend) { mType = opType; + mActivationType = activationType; } BinaryExecution::~BinaryExecution(){ // Do nothing @@ -59,7 +60,7 @@ ErrorCode BinaryExecution::onExecute(const std::vector &inputs, const auto input0 = (uint8_t*)input0T->deviceId(); auto input1 = (uint8_t*)input1T->deviceId(); auto output = (uint8_t*)outputT->deviceId(); - BinaryBlit(output, input0, input1, size, stride0, stride1, stride2, type, runtime, mType); + BinaryBlit(output, input0, input1, size, stride0, stride1, stride2, type, runtime, mType, mActivationType); }; computeFunction(inputs[0], inputs[1], outputs[0]); for (int i=2; i& inputs, const std::vector& outputs, const MNN::Op* op, Backend* backend) const override { if (op->type() == OpType_BinaryOp) { - return new BinaryExecution(op->main_as_BinaryOp()->opType(), backend); + //MNN_PRINT("binary act:%d\n", op->main_as_BinaryOp()->activationType()); + return new BinaryExecution(op->main_as_BinaryOp()->opType(), backend, op->main_as_BinaryOp()->activationType()); } if (op->type() == OpType_Eltwise) { switch (op->main_as_Eltwise()->type()) { diff --git a/source/backend/cuda/execution/BinaryExecution.hpp b/source/backend/cuda/execution/BinaryExecution.hpp index 38620216b..3688d51b1 100644 --- a/source/backend/cuda/execution/BinaryExecution.hpp +++ b/source/backend/cuda/execution/BinaryExecution.hpp @@ -15,12 +15,13 @@ namespace MNN { namespace CUDA { class BinaryExecution : public Execution { public: - BinaryExecution(int opType, Backend *backend); + BinaryExecution(int opType, Backend *backend, int activationType = 0); virtual ~BinaryExecution(); virtual ErrorCode onExecute(const std::vector &inputs, const std::vector &outputs) override; private: int mType; + int mActivationType; }; } // namespace CUDA } // namespace MNN diff --git a/source/backend/cuda/execution/ConvCutlassExecution.cu b/source/backend/cuda/execution/ConvCutlassExecution.cu index 614b4d872..1bf148643 100644 --- a/source/backend/cuda/execution/ConvCutlassExecution.cu +++ b/source/backend/cuda/execution/ConvCutlassExecution.cu @@ -8,8 +8,6 @@ #include "ConvCutlassExecution.hpp" #include "Raster.cuh" -#include "MNNCUDADefine.hpp" -#include "MNNCUDAFunction.cuh" //#define DEBUG @@ -230,8 +228,8 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con mGemmInfo.elh[1] = l; mGemmInfo.elh[2] = h; mGemmInfo.elhPad[0] = UP_DIV(e, 8) * 8; - mGemmInfo.elhPad[1] = UP_DIV(l, 8) * 8;; - mGemmInfo.elhPad[2] = UP_DIV(h, 8) * 8;; + mGemmInfo.elhPad[1] = UP_DIV(l, 8) * 8; + mGemmInfo.elhPad[2] = UP_DIV(h, 8) * 8; //MNN_PRINT("Activate:%d \n", mActivationType); //MNN_PRINT("Im2Col：%d-%d-%d temp size:%zu!!!\n\n",output->width(), ic, mIm2ColParamter.kernelX, (size_t)sizeof(__half) * mMatMulParam.elhPack[0] * mMatMulParam.elhPack[1] * MATMULPACK * MATMULPACK); @@ -283,10 +281,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F16_Relu_Sm70::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF16ReluSm70.can_implement(arguments); @@ -307,10 +305,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F32_Relu_Sm70::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF32ReluSm70.can_implement(arguments); @@ -335,10 +333,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F16_Relu6_Sm70::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF16Relu6Sm70.can_implement(arguments); @@ -359,10 +357,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F32_Relu6_Sm70::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF32Relu6Sm70.can_implement(arguments); @@ -385,10 +383,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F16_Linear_Sm70::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); cutlass::Status status = mGemmF16LnSm70.can_implement(arguments); cutlass_check(status); @@ -406,10 +404,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F32_Linear_Sm70::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); cutlass::Status status = mGemmF32LnSm70.can_implement(arguments); cutlass_check(status); @@ -435,10 +433,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F16_Relu_Sm75::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF16ReluSm75.can_implement(arguments); @@ -459,10 +457,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F32_Relu_Sm75::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF32ReluSm75.can_implement(arguments); @@ -487,10 +485,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F16_Relu6_Sm75::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF16Relu6Sm75.can_implement(arguments); @@ -511,10 +509,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F32_Relu6_Sm75::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); // Check the problem size is supported or not cutlass::Status status = mGemmF32Relu6Sm75.can_implement(arguments); @@ -537,10 +535,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F16_Linear_Sm75::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); cutlass::Status status = mGemmF16LnSm75.can_implement(arguments); cutlass_check(status); @@ -558,10 +556,10 @@ ErrorCode ConvCutlassExecution::onResize(const std::vector &inputs, con split_k_slices}; // <- k-dimension split factor size_t workspace_size = Gemm_F32_Linear_Sm75::get_workspace_size(arguments); - auto buffer3 = pool->alloc(workspace_size * sizeof(uint8_t)); - mWorkspace = (uint8_t*)buffer3.first + buffer3.second; + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); - pool->free(buffer3); + pool->free(bufferWs); cutlass::Status status = mGemmF32LnSm75.can_implement(arguments); cutlass_check(status); diff --git a/source/backend/cuda/execution/ConvCutlassExecution.hpp b/source/backend/cuda/execution/ConvCutlassExecution.hpp index a778f3995..746f2d635 100644 --- a/source/backend/cuda/execution/ConvCutlassExecution.hpp +++ b/source/backend/cuda/execution/ConvCutlassExecution.hpp @@ -11,15 +11,12 @@ #include "backend/cuda/core/CUDABackend.hpp" #include "core/Execution.hpp" #include "CutlassGemmParam.hpp" +#include "MNNCUDADefine.hpp" +#include "MNNCUDAFunction.cuh" namespace MNN { namespace CUDA { -struct CutlassGemmInfo{ - int elh[3]; - int elhPad[3]; -}; - class ConvCutlassExecution : public Execution { public: struct Resource { diff --git a/source/backend/cuda/execution/ConvDepthWiseExecution.cu b/source/backend/cuda/execution/ConvDepthWiseExecution.cu index 6e9c8c287..02f3d719d 100755 --- a/source/backend/cuda/execution/ConvDepthWiseExecution.cu +++ b/source/backend/cuda/execution/ConvDepthWiseExecution.cu @@ -13,7 +13,10 @@ __global__ void CONV_DW(const T* input, const half* kernel, const half* bias, T *output, - const constBuffer* uConstant + const constBuffer* uConstant, + DivModFast d_oc, + DivModFast d_ow, + DivModFast d_oh ) { float maxV = uConstant->maxValue; float minV = uConstant->minValue; @@ -32,17 +35,18 @@ __global__ void CONV_DW(const T* input, int pw = uConstant->pad[0]; int ph = uConstant->pad[1]; - for (size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < uConstant->total; index += blockDim.x * gridDim.x) { - int i = index / c_p; - int oz = index % c_p; - int ob = i / (ow * oh); - int tmp = i % (ow * oh); - int oy = tmp / ow; - int ox = tmp % ow; + for (size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < uConstant->total/2; index += blockDim.x * gridDim.x) { + int oz_2, tmp2, oy, ox, tmp1, ob; + d_oc.divmod(index, tmp1, oz_2); + d_ow.divmod(tmp1, tmp2, ox); + d_oh.divmod(tmp2, ob, oy); + int oz = oz_2 << 1; int ix = ox * sw - pw; int iy = oy * sh - ph; - float color = bias[oz]; + float color0 = bias[oz]; + float color1 = bias[oz+1]; + int fxSta = max(0, (UP_DIV(-ix, dw))); int fySta = max(0, (UP_DIV(-iy, dh))); int fxEnd = min(kw, UP_DIV(iw - ix, dw)); @@ -52,32 +56,190 @@ __global__ void CONV_DW(const T* input, int sy = fy*dh + iy; for (fx=fxSta; fxmaxValue; + float minV = uConstant->minValue; + int iw = uConstant->inputSize[0]; + int ih = uConstant->inputSize[1]; + int c = uConstant->channel; + int c_p = c * PACK_NUMBER / 2; + int ow = uConstant->outputSize[0]; + int oh = uConstant->outputSize[1]; + int kw = uConstant->kernelSize[0]; + int kh = uConstant->kernelSize[1]; + int sw = uConstant->stride[0]; + int sh = uConstant->stride[1]; + int pw = uConstant->pad[0]; + int ph = uConstant->pad[1]; + + for (size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < uConstant->total/2; index += blockDim.x * gridDim.x) { + int oz_2, tmp2, oy, ox, tmp1, ob; + d_oc.divmod(index, tmp1, oz_2); + d_ow.divmod(tmp1, tmp2, ox); + d_oh.divmod(tmp2, ob, oy); + + int oz = oz_2; + int ix = ox * sw - pw; + int iy = oy * sh - ph; + half2 color = bias[oz]; + + int fxSta = max(0, -ix); + int fySta = max(0, -iy); + int fxEnd = min(kw, iw - ix); + int fyEnd = min(kh, ih - iy); + int fx, fy, fz; + for (fy=fySta; fymaxValue; + float minV = uConstant->minValue; + int iw = uConstant->inputSize[0]; + int ih = uConstant->inputSize[1]; + int c = uConstant->channel; + int c_p = c * PACK_NUMBER / 2; + int ow = uConstant->outputSize[0]; + int oh = uConstant->outputSize[1]; + + for (size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < uConstant->total/4; index += blockDim.x * gridDim.x) { + int oz_2, tmp2, oy, ox_2, tmp1, ob; + d_oc.divmod(index, tmp1, oz_2); + d_ow.divmod(tmp1, tmp2, ox_2); + d_oh.divmod(tmp2, ob, oy); + + int oz = oz_2; + int ox = ox_2 << 1; + int ix = ox - 1; + int iy = oy - 1; + half2 color0 = bias[oz]; + half2 color1 = color0; + + half2 zero; + zero.x = (half)0.0; + zero.y = (half)0.0; + + half2 inp[12]; + half2 ker[3][3]; + for(int j=0; j<3; j++) { + if(iy < 0 && j==0) { + for(int i=0; i<4; i++) { + inp[i] = zero; + } + continue; + } + if(iy+2 > ih-1 && j==2) { + for(int i=0; i<4; i++) { + inp[8+i] = zero; + } + continue; + } + + for(int i=0; i<4; i++) { + if(ix < 0 && i==0) { + for(int j=0; j<3; j++) { + inp[4*j+0] = zero; + } + continue; + } + if(ix+3 > iw-1 && i==3) { + for(int j=0; j<3; j++) { + inp[4*j+3] = zero; + } + continue; + } + int src_offset = ((ob * ih + iy+j) * iw + ix+i) * c_p + oz; + inp[4*j+i] = input[src_offset]; + } + } + + for(int j=0; j<3; j++) { + for(int i=0; i<3; i++) { + ker[j][i] = kernel[(j * 3 + i) * c_p + oz]; + } + } + + for(int j=0; j<3; j++) { + for(int i=0; i<3; i++) { + color0 = __hfma2(inp[4*j+i], ker[j][i], color0); + color1 = __hfma2(inp[4*j+i+1], ker[j][i], color1); + } + } + + color0.x = max(color0.x, minV); + color0.x = min(color0.x, maxV); + color0.y = max(color0.y, minV); + color0.y = min(color0.y, maxV); + + color1.x = max(color1.x, minV); + color1.x = min(color1.x, maxV); + color1.y = max(color1.y, minV); + color1.y = min(color1.y, maxV); + + int dst_offset = ((ob * oh + oy) * ow + ox) * c_p + oz; + output[dst_offset] = color0; + output[dst_offset+c_p] = color1; + } +} __global__ void CONV_DW_OPT(const float* input, const half* kernel, const half* bias, float *output, const constBuffer* uConstant, DivModFast d_oc, @@ -88,6 +250,8 @@ __global__ void CONV_DW_OPT(const float* input, const half* kernel, const half* float minV = uConstant->minValue; int iw = uConstant->inputSize[0]; int ih = uConstant->inputSize[1]; + int ow = uConstant->outputSize[0]; + int oh = uConstant->outputSize[1]; int kw = uConstant->kernelSize[0]; int kh = uConstant->kernelSize[1]; int sw = uConstant->stride[0]; @@ -97,15 +261,18 @@ __global__ void CONV_DW_OPT(const float* input, const half* kernel, const half* int c = uConstant->channel; int c_p = c * PACK_NUMBER; - for (size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < uConstant->total; index += blockDim.x * gridDim.x) { - int oz, tmp2, oy, ox, tmp1, ob; - d_oc.divmod(index, tmp1, oz); + for (size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < uConstant->total / 2; index += blockDim.x * gridDim.x) { + int oz_2, tmp2, oy, ox, tmp1, ob; + d_oc.divmod(index, tmp1, oz_2); d_ow.divmod(tmp1, tmp2, ox); d_oh.divmod(tmp2, ob, oy); + int oz = oz_2 << 1; int ix = ox * sw - pw; int iy = oy * sh - ph; - float color = bias[oz]; + float color0 = bias[oz]; + float color1 = bias[oz+1]; + int fxSta = max(0, -ix); int fySta = max(0, -iy); int fxEnd = min(kw, iw - ix); @@ -115,25 +282,28 @@ __global__ void CONV_DW_OPT(const float* input, const half* kernel, const half* int sy = fy + iy; for (fx=fxSta; fx _makeResource(const Op* op, Backend* bn) { @@ -162,21 +332,22 @@ static std::shared_ptr _makeResource(const Op* int weightSize = 0; std::shared_ptr quanCommon; ConvolutionCommon::getConvParameters(&quanCommon, conv, &filterDataPtr, &weightSize); - auto tempWeightStorage = pool->alloc(weightSize * sizeof(float)); + auto tempWeightStorage = pool->alloc(depthC * PACK_NUMBER * kernelY * kernelX * sizeof(float)); auto tempWeight = (uint8_t*)tempWeightStorage.first + tempWeightStorage.second; + cuda_check(cudaMemset(tempWeight, 0, depthC * PACK_NUMBER * kernelY * kernelX * sizeof(float))); cuda_check(cudaMemcpy(tempWeight, filterDataPtr, weightSize*sizeof(float), cudaMemcpyHostToDevice)); reg.size[0] = 1; - reg.size[1] = depthC * PACK_NUMBER; - reg.size[2] = kernelY * kernelX; + reg.size[1] = kernelY * kernelX; + reg.size[2] = depthC * PACK_NUMBER; reg.srcStride[0] = 0; - reg.srcStride[1] = kernelY * kernelX; - reg.srcStride[2] = 1; + reg.srcStride[1] = 1; + reg.srcStride[2] = kernelY * kernelX; reg.dstStride[0] = 0; - reg.dstStride[1] = kernelY * kernelX; + reg.dstStride[1] = depthC * PACK_NUMBER; reg.dstStride[2] = 1; offset[0] = 1; - offset[1] = depth; - offset[2] = kernelY * kernelX; + offset[1] = kernelY * kernelX; + offset[2] = depth; offset[3] = 0; offset[4] = 1; offset[5] = reg.size[1]; @@ -276,7 +447,7 @@ ErrorCode ConvDepthWiseExecution::onResize(const std::vector &inputs, auto runtime = static_cast(backend())->getCUDARuntime(); runtime->memcpy((uint8_t*)mConstBuffer.first + mConstBuffer.second, ¶meters, sizeof(constBuffer), MNNMemcpyHostToDevice); mTotalCount = parameters.total; - //printf("%d-%d-%d-%d, %d-%d-%d-%d-%d\n", parameters.kernelSize[0], parameters.kernelSize[1], parameters.stride[0], parameters.stride[1], parameters.inputSize[0], parameters.inputSize[1], channel, parameters.outputSize[0], parameters.outputSize[1]); + //MNN_PRINT("%d-%d-%d-%d, %d-%d-%d-%d-%d\n", parameters.kernelSize[0], parameters.kernelSize[1], parameters.stride[0], parameters.stride[1], parameters.inputSize[0], parameters.inputSize[1], channel, parameters.outputSize[0], parameters.outputSize[1]); return NO_ERROR; } @@ -287,10 +458,31 @@ ErrorCode ConvDepthWiseExecution::onExecute(const std::vector &inputs, int threads_num = ALIMIN(prop.maxThreadsPerBlock/2, limitThreads); int block_num = prop.multiProcessorCount; auto constPtr = (uint8_t*)mConstBuffer.first + mConstBuffer.second; + + DivModFast d_oc(parameters.channel * PACK_NUMBER / 2); + DivModFast d_ow(parameters.outputSize[0]); + DivModFast d_oh(parameters.outputSize[1]); + if (static_cast(backend())->useFp16()) { - if (inputs.size() == 1) { + if(parameters.kernelSize[0]==3 && parameters.kernelSize[1]==3 && parameters.stride[0]==1 && parameters.stride[1]==1 && parameters.pad[0]==1 && parameters.pad[1]==1 && parameters.outputSize[0] % 2 ==0) { + DivModFast d_ow2(parameters.outputSize[0]/2); + + CONV_DW3x3_HALF2_OPT<<>>((const half2*)inputs[0]->deviceId(), (const half2*)mResource->mFilter, + (const half2*)mResource->mBias, (half2*)outputs[0]->deviceId(), (const constBuffer*)(constPtr), + d_oc, d_ow2, d_oh); + checkKernelErrors; + return NO_ERROR; + } + if(parameters.dilate[0] == 1 && parameters.dilate[1] == 1) { + CONV_DW_HALF2_OPT<<>>((const half2*)inputs[0]->deviceId(), (const half2*)mResource->mFilter, + (const half2*)mResource->mBias, (half2*)outputs[0]->deviceId(), (const constBuffer*)(constPtr), + d_oc, d_ow, d_oh);//_HALF_OPT + checkKernelErrors; + } else { CONV_DW<<>>((const half*)inputs[0]->deviceId(), (const half*)mResource->mFilter, - (const half*)mResource->mBias, (half*)outputs[0]->deviceId(), (const constBuffer*)(constPtr)); + (const half*)mResource->mBias, (half*)outputs[0]->deviceId(), (const constBuffer*)(constPtr), + d_oc, d_ow, d_oh); + checkKernelErrors; } return NO_ERROR; } @@ -298,18 +490,16 @@ ErrorCode ConvDepthWiseExecution::onExecute(const std::vector &inputs, if (inputs.size() == 1) { // block_num = runtime->blocks_num(mTotalCount); // threads_num = runtime->threads_num(); - if(parameters.dilate[0] == 1 && parameters.dilate[1] == 1) { - const int area = parameters.outputSize[0] * parameters.outputSize[1]; - DivModFast d_oc(parameters.channel * PACK_NUMBER); - DivModFast d_ow(parameters.outputSize[0]); - DivModFast d_oh(parameters.outputSize[1]); - + if(parameters.dilate[0] == 1 && parameters.dilate[1] == 1) { CONV_DW_OPT<<>>((const float*)inputs[0]->deviceId(), (const half*)mResource->mFilter, (const half*)mResource->mBias, (float*)outputs[0]->deviceId(), (const constBuffer*)(constPtr), d_oc, d_ow, d_oh); + checkKernelErrors; } else { CONV_DW<<>>((const float*)inputs[0]->deviceId(), (const half*)mResource->mFilter, - (const half*)mResource->mBias, (float*)outputs[0]->deviceId(), (const constBuffer*)(constPtr)); + (const half*)mResource->mBias, (float*)outputs[0]->deviceId(), (const constBuffer*)(constPtr), + d_oc, d_ow, d_oh); + checkKernelErrors; } } return NO_ERROR; diff --git a/source/backend/cuda/execution/ConvSingleInputExecution.cu b/source/backend/cuda/execution/ConvSingleInputExecution.cu index 854ac805b..6a7a81b22 100644 --- a/source/backend/cuda/execution/ConvSingleInputExecution.cu +++ b/source/backend/cuda/execution/ConvSingleInputExecution.cu @@ -13,6 +13,9 @@ #include "MNNCUDADefine.hpp" #include "MNNCUDAFunction.cuh" +#include "common/MemoryFormater.h" +#include "backend/cuda/core/CUDATools.hpp" + // 16 / sizeof(int4) namespace MNN { namespace CUDA { @@ -100,6 +103,8 @@ ConvSingleInputExecution::Resource::Resource(Backend* bn, const MNN::Op* op) { auto offsetGpuStorage = static_cast(bn)->getStaticBufferPool()->alloc(sizeof(int) * maxOffsetNumber); auto offsetGpu = (uint8_t*)offsetGpuStorage.first + offsetGpuStorage.second; + + NVTX_PUSH("cuda_conv_weight"); // Reorder weight { auto tempCacheBuffer = static_cast(bn)->getStaticBufferPool()->alloc(weightSize * sizeof(float)); @@ -121,9 +126,13 @@ ConvSingleInputExecution::Resource::Resource(Backend* bn, const MNN::Op* op) { } static_cast(bn)->getStaticBufferPool()->free(tempCacheBuffer); } + NVTX_POP(); + // Copy Bias int biasSize = conv->bias()->size(); + + NVTX_PUSH("cuda_conv_bias"); biasTensor.reset(Tensor::createDevice({biasSize})); bn->onAcquireBuffer(biasTensor.get(), Backend::STATIC); @@ -159,6 +168,7 @@ ConvSingleInputExecution::Resource::Resource(Backend* bn, const MNN::Op* op) { } else { FuseRasterBlitCommon((uint8_t*)mBias, (uint8_t*)biasTemp, (FuseRegion*)((uint8_t*)regionStorage.first + regionStorage.second), offsetGpu, runtime, 4); } + NVTX_POP(); static_cast(bn)->getStaticBufferPool()->free(regionStorage); static_cast(bn)->getStaticBufferPool()->free(offsetGpuStorage); static_cast(bn)->getStaticBufferPool()->free(tempBiasStorage); @@ -219,6 +229,7 @@ ErrorCode ConvSingleInputExecution::onResize(const std::vector &inputs, mIm2ColParamter.srcYStep = input->width() * UNIT; mIm2ColParamter.packCUnit = UNIT; + // hostToDevice runtime->memcpy((uint8_t*)mGpuIm2ColParam.first + mGpuIm2ColParam.second, &mIm2ColParamter, sizeof(ConvolutionCommon::Im2ColParameter), MNNMemcpyHostToDevice); //MNN_PRINT("conv size:%d-%d, %d-%d-%d, %d-%d-%d\n", mIm2ColParamter.kernelX, mIm2ColParamter.strideX, input->height(), input->width(), input->channel(), output->height(), output->width(), output->channel()); @@ -267,7 +278,7 @@ ErrorCode ConvSingleInputExecution::onResize(const std::vector &inputs, auto buffer = pool->alloc((size_t)sizeof(__half) * (size_t)mMatMulParam.elhPack[0] * (size_t)mMatMulParam.elhPack[1] * (size_t)ePack * (size_t)hPack); mIm2ColBuffer = (__half*)((uint8_t*)buffer.first + buffer.second); pool->free(buffer); - + return NO_ERROR; } @@ -289,6 +300,9 @@ ErrorCode ConvSingleInputExecution::onExecute(const std::vector &inputs auto gpuIm2Col = (const ConvolutionCommon::Im2ColParameter*)((uint8_t*)mGpuIm2ColParam.first + mGpuIm2ColParam.second); auto gpuMatMul = (const MatMulParam*)((uint8_t*)mGpuMatMulParam.first + mGpuMatMulParam.second); + + // MNN_PRINT("onExecute bytes is:%d mUseEPack:%d, mResource->mUseHPack:%d, useFp16:%d, mBlockNum:%d,3 dimPack:{ePack:%d, lPack:%d, hPack:%d}, mMatMulParam.elh:{%d,%d,%d}, elhMultiPack:{%d,%d,%d}\n", + // bytes, mUseEPack, mResource->mUseHPack, static_cast(backend())->useFp16(), mBlockNum, ePack, MATMULPACK, hPack, mMatMulParam.elh[0], mMatMulParam.elh[1], mMatMulParam.elh[2], mMatMulParam.elhPack[0], mMatMulParam.elhPack[1], mMatMulParam.elhPack[2]); // Im2col in Block for(int block_idx = 0; block_idx < mBlockNum; block_idx++) { if(mUseEPack) { @@ -307,9 +321,11 @@ ErrorCode ConvSingleInputExecution::onExecute(const std::vector &inputs return NO_ERROR; } +// #define USE_MNN_CONV + class CUDAConvolutionCreator : public CUDABackend::Creator { public: - virtual Execution* onCreate(const std::vector& inputs, const std::vector& outputs, + virtual Execution* onCreate(const std::vector& inputs, const std::vector& outputs, const MNN::Op* op, Backend* backend) const override { if (nullptr != op->main_as_Convolution2D()->quanParameter()) { auto quan = op->main_as_Convolution2D()->quanParameter(); @@ -321,19 +337,24 @@ public: } } +#ifdef USE_MNN_CONV + + std::shared_ptr resource(new ConvSingleInputExecution::Resource(backend, op)); + return new ConvSingleInputExecution(backend, op, resource); + +#else auto conv = op->main_as_Convolution2D()->common(); - if(ConvWinogradExecution::isValid(op->main_as_Convolution2D(), inputs[0])) { + if(ConvWinogradExecution::isValid(op->main_as_Convolution2D())) { // inputs[0] is invalid now. //printf("%dx%ds%dd%d\n", conv->kernelX(), conv->kernelY(), conv->strideX(), conv->dilateX()); std::shared_ptr resource(new ConvWinogradExecution::Resource(backend, op)); return new ConvWinogradExecution(backend, op, resource); } - // std::shared_ptr resource(new ConvSingleInputExecution::Resource(backend, op)); - // return new ConvSingleInputExecution(backend, op, resource); - std::shared_ptr resource(new ConvCutlassExecution::Resource(backend, op)); return new ConvCutlassExecution(backend, op, resource); +#endif + } }; diff --git a/source/backend/cuda/execution/ConvWinogradExecution.cu b/source/backend/cuda/execution/ConvWinogradExecution.cu index a113e79a4..37cfbae5e 100644 --- a/source/backend/cuda/execution/ConvWinogradExecution.cu +++ b/source/backend/cuda/execution/ConvWinogradExecution.cu @@ -15,24 +15,26 @@ namespace CUDA { #define UNIT 2 __global__ void WinoWeightReorder(const float* GgGt, half* GgGt_trans, - const int outside, + const int block, + const int co_pack, + const int ci_pack, const int unitCi, const int unitCo ) { - const int maxCount = outside * unitCi * unitCo; + const int maxCount = block * co_pack * ci_pack; for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += gridDim.x * blockDim.x) { - size_t outside_idx = index / (unitCi*unitCo); - size_t tmp = index % (unitCi*unitCo); - size_t ci_idx = tmp / unitCo; - size_t co_idx = tmp % unitCo; + size_t tmp = index / ci_pack; + size_t ci_idx = index % ci_pack; - // [4x4, Cop, Cip, unitCi, unitCo] -->> [4x4, Cop, Cip, unitCo, unitCi] - size_t dst_idx = outside_idx * (unitCi*unitCo) + co_idx * unitCi + ci_idx; - *(GgGt_trans + dst_idx) = *(GgGt + index); + size_t block_idx = tmp / co_pack; + size_t co_idx = tmp % co_pack; + // [4x4, Cop, Cip, unitCi, unitCo] -->> [4x4, Cop*unitCo, Cip*unitCi] + size_t src_idx = block_idx * (co_pack*ci_pack) + (co_idx/unitCo) * (ci_pack*unitCo) + (ci_idx/unitCi) * (unitCi*unitCo) + (ci_idx%unitCi) * unitCo + (co_idx%unitCo); + *(GgGt_trans + index) = *(GgGt + src_idx); } } -bool ConvWinogradExecution::isValid(const Convolution2D* conv, const Tensor* input) { +bool ConvWinogradExecution::isValid(const Convolution2D* conv) { //return false; if(conv->common()->strideX() != 1 || conv->common()->strideY() != 1) { return false; @@ -74,7 +76,7 @@ ConvWinogradExecution::Resource::Resource(Backend* backend, const MNN::Op* op) { std::shared_ptr srcWeight(Tensor::create({mKernelInfo.kernelN, mKernelInfo.kernelC, mKernelInfo.kernelY, mKernelInfo.kernelX}, (void *)filterDataPtr, Tensor::CAFFE)); - auto dstWeight = generator.allocTransformWeight(srcWeight.get(), MATMULPACK, MATMULPACK); + auto dstWeight = generator.allocTransformWeight(srcWeight.get(), PACK_NUMBER, PACK_NUMBER); generator.transformWeight(dstWeight.get(), srcWeight.get()); auto dstWeightSize = dstWeight->elementSize(); @@ -90,18 +92,18 @@ ConvWinogradExecution::Resource::Resource(Backend* backend, const MNN::Op* op) { int cores = prop.multiProcessorCount; int threadNumbers = prop.maxThreadsPerBlock; - int coDiv = UP_DIV(mKernelInfo.kernelN, MATMULPACK); - int ciDiv = UP_DIV(mKernelInfo.kernelC, MATMULPACK); + int coPack = UP_DIV(mKernelInfo.kernelN, PACK_NUMBER) * PACK_NUMBER; + int ciPack = UP_DIV(mKernelInfo.kernelC, PACK_NUMBER) * PACK_NUMBER; WinoWeightReorder<<>>((float*)cacheWeight, (half*)mFilter, - (UNIT+kernel-1) * (UNIT+kernel-1) * coDiv * ciDiv, MATMULPACK, MATMULPACK); + (UNIT+kernel-1) * (UNIT+kernel-1), coPack, ciPack, PACK_NUMBER, PACK_NUMBER); static_cast(backend)->getStaticBufferPool()->free(tempCacheBuffer); } // Copy Bias int biasSize = conv->bias()->size(); - int alignSize = UP_DIV(biasSize, MATMULPACK) * MATMULPACK; + int alignSize = UP_DIV(biasSize, PACK_NUMBER) * PACK_NUMBER; biasTensor.reset(Tensor::createDevice({alignSize})); backend->onAcquireBuffer(biasTensor.get(), Backend::STATIC); @@ -148,23 +150,23 @@ ErrorCode ConvWinogradExecution::onResize(const std::vector &inputs, c mPadX = std::get<0>(pads); mPadY = std::get<1>(pads); int ic = input->channel(); - int icDiv = UP_DIV(ic, MATMULPACK); + int icDiv = UP_DIV(ic, PACK_NUMBER); auto bytes = static_cast(backend())->getBytes(input); auto wUnit = UP_DIV(output->width(), UNIT); auto hUnit = UP_DIV(output->height(), UNIT); int e = wUnit * hUnit * output->batch(); - int l = icDiv * MATMULPACK; + int l = ic; int h = output->channel(); mMatMulParam.elh[0] = e; mMatMulParam.elh[1] = l; mMatMulParam.elh[2] = h; - int ePack = MATMULPACK; - int hPack = MATMULPACK; + int ePack = PACK_NUMBER; + int hPack = PACK_NUMBER; mMatMulParam.elhPack[0] = UP_DIV(e, ePack); - mMatMulParam.elhPack[1] = UP_DIV(l, MATMULPACK); + mMatMulParam.elhPack[1] = UP_DIV(l, PACK_NUMBER); mMatMulParam.elhPack[2] = UP_DIV(h, hPack); // mMatMulParam.cStride[0] = mIm2ColParamter.ow * mIm2ColParamter.oh * h; // mMatMulParam.cStride[1] = 1; @@ -185,14 +187,87 @@ ErrorCode ConvWinogradExecution::onResize(const std::vector &inputs, c int block = UNIT + convCommon->kernelY() - 1; mBlock2 = block * block; auto pool = static_cast(backend())->getBufferPool(); - auto buffer = pool->alloc((size_t)sizeof(__half) * mBlock2 * mMatMulParam.elhPack[0] * mMatMulParam.elhPack[1] * (size_t)ePack * (size_t)MATMULPACK); - mBtdB_Buffer = (__half*)((uint8_t*)buffer.first + buffer.second); + auto bufferData = pool->alloc((size_t)sizeof(__half) * mBlock2 * mMatMulParam.elhPack[0] * mMatMulParam.elhPack[1] * (size_t)ePack * (size_t)PACK_NUMBER); + mBtdB_Buffer = (__half*)((uint8_t*)bufferData.first + bufferData.second); - auto buffer2 = pool->alloc(bytes * mBlock2 * mMatMulParam.elh[0] * mMatMulParam.elhPack[2] * (size_t)hPack); - mMatmul_Buffer = (void*)((uint8_t*)buffer2.first + buffer2.second); + auto bufferMatmul = pool->alloc(bytes * mBlock2 * mMatMulParam.elh[0] * mMatMulParam.elhPack[2] * (size_t)hPack); + mMatmul_Buffer = (void*)((uint8_t*)bufferMatmul.first + bufferMatmul.second); - pool->free(buffer); - pool->free(buffer2); + pool->free(bufferData); + pool->free(bufferMatmul); + + + mGemmInfo.elh[0] = e; + mGemmInfo.elh[1] = l; + mGemmInfo.elh[2] = h; + mGemmInfo.elhPad[0] = UP_DIV(e, 8) * 8; + mGemmInfo.elhPad[1] = UP_DIV(l, 8) * 8; + mGemmInfo.elhPad[2] = UP_DIV(h, 8) * 8; + + ElementComputeEpilogue alpha = ElementComputeEpilogue(1); + ElementComputeEpilogue beta = ElementComputeEpilogue(0); + + // Split K dimension into 1 partitions + cutlass::gemm::GemmCoord problem_size(mGemmInfo.elh[0], mGemmInfo.elhPad[2], mGemmInfo.elhPad[1]);// m n k + + //MNN_PRINT("Winograd BatchGemm batch:%d, MNK:%d-%d-%d\n", mBlock2, mGemmInfo.elh[0], mGemmInfo.elhPad[2], mGemmInfo.elhPad[1]); + if(bytes == 2) { + typename GemmBatched_F16_Linear_Sm75::Arguments arguments{problem_size, // <- problem size of matrix multiplication + {(ElementInputA *)mBtdB_Buffer, mGemmInfo.elhPad[1]}, // Ptr + ldm + (int64_t)(mGemmInfo.elh[0] * mGemmInfo.elhPad[1]), // batch_stride_A + {(ElementInputB *)mResource->mFilter, mGemmInfo.elhPad[1]}, // Ptr + ldm + (int64_t)(mGemmInfo.elhPad[1] * mGemmInfo.elhPad[2]), // batch_stride_B + {(ElementOutput_F16 *)mResource->mBias, 0}, // Ptr + ldm if ldm = 0, vector, + (int64_t)(0), // batch_stride_bias + {(ElementOutput_F16 *)mMatmul_Buffer, mGemmInfo.elhPad[2]}, // Ptr + ldm + (int64_t)(mGemmInfo.elh[0] * mGemmInfo.elhPad[2]), // batch_stride_C + {alpha, beta}, // <- tuple of alpha and beta + mBlock2}; // batch_count + + size_t workspace_size = GemmBatched_F16_Linear_Sm75::get_workspace_size(arguments); + + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; + runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); + pool->free(bufferWs); + + // Check the problem size is supported or not + cutlass::Status status = mGemmBatchedF16LnSm75.can_implement(arguments); + cutlass_check(status); + + // Initialize CUTLASS kernel with arguments and workspace pointer + status = mGemmBatchedF16LnSm75.initialize(arguments, (uint8_t *)mWorkspace); + cutlass_check(status); + } else { + + typename GemmBatched_F32_Linear_Sm75::Arguments arguments{problem_size, // <- problem size of matrix multiplication + {(ElementInputA *)mBtdB_Buffer, mGemmInfo.elhPad[1]}, // Ptr + ldm + (int64_t)(mGemmInfo.elh[0] * mGemmInfo.elhPad[1]), // batch_stride_A + {(ElementInputB *)mResource->mFilter, mGemmInfo.elhPad[1]}, // Ptr + ldm + (int64_t)(mGemmInfo.elhPad[1] * mGemmInfo.elhPad[2]), // batch_stride_B + {(ElementOutput_F32 *)mResource->mBias, 0}, // Ptr + ldm if ldm = 0, vector, + (int64_t)(0), // batch_stride_bias + {(ElementOutput_F32 *)mMatmul_Buffer, mGemmInfo.elhPad[2]}, // Ptr + ldm + (int64_t)(mGemmInfo.elh[0] * mGemmInfo.elhPad[2]), // batch_stride_C + {alpha, beta}, // <- tuple of alpha and beta + mBlock2}; // batch_count + + size_t workspace_size = GemmBatched_F32_Linear_Sm75::get_workspace_size(arguments); + + auto bufferWs = pool->alloc(workspace_size * sizeof(uint8_t)); + mWorkspace = (uint8_t*)bufferWs.first + bufferWs.second; + runtime->memset(mWorkspace, 0, workspace_size * sizeof(uint8_t)); + pool->free(bufferWs); + + // Check the problem size is supported or not + cutlass::Status status = mGemmBatchedF32LnSm75.can_implement(arguments); + cutlass_check(status); + + // Initialize CUTLASS kernel with arguments and workspace pointer + status = mGemmBatchedF32LnSm75.initialize(arguments, (uint8_t *)mWorkspace); + cutlass_check(status); + } + return NO_ERROR; } @@ -205,8 +280,8 @@ ErrorCode ConvWinogradExecution::onExecute(const std::vector &inputs, c int threadNumbers = prop.maxThreadsPerBlock / 2; auto gpuMatMul = (const MatMulParam*)((uint8_t*)mGpuMatMulParam.first + mGpuMatMulParam.second); - int coDiv = UP_DIV(mResource->mKernelInfo.kernelN, MATMULPACK); - int ciDiv = UP_DIV(mResource->mKernelInfo.kernelC, MATMULPACK); + int co_pack = UP_DIV(mResource->mKernelInfo.kernelN, PACK_NUMBER) * PACK_NUMBER; + int ci_pack = UP_DIV(mResource->mKernelInfo.kernelC, PACK_NUMBER) * PACK_NUMBER; auto bytes = static_cast(backend())->getBytes(input); const void *input_addr = (const void*)input->deviceId(); @@ -215,16 +290,23 @@ ErrorCode ConvWinogradExecution::onExecute(const std::vector &inputs, c void *output_addr = (void*)output->deviceId(); const int kernel = 3; + const int wUnit = UP_DIV(input->width(), UNIT); + const int hUnit = UP_DIV(input->height(), UNIT); + DivModFast lD(ci_pack); + DivModFast hD(co_pack); + DivModFast whD(wUnit * hUnit); + DivModFast wD(wUnit); + if(bytes == 4) { WinoInputTrans<<>>((const float*)input_addr, (half*)mBtdB_Buffer, UNIT, - (UNIT+kernel-1)*(UNIT+kernel-1), input->channel(), ciDiv, output->batch(), UP_DIV(input->width(), UNIT), - UP_DIV(input->height(), UNIT), MATMULPACK, MATMULPACK, + (UNIT+kernel-1)*(UNIT+kernel-1), input->channel(), ci_pack, + mMatMulParam.elh[0] * ci_pack, lD, whD, wD, mPadX, mPadY, input->width(), input->height()); checkKernelErrors; } else { WinoInputTrans<<>>((const half*)input_addr, (half*)mBtdB_Buffer, UNIT, - (UNIT+kernel-1)*(UNIT+kernel-1), input->channel(), ciDiv, output->batch(), UP_DIV(input->width(), UNIT), - UP_DIV(input->height(), UNIT), MATMULPACK, MATMULPACK, + (UNIT+kernel-1)*(UNIT+kernel-1), input->channel(), ci_pack, + mMatMulParam.elh[0] * ci_pack, lD, whD, wD, mPadX, mPadY, input->width(), input->height()); checkKernelErrors; } @@ -235,41 +317,27 @@ ErrorCode ConvWinogradExecution::onExecute(const std::vector &inputs, c int iBlock = 0; if (4 == bytes) { - cudaFuncSetAttribute(GemmPackedMulti, cudaFuncAttributeMaxDynamicSharedMemorySize, prop.sharedMemPerMultiprocessor); - GemmPackedMulti<<>>(gpuMatMul, iBlock, mBlock2, (float*)mMatmul_Buffer, mBtdB_Buffer, (const __half*)mGgGt_Buffer); - checkKernelErrors; + cutlass::Status status = mGemmBatchedF32LnSm75(); + cutlass_check(status); } else { - //MNN_PRINT("%d - %d, %d- %d\n", cpuParam->elhPack[0], cpuParam->elhPack[2], cpuParam->elh[0], cpuParam->elh[2]); - cudaFuncSetAttribute(GemmPackedMulti, cudaFuncAttributeMaxDynamicSharedMemorySize, prop.sharedMemPerMultiprocessor); - GemmPackedMulti<<>>(gpuMatMul, iBlock, mBlock2, (half*)mMatmul_Buffer, mBtdB_Buffer, (const __half*)mGgGt_Buffer); - checkKernelErrors; + cutlass::Status status = mGemmBatchedF16LnSm75(); + cutlass_check(status); } if (4 == bytes) { WinoTrans2Output<<>>((const float*)mMatmul_Buffer, (const float*)bias_addr, (float*)output_addr, - gpuMatMul, UNIT, - mBlock2, output->channel(), ciDiv, output->batch(), UP_DIV(output->width(), UNIT), - UP_DIV(output->height(), UNIT), MATMULPACK, MATMULPACK, + gpuMatMul, UNIT, mBlock2, output->channel(), co_pack, + mMatMulParam.elh[0] * co_pack, hD, whD, wD, output->width(), output->height()); checkKernelErrors; } else { WinoTrans2Output<<>>((const half*)mMatmul_Buffer, (const float*)bias_addr, (half*)output_addr, - gpuMatMul, UNIT, - mBlock2, output->channel(), ciDiv, output->batch(), UP_DIV(output->width(), UNIT), - UP_DIV(output->height(), UNIT), MATMULPACK, MATMULPACK, + gpuMatMul, UNIT, mBlock2, output->channel(), co_pack, + mMatMulParam.elh[0] * co_pack, hD, whD, wD, output->width(), output->height()); checkKernelErrors; } - - // if(output->width() == 56 && output->channel() == 64 && input->channel() == 64) { - // cudaDeviceSynchronize(); - // float bias_[mMatMulParam.elhPack[2] * 16]; - // runtime->memcpy((void*)bias_, bias_addr, mMatMulParam.elhPack[2] * 16*sizeof(float), MNNMemcpyDeviceToHost); - // for(int i=0; i res); virtual ~ConvWinogradExecution(); @@ -45,6 +48,13 @@ private: void* mMatmul_Buffer; MatMulParam mMatMulParam; std::pair mGpuMatMulParam; + GemmBatched_F16_Linear_Sm75 mGemmBatchedF16LnSm75; + GemmBatched_F32_Linear_Sm75 mGemmBatchedF32LnSm75; + + std::shared_ptr workspaceTensor; + uint8_t* mWorkspace; + + CutlassGemmInfo mGemmInfo; int mPadX; int mPadY; diff --git a/source/backend/cuda/execution/CutlassGemmParam.hpp b/source/backend/cuda/execution/CutlassGemmParam.hpp index 3e3dc9373..ce28158d5 100644 --- a/source/backend/cuda/execution/CutlassGemmParam.hpp +++ b/source/backend/cuda/execution/CutlassGemmParam.hpp @@ -11,10 +11,17 @@ #include "cutlass/epilogue/thread/linear_combination_relu.h" #include "cutlass/epilogue/thread/linear_combination_relu6.h" #include "cutlass/gemm/device/gemm.h" +#include "cutlass/gemm/device/gemm_array.h" +#include "cutlass/gemm/device/gemm_batched.h" namespace MNN { namespace CUDA { +struct CutlassGemmInfo{ + int elh[3]; + int elhPad[3]; +}; + using ElementAccumulator = float; // <- data type of accumulator using ElementComputeEpilogue = ElementAccumulator; // <- data type of epilogue operations using ElementInputA = cutlass::half_t; // <- data type of elements in input matrix A @@ -37,9 +44,9 @@ using SmArch75 = cutlass::arch::Sm75; // This code section describes the tile size a thread block will compute using ShapeMMAThreadBlock = - cutlass::gemm::GemmShape<64, 64, 32>; // <- threadblock tile M = 128, N = 256, K = 64 + cutlass::gemm::GemmShape<64, 64, 64>; // <- threadblock tile M = 128, N = 256, K = 64 // This code section describes tile size a warp will compute -using ShapeMMAWarp = cutlass::gemm::GemmShape<32, 32, 32>; // <- warp tile M = 64, N = 64, K = 64 +using ShapeMMAWarp = cutlass::gemm::GemmShape<32, 32, 64>; // <- warp tile M = 64, N = 64, K = 64 // This code section describes the size of MMA op using ShapeMMAOp1688 = cutlass::gemm::GemmShape<16, 8, 8>; // <- MMA Op tile M = 8, N = 8, K = 16 using ShapeMMAOp884 = cutlass::gemm::GemmShape<8, 8, 4>; // <- MMA Op tile M = 8, N = 8, K = 16 @@ -300,6 +307,45 @@ using Gemm_F32_Relu6_Sm75 = cutlass::gemm::device::Gemm; +// This code section describes how threadblocks are scheduled on GPU +using BatchedSwizzleThreadBlock = cutlass::gemm::threadblock::GemmBatchedIdentityThreadblockSwizzle; // <- ?? + +using ShapeBatchMMAThreadBlock = + cutlass::gemm::GemmShape<64, 64, 64>; // <- threadblock tile M = 128, N = 256, K = 64 +// This code section describes tile size a warp will compute +using ShapeBatchMMAWarp = cutlass::gemm::GemmShape<16, 64, 64>; // <- warp tile M = 64, N = 64, K = 64 + +using GemmBatched_F16_Linear_Sm75 = cutlass::gemm::device::GemmBatched; + +using GemmBatched_F32_Linear_Sm75 = cutlass::gemm::device::GemmBatched; } // namespace CUDA } // namespace MNN diff --git a/source/backend/cuda/execution/Raster.cu b/source/backend/cuda/execution/Raster.cu index f54138cc2..f1e20c0dc 100644 --- a/source/backend/cuda/execution/Raster.cu +++ b/source/backend/cuda/execution/Raster.cu @@ -536,7 +536,7 @@ __global__ void Binary##Name(\ int sizeZ, int sizeY, int sizeX,\ int strideZ, int strideY, int strideX,\ int strideZ1, int strideY1, int strideX1,\ - int dstStrideZ, int dstStrideY, int dstStrideX\ + int dstStrideZ, int dstStrideY, int dstStrideX, int activationType\ ) { \ int count = sizeZ * sizeY * sizeX;\ for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < (count); i += blockDim.x * gridDim.x) {\ @@ -550,7 +550,11 @@ __global__ void Binary##Name(\ int dstOffset = iz * dstStrideZ + iy * dstStrideY + ix * dstStrideX;\ TIn x = input0[srcOffset];\ TIn y = input1[srcOffset1];\ - output[dstOffset] = (TOut)Func;\ + TOut val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset] = val;\ }\ }\ @@ -561,7 +565,7 @@ __global__ void BinaryMid##Name(\ int sizeZ, int sizeY, int sizeX,\ int strideZ, int strideY, int strideX,\ int strideZ1, int strideY1, int strideX1,\ - int dstStrideZ, int dstStrideY, int dstStrideX\ + int dstStrideZ, int dstStrideY, int dstStrideX, int activationType\ ) { \ int count = sizeZ * sizeY * sizeX;\ for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < (count); i += blockDim.x * gridDim.x) {\ @@ -575,7 +579,11 @@ __global__ void BinaryMid##Name(\ int dstOffset = iz * dstStrideZ + iy * dstStrideY + ix * dstStrideX;\ float x = input0[srcOffset];\ float y = input1[srcOffset1];\ - output[dstOffset] = (TOut)(Func);\ + TOut val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset] = val;\ }\ }\ template\ @@ -584,7 +592,8 @@ __global__ void BinaryMidLinear##Name(\ int sizeZ,\ int strideZ,\ int strideZ1,\ - int dstStrideZ\ + int dstStrideZ,\ + int activationType\ ) { \ int count = sizeZ;\ for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < (count); i += blockDim.x * gridDim.x) {\ @@ -594,7 +603,11 @@ __global__ void BinaryMidLinear##Name(\ int dstOffset = iz * dstStrideZ;\ float x = input0[srcOffset];\ float y = input1[srcOffset1];\ - output[dstOffset] = (TOut)(Func);\ + TOut val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset] = val;\ }\ }\ @@ -602,7 +615,7 @@ __global__ void BinaryMidLinear##Name(\ template\ __global__ void BinaryMidLinear4_##Name(\ const TIn *input0, const TIn* input1, TOut *output,\ - int count_4\ + int count_4, int activationType\ ) { \ for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < (count_4); i += blockDim.x * gridDim.x) {\ int iz = i;\ @@ -613,22 +626,38 @@ __global__ void BinaryMidLinear4_##Name(\ float4 yy = ((float4 *)(input1+srcOffset1))[0];\ float x = xx.x;\ float y = yy.x;\ - output[dstOffset] = (TOut)(Func);\ + TOut val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset] = val;\ x = xx.y;\ y = yy.y;\ - output[dstOffset+1] = (TOut)(Func);\ + val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset+1] = val;\ x = xx.z;\ y = yy.z;\ - output[dstOffset+2] = (TOut)(Func);\ + val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset+2] = val;\ x = xx.w;\ y = yy.w;\ - output[dstOffset+3] = (TOut)(Func);\ + val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset+3] = val;\ }\ }\ template\ __global__ void BinaryMidLinearHalf4_##Name(\ const TIn *input0, const TIn* input1, TOut *output,\ - int count_4\ + int count_4, int activationType\ ) { \ for (size_t i = blockIdx.x * blockDim.x + threadIdx.x; i < (count_4); i += blockDim.x * gridDim.x) {\ int iz = i;\ @@ -639,18 +668,34 @@ __global__ void BinaryMidLinearHalf4_##Name(\ half2 yy = ((half2 *)(input1+srcOffset1))[0];\ float x = (float)xx.x;\ float y = (float)yy.x;\ - output[dstOffset] = (TOut)(Func);\ + TOut val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset] = val;\ x = (float)xx.y;\ y = (float)yy.y;\ - output[dstOffset+1] = (TOut)(Func);\ + val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset+1] = val;\ xx = ((half2 *)(input0+srcOffset))[1];\ yy = ((half2 *)(input1+srcOffset1))[1];\ x = (float)xx.x;\ y = (float)yy.x;\ - output[dstOffset+2] = (TOut)(Func);\ + val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset+2] = val;\ x = (float)xx.y;\ y = (float)yy.y;\ - output[dstOffset+3] = (TOut)(Func);\ + val = (TOut)(Func);\ + if(activationType == 1) {\ + val = (val < (TOut)0 ? (TOut)0 : val);\ + }\ + output[dstOffset+3] = val;\ }\ }\ @@ -720,7 +765,7 @@ BINARY_FUNC_FLOATMID4(MOD, fmod(x, y)); BINARY_FUNC_FLOATMID4(LOGICALOR, (x || y) ? 1 : 0); template -void BinaryBlitTemplateFloat(T* output, const T* input, const T* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, int bytes, CUDARuntime* runtime, int opType) { +void BinaryBlitTemplateFloat(T* output, const T* input, const T* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, int bytes, CUDARuntime* runtime, int opType, int activationType) { int count = size[0] * size[1] * size[2]; int block_num = runtime->blocks_num(count); int threads_num = runtime->threads_num(); @@ -732,24 +777,25 @@ void BinaryBlitTemplateFloat(T* output, const T* input, const T* input1, const i threads_num = runtime->threads_num();\ if(bytes == 4) {\ BinaryMidLinear4_##TYPE<<>>((const T*)input, (const T*)(input1), (TOut*)output,\ - count/4);\ + count/4, activationType);\ } else {\ BinaryMidLinearHalf4_##TYPE<<>>((const T*)input, (const T*)(input1), (TOut*)output,\ - count/4);\ + count/4, activationType);\ }\ } else {\ BinaryMidLinear##TYPE<<>>((const T*)input, (const T*)(input1), (TOut*)output,\ size[2],\ srcStride[2],\ srcStride1[2],\ - dstStride[2]);\ + dstStride[2],\ + activationType);\ }\ } else {\ BinaryMid##TYPE<<>>((const T*)input, (const T*)(input1), (TOut*)output,\ size[0], size[1], size[2],\ srcStride[0], srcStride[1], srcStride[2],\ srcStride1[0], srcStride1[1], srcStride1[2],\ - dstStride[0], dstStride[1], dstStride[2]);\ + dstStride[0], dstStride[1], dstStride[2], activationType);\ }\ return;\ }\ @@ -777,7 +823,7 @@ void BinaryBlitTemplateFloat(T* output, const T* input, const T* input1, const i #undef COMPUTE_FLOAT } -void BinaryBlitTemplateInt32(uint8_t* output, const uint8_t* input, const uint8_t* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, int bytes, CUDARuntime* runtime, int opType) { +void BinaryBlitTemplateInt32(uint8_t* output, const uint8_t* input, const uint8_t* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, int bytes, CUDARuntime* runtime, int opType, int activationType) { int count = size[0] * size[1] * size[2]; int block_num = runtime->blocks_num(count); int threads_num = runtime->threads_num(); @@ -787,7 +833,7 @@ void BinaryBlitTemplateInt32(uint8_t* output, const uint8_t* input, const uint8_ size[0], size[1], size[2],\ srcStride[0], srcStride[1], srcStride[2],\ srcStride1[0], srcStride1[1], srcStride1[2],\ - dstStride[0], dstStride[1], dstStride[2]);\ + dstStride[0], dstStride[1], dstStride[2], activationType);\ return;\ }\ @@ -809,15 +855,15 @@ void BinaryBlitTemplateInt32(uint8_t* output, const uint8_t* input, const uint8_ } -void BinaryBlit(uint8_t* output, const uint8_t* input, const uint8_t* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, halide_type_t type, CUDARuntime* runtime, int opType) { +void BinaryBlit(uint8_t* output, const uint8_t* input, const uint8_t* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, halide_type_t type, CUDARuntime* runtime, int opType, int activationType) { if (type.code == halide_type_float) { if (type.bits == 32) { - BinaryBlitTemplateFloat((float*)output, (float*)input, (float*)input1, size, srcStride, srcStride1, dstStride, type.bytes(), runtime, opType); + BinaryBlitTemplateFloat((float*)output, (float*)input, (float*)input1, size, srcStride, srcStride1, dstStride, type.bytes(), runtime, opType, activationType); } else if (type.bits == 16) { - BinaryBlitTemplateFloat((half*)output, (half*)input, (half*)input1, size, srcStride, srcStride1, dstStride, type.bytes(), runtime, opType); + BinaryBlitTemplateFloat((half*)output, (half*)input, (half*)input1, size, srcStride, srcStride1, dstStride, type.bytes(), runtime, opType, activationType); } } else if (type.code == halide_type_int) { - BinaryBlitTemplateInt32(output, input, input1, size, srcStride, srcStride1, dstStride, type.bytes(), runtime, opType); + BinaryBlitTemplateInt32(output, input, input1, size, srcStride, srcStride1, dstStride, type.bytes(), runtime, opType, activationType); } } diff --git a/source/backend/cuda/execution/Raster.cuh b/source/backend/cuda/execution/Raster.cuh index 34e171e39..cd28a5058 100644 --- a/source/backend/cuda/execution/Raster.cuh +++ b/source/backend/cuda/execution/Raster.cuh @@ -8,7 +8,7 @@ namespace CUDA { void FuseRasterBlit(uint8_t* output, const uint8_t* input, const int32_t* size, const int32_t* srcStride, const int32_t* dstStride, int fuseNum, void* sliceOffset, int bytes, CUDARuntime* runtime, int offsetunit); void BlitWithIndice(uint8_t* dest, const uint8_t* src, const int32_t* dstIndices, const int32_t* srcIndices, int dstUseIndice, int srcUseIndice, int loopCount, int dstStep, int srcStep, int srcLimit, const Tensor::InsideDescribe::Region& reg, int bytes, CUDARuntime* runtime); void UnaryBlit(uint8_t* output, const uint8_t* input, const int32_t* size, const int32_t* srcStride, const int32_t* dstStride, int bytes, CUDARuntime* runtime, int opType); - void BinaryBlit(uint8_t* output, const uint8_t* input, const uint8_t* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, halide_type_t type, CUDARuntime* runtime, int opType); + void BinaryBlit(uint8_t* output, const uint8_t* input, const uint8_t* input1, const int32_t* size, const int32_t* srcStride, const int32_t* srcStride1, const int32_t* dstStride, halide_type_t type, CUDARuntime* runtime, int opType, int activationType = 0); // Offset: 8 * fuseNum, first 4 for src: limitX, limitY, limitZ, offset, second 4 for dst struct FuseRegion { diff --git a/source/backend/cuda/execution/RasterExecution.cpp b/source/backend/cuda/execution/RasterExecution.cpp index 6878b0b21..8c3fac050 100644 --- a/source/backend/cuda/execution/RasterExecution.cpp +++ b/source/backend/cuda/execution/RasterExecution.cpp @@ -145,6 +145,59 @@ static int _singleConvert(const Tensor::InsideDescribe::Region& region, const Te return 1; } +static bool _equalSizeStride(const Tensor::InsideDescribe::Region& slice0, const Tensor::InsideDescribe::Region& slice1) { + if (slice0.src.stride[0] != slice1.src.stride[0] || slice0.dst.stride[0] != slice1.dst.stride[0]) { + //MNN_PRINT("Raster total:%d, index:%d, src stride0:%d-%d, , dst stride0:%d-%d\n", mTempInputCopy.size(), i, slice.src.stride[0], slice0.src.stride[0], slice.dst.stride[0], slice0.dst.stride[0]); + return false; + } + if (slice0.src.stride[1] != slice1.src.stride[1] || slice0.dst.stride[1] != slice1.dst.stride[1]) { + //MNN_PRINT("Raster total:%d, index:%d, src stride1:%d-%d, , dst stride1:%d-%d\n", mTempInputCopy.size(), i, slice.src.stride[1], slice0.src.stride[1], slice.dst.stride[1], slice0.dst.stride[1]); + return false; + } + if (slice0.src.stride[2] != slice1.src.stride[2] || slice0.dst.stride[2] != slice1.dst.stride[2]) { + //MNN_PRINT("Raster total:%d, index:%d, src stride2:%d-%d, , dst stride2:%d-%d\n", mTempInputCopy.size(), i, slice.src.stride[2], slice0.src.stride[2], slice.dst.stride[2], slice0.dst.stride[2]); + return false; + } + if (slice0.size[0] != slice1.size[0] || slice0.size[1] != slice1.size[1] || slice0.size[2] != slice1.size[2]) { + //MNN_PRINT("Raster total:%d, index:%d, copy size:%d-%d-%d, %d-%d-%d\n", mTempInputCopy.size(), i, slice.size[0], slice.size[1], slice.size[2], slice0.size[0], slice0.size[1], slice0.size[2]); + return false; + } + return true; +} + +static bool _directBlitC4(const Tensor::InsideDescribe::Region& slice0, const Tensor::InsideDescribe::Region& slice1) { + if(slice0.size[1] % PACK_NUMBER != 0 || slice0.size[0] != 1) { + return false; + } + if(slice1.size[1] % PACK_NUMBER != 0 || slice1.size[0] != 1) { + return false; + } + if(slice0.dst.offset % (slice0.size[1] * slice0.size[0]) != 0) { + return false; + } + if(slice1.dst.offset % (slice1.size[1] * slice1.size[0]) != 0) { + return false; + } + return _equalSizeStride(slice0, slice1); +} + +static void _turnToNewRegion(const Tensor::InsideDescribe::Region& region, Tensor::InsideDescribe::Region& newRegion, int multiStride) { + newRegion.size[0] = region.size[0]; + newRegion.size[1] = region.size[2]; + newRegion.size[2] = region.size[1]; + + newRegion.src.stride[0] = region.src.stride[0]; + newRegion.src.stride[1] = region.src.stride[2] * region.size[1]; + newRegion.src.stride[2] = region.src.stride[1] / region.size[2]; + + newRegion.dst.stride[0] = region.dst.stride[0] * multiStride; + newRegion.dst.stride[1] = region.dst.stride[2] * region.size[1] * multiStride; + newRegion.dst.stride[2] = region.dst.stride[1] / region.size[2]; + + newRegion.src.offset = region.src.offset / region.size[2]; + newRegion.dst.offset = region.dst.offset / region.size[2]; +} + ErrorCode RasterExecution::onResize(const std::vector &inputs, const std::vector &outputs) { MNN_ASSERT(inputs.size() == 1); MNN_ASSERT(outputs.size() == 1); @@ -157,7 +210,52 @@ ErrorCode RasterExecution::onResize(const std::vector &inputs, const s mTempInput.clear(); mTempOutput = nullptr; - mOutputPtr = output; + mOutputPtr = output; + + mFast = false; + int pack = PACK_NUMBER; + // all_srcFormat == dstFormat == NC4HW4 : Fast Exe + if (outputDes->dimensionFormat == MNN_DATA_FORMAT_NC4HW4) { + mFast = true; + auto& slice0 = des->regions[0]; + for (int i=0; i< des->regions.size(); ++i) { + auto& slice = des->regions[i]; + //MNN_PRINT("%d-%d-%d, %d-%d-%d-%d\n", slice.size[0], slice.size[1], slice.size[2], slice.src.stride[1], slice.src.stride[2], slice.dst.stride[1], slice.dst.stride[2]); + if (TensorUtils::getDescribe(slice.origin)->dimensionFormat != MNN_DATA_FORMAT_NC4HW4) { + mFast = false; + break; + } + if(!_directBlitC4(slice0, slice)) { + mFast = false; + break; + } + if (!OpCommonUtils::canBlitFast(slice, output, pack, false, true)) { + mFast = false; + break; + } + } + //MNN_PRINT("raster fast:%d\n", mFast); + if (mFast) { + int multiStride = 1; + for (int i=0; i< des->regions.size(); ++i) { + auto& slice = des->regions[i]; + if(slice.dst.offset / (slice.size[0] * slice.size[1]) >= 1) { + int batchChannel = slice.dst.offset / (slice.size[1] * slice.size[2]) + 1; + multiStride = multiStride > batchChannel ? multiStride : batchChannel; + } + } + for (int i=0; i< des->regions.size(); ++i) { + auto& slice = des->regions[i]; + if (slice.origin == nullptr) { + continue; + } + Tensor::InsideDescribe::Region newRegion; + _turnToNewRegion(slice, newRegion, multiStride); + mFastBlit.emplace_back(std::make_pair(slice.origin, std::move(newRegion))); + } + return NO_ERROR; + } + } mSingleConvert = 0; // srcNum == 1 && srcFormat != dstFormat : Single Convert @@ -228,25 +326,8 @@ ErrorCode RasterExecution::onResize(const std::vector &inputs, const s //MNN_PRINT("Raster total:%d, index:%d, origin:%p-%p\n", mTempInputCopy.size(), i, mTempInputCopy[i].first, mTempInputCopy[0].first); break; } - if (slice0.src.stride[0] != slice.src.stride[0] || slice0.dst.stride[0] != slice.dst.stride[0]) { - //MNN_PRINT("Raster total:%d, index:%d, src stride0:%d-%d, , dst stride0:%d-%d\n", mTempInputCopy.size(), i, slice.src.stride[0], slice0.src.stride[0], slice.dst.stride[0], slice0.dst.stride[0]); + if(!_equalSizeStride(slice0, slice)) { mFuseRaster.first = 0; - break; - } - if (slice0.src.stride[1] != slice.src.stride[1] || slice0.dst.stride[1] != slice.dst.stride[1]) { - //MNN_PRINT("Raster total:%d, index:%d, src stride1:%d-%d, , dst stride1:%d-%d\n", mTempInputCopy.size(), i, slice.src.stride[1], slice0.src.stride[1], slice.dst.stride[1], slice0.dst.stride[1]); - mFuseRaster.first = 0; - break; - } - if (slice0.src.stride[2] != slice.src.stride[2] || slice0.dst.stride[2] != slice.dst.stride[2]) { - //MNN_PRINT("Raster total:%d, index:%d, src stride2:%d-%d, , dst stride2:%d-%d\n", mTempInputCopy.size(), i, slice.src.stride[2], slice0.src.stride[2], slice.dst.stride[2], slice0.dst.stride[2]); - mFuseRaster.first = 0; - break; - } - if (slice0.size[0] != slice.size[0] || slice0.size[1] != slice.size[1] || slice0.size[2] != slice.size[2]) { - //MNN_PRINT("Raster total:%d, index:%d, copy size:%d-%d-%d, %d-%d-%d\n", mTempInputCopy.size(), i, slice.size[0], slice.size[1], slice.size[2], slice0.size[0], slice0.size[1], slice0.size[2]); - mFuseRaster.first = 0; - break; } } } @@ -284,7 +365,29 @@ ErrorCode RasterExecution::onResize(const std::vector &inputs, const s return NO_ERROR; } +void RasterExecution::executeFaster(const std::vector &inputs, const std::vector &outputs) const { + auto bn = static_cast(backend()); + auto input = inputs[0]; + auto output = outputs[0]; + auto bytes = bn->getBytes(output); + auto runtime = static_cast(backend())->getCUDARuntime(); + if (mNeedZero) { + auto size = static_cast(backend())->realSize(output) * bytes; + cudaMemset((uint8_t*)output->deviceId(), 0, size); + } + // Use mFastBlit + for (auto& iter : mFastBlit) { + auto srcPtr = (uint8_t*)iter.first->deviceId() + iter.second.src.offset * bytes; + auto dstPtr = (uint8_t*)output->deviceId() + iter.second.dst.offset * bytes; + RasterBlit(dstPtr, srcPtr, iter.second.size, iter.second.src.stride, iter.second.dst.stride, bytes, runtime); + } +} + ErrorCode RasterExecution::onExecute(const std::vector &inputs, const std::vector &outputs) { + if (mFast) { + executeFaster(inputs, outputs); + return NO_ERROR; + } auto bn = static_cast(backend()); auto input = inputs[0]; auto output = outputs[0]; diff --git a/source/backend/cuda/execution/TensorCoreGemmPacked.cu b/source/backend/cuda/execution/TensorCoreGemmPacked.cu index 13d76d6ee..b8560b8be 100644 --- a/source/backend/cuda/execution/TensorCoreGemmPacked.cu +++ b/source/backend/cuda/execution/TensorCoreGemmPacked.cu @@ -27,7 +27,7 @@ __global__ void GemmPackedFull(const MatMulParam* param, const int iBlock, T *c, wmma::fragment b_frag; wmma::fragment acc_frag; - + for (size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += blockDim.x * gridDim.x) { size_t subIndex = index / warpSize; size_t warpM = subIndex % eU; @@ -39,9 +39,6 @@ __global__ void GemmPackedFull(const MatMulParam* param, const int iBlock, T *c, //printf("GemmPacked: %d - %d - %d, numele: %d, %d\n", eU, lU, hU, a_frag.num_elements, b_frag.num_elements); // MLA for (size_t i = 0; i < lU; ++i) { - half* aTemp = ((half *)(aStart+i*256));//aStart + (i << 8) + (laneId << 1); - half* bTemp = ((half *)(bStart+i*256));//bStart + (i << 8) + (laneId << 1); - wmma::load_matrix_sync(a_frag, aStart + i * 256, 16); wmma::load_matrix_sync(b_frag, bStart + i * 256, 16); wmma::mma_sync(acc_frag, a_frag, b_frag, acc_frag); @@ -99,7 +96,10 @@ __global__ void GemmPackedFull16x32(const MatMulParam* param, const int iBlock, size_t wrapId = threadIdx.x / warpSize; size_t laneId = threadIdx.x % warpSize; extern __shared__ float sharedMemory[]; - T* cache = (T*)(sharedMemory + wrapId * 16 * 32); + constexpr int row = 17; + constexpr int conflict_free_size = 24; + constexpr int offset = 16; + T* cache = (T*)(sharedMemory + wrapId * conflict_free_size * (16 + row)); for (size_t index = blockIdx.x * threadCount + wrapId; index < maxCount; index += gridDim.x * threadCount) { size_t warpM = index % eU; size_t warpN = index / eU; @@ -143,18 +143,18 @@ __global__ void GemmPackedFull16x32(const MatMulParam* param, const int iBlock, T* dst0 = (T*)(c + warpN * 32 * (size_t)param->elh[0] + eSta * 16); T* dst1 = (T*)(c + (warpN * 32 + 16) * (size_t)param->elh[0] + eSta * 16); // First 8x32 - wmma::store_matrix_sync(cache, MC0, 16, wmma::mem_row_major); + wmma::store_matrix_sync(cache, MC0, conflict_free_size, wmma::mem_row_major); // Second 8x32 - wmma::store_matrix_sync(cache + 256, MC1, 16, wmma::mem_row_major); + wmma::store_matrix_sync(cache + 16 * conflict_free_size + offset, MC1, conflict_free_size, wmma::mem_row_major); auto dst = dst0; auto src = cache; if (laneId >= 16) { dst = dst1; - src = cache + 256; + src = cache + 16 * conflict_free_size + offset; } size_t x = laneId % 16; for (size_t y = 0; y < eC; ++y) { - dst[y * 16 + x] = src[y * 16 + x]; + dst[y * 16 + x] = src[y * conflict_free_size + x]; } } } @@ -169,7 +169,10 @@ __global__ void GemmPackedFull32x16(const MatMulParam* param, const int iBlock, size_t wrapId = threadIdx.x / warpSize; size_t laneId = threadIdx.x % warpSize; extern __shared__ float sharedMemory[]; - T* cache = (T*)(sharedMemory + wrapId * 32 * 16); + constexpr int row = 17; + constexpr int conflict_free_size = 24; + constexpr int offset = 16; + T* cache = (T*)(sharedMemory + wrapId * (16 + row) * conflict_free_size); for (size_t index = blockIdx.x * threadCount + wrapId; index < maxCount; index += gridDim.x * threadCount) { size_t warpN = index % hU; size_t warpM = index / hU; @@ -216,18 +219,18 @@ __global__ void GemmPackedFull32x16(const MatMulParam* param, const int iBlock, T* dst0 = (T*)(c + warpN * 16 * (size_t)param->elh[0] + eSta * 16); T* dst1 = (T*)(dst0 + 256); // First 8x32 - wmma::store_matrix_sync(cache, MC0, 16, wmma::mem_row_major); + wmma::store_matrix_sync(cache, MC0, conflict_free_size, wmma::mem_row_major); // Second 8x32 - wmma::store_matrix_sync(cache + 256, MC1, 16, wmma::mem_row_major); + wmma::store_matrix_sync(cache + 16 * conflict_free_size + offset, MC1, conflict_free_size, wmma::mem_row_major); auto dst = dst0; auto src = cache; if (laneId >= 16) { dst = dst1; - src = cache + 256; + src = cache + 16 * conflict_free_size + offset; } size_t x = laneId % 16; for (size_t y = 0; y < eC; ++y) { - dst[y * 16 + x] = src[y * 16 + x]; + dst[y * 16 + x] = src[y * conflict_free_size + x]; } } } @@ -261,10 +264,14 @@ void GemmPacked16x32(CUDARuntime* runtime, const MatMulParam* cpuParam, const Ma { int hUP = cpuParam->elhPack[2]; int maxThreadInWarp = UP_DIV(cpuParam->elhPack[0] * hUP, cores); - int threads_num = ALIMIN(512, maxThreadInWarp * prop.warpSize); + constexpr int max_threadblock = 512; + int threads_num = ALIMIN(max_threadblock, maxThreadInWarp * prop.warpSize); //MNN_PRINT("GemmPacked16x32：%d-%d-%d-%d-%d\n\n", hUP, cpuParam->elhPack[0], cpuParam->elhPack[2], cpuParam->elhPack[0]*cpuParam->elhPack[2], threads_num); threads_num = ALIMIN(prop.maxThreadsPerBlock, threads_num); - int basicMemory = 32 * 16 * sizeof(float) * (threads_num / prop.warpSize); + constexpr int row = 17; + constexpr int conflict_free_size = 24; + int basicMemory = (16 + row) * conflict_free_size * sizeof(float) * (threads_num / prop.warpSize); + // MNN_PRINT("GemmPacked16x32 basicMemory byte size:%d\n", basicMemory); if (4 == bytes) { cudaFuncSetAttribute(GemmPackedFull16x32, cudaFuncAttributeMaxDynamicSharedMemorySize, basicMemory); GemmPackedFull16x32<<>>(param, iBlock, (float*)c, a, b, (float*)biasPtr); @@ -284,10 +291,13 @@ void GemmPacked32x16(CUDARuntime* runtime, const MatMulParam* cpuParam, const Ma { int eUP = cpuParam->elhPack[0]; int maxThreadInWarp = UP_DIV(eUP * cpuParam->elhPack[2], cores); - int threads_num = ALIMIN(512, maxThreadInWarp * prop.warpSize); + constexpr int max_threadblock = 512; + int threads_num = ALIMIN(max_threadblock, maxThreadInWarp * prop.warpSize); //MNN_PRINT("GemmPacked32x16：%d-%d-%d-%d-%d\n\n", eUP, cpuParam->elhPack[0], cpuParam->elhPack[2], cpuParam->elhPack[0]*cpuParam->elhPack[2], threads_num); threads_num = ALIMIN(prop.maxThreadsPerBlock, threads_num); - int basicMemory = 32 * 16 * sizeof(float) * (threads_num / prop.warpSize); + constexpr int row = 17; + constexpr int conflict_free_size = 24; + int basicMemory = (16 + row) * conflict_free_size * sizeof(float) * (threads_num / prop.warpSize); if (4 == bytes) { cudaFuncSetAttribute(GemmPackedFull32x16, cudaFuncAttributeMaxDynamicSharedMemorySize, basicMemory); GemmPackedFull32x16<<>>(param, iBlock, (float*)c, a, b, (float*)biasPtr); diff --git a/source/backend/cuda/execution/Transpose.cu b/source/backend/cuda/execution/Transpose.cu index 09bcd2575..37da60805 100644 --- a/source/backend/cuda/execution/Transpose.cu +++ b/source/backend/cuda/execution/Transpose.cu @@ -292,19 +292,65 @@ __global__ void NCHW_2_NHWC8(const T0* input, const int maxCount, const int channel, const int area, - const int channel_pack + const int channel_pack, + DivModFast d_ocp, + DivModFast d_area ) { for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += blockDim.x * gridDim.x) { - int chnlp_idx = index % channel_pack; - int temp = index / channel_pack; - int area_idx = temp % area; - int batch_idx = temp / area; + int area_idx, temp, chnlp_idx, batch_idx; + d_ocp.divmod(index, temp, chnlp_idx); + d_area.divmod(temp, batch_idx, area_idx); if(chnlp_idx >= channel) { output[index] = (T1)0.0f; continue; } - output[index] = (T1)input[(batch_idx * channel + chnlp_idx) * area + area_idx]; + int src_offset = (batch_idx * channel + chnlp_idx) * area + area_idx; + output[index] = (T1)input[src_offset]; + } +} + +template +__global__ void NCHW_2_NHWC(const T0* input, + T1* output, + const int maxCount, + const int channel, + const int area, + const int channel_pack, + DivModFast d_oc, + DivModFast d_area +) { + for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += blockDim.x * gridDim.x) { + int area_idx, temp, chnl_idx, batch_idx; + d_oc.divmod(index, temp, chnl_idx); + d_area.divmod(temp, batch_idx, area_idx); + + int src_offset = (batch_idx * channel + chnl_idx) * area + area_idx; + output[index] = (T1)input[src_offset]; + } +} + +template +__global__ void NHWC_2_NHWC8(const T0* input, + T1* output, + const int maxCount, + const int channel, + const int area, + const int channel_pack, + DivModFast d_ocp, + DivModFast d_area +) { + for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += blockDim.x * gridDim.x) { + int area_idx, temp, chnlp_idx, batch_idx; + d_ocp.divmod(index, temp, chnlp_idx); + d_area.divmod(temp, batch_idx, area_idx); + + if(chnlp_idx >= channel) { + output[index] = (T1)0.0f; + continue; + } + int src_offset = (batch_idx * area + area_idx) * channel + chnlp_idx; + output[index] = (T1)input[src_offset]; } } @@ -314,17 +360,40 @@ __global__ void NHWC8_2_NCHW(const T0* input, const int maxCount, const int channel, const int area, - const int channel_pack + const int channel_pack, + DivModFast d_oc, + DivModFast d_area ) { for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += blockDim.x * gridDim.x) { - int area_idx = index % area; - int temp = index / area; - int channel_idx = temp % channel; - int batch_idx = temp / channel; - output[index] = (T1)input[(batch_idx * area + area_idx) * channel_pack + channel_idx]; + int area_idx, temp, channel_idx, batch_idx; + d_area.divmod(index, temp, area_idx); + d_oc.divmod(temp, batch_idx, channel_idx); + + int src_offset = (batch_idx * area + area_idx) * channel_pack + channel_idx; + output[index] = (T1)input[src_offset]; } +} +template +__global__ void NHWC8_2_NHWC(const T0* input, + T1* output, + const int maxCount, + const int channel, + const int area, + const int channel_pack, + DivModFast d_oc, + DivModFast d_area +) { + for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += blockDim.x * gridDim.x) { + + int area_idx, temp, channel_idx, batch_idx; + d_oc.divmod(index, temp, channel_idx); + d_area.divmod(temp, batch_idx, area_idx); + + int src_offset = (batch_idx * area + area_idx) * channel_pack + channel_idx; + output[index] = (T1)input[src_offset]; + } } template @@ -383,11 +452,25 @@ __global__ void NHWC8_2_C4NHW4(const T0* input, template static void insideFormatConvert(T0* input, T1* output, MNN_DATA_FORMAT srcDataFormat, MNN_DATA_FORMAT dstDataFormat, CUDARuntime* runtime, \ const int area, const int batch, const int channel) { + DivModFast d_oc(channel); + DivModFast d_ocp(UP_DIV(channel, 8) * 8); + DivModFast d_area(area); + if(srcDataFormat == MNN_DATA_FORMAT_NCHW && dstDataFormat == MNN_DATA_FORMAT_NC4HW4) { const int maxCount = batch * area * UP_DIV(channel, 8) * 8; const int block_num = runtime->blocks_num(maxCount); const int block_size = runtime->threads_num(); - NCHW_2_NHWC8<<>>(input, output, maxCount, channel, area, UP_DIV(channel, 8) * 8); + NCHW_2_NHWC8<<>>(input, output, maxCount, channel, area, UP_DIV(channel, 8) * 8, + d_ocp, d_area); + checkKernelErrors; + return; + } + if(srcDataFormat == MNN_DATA_FORMAT_NHWC && dstDataFormat == MNN_DATA_FORMAT_NC4HW4) { + const int maxCount = batch * area * UP_DIV(channel, 8) * 8; + const int block_num = runtime->blocks_num(maxCount); + const int block_size = runtime->threads_num(); + NHWC_2_NHWC8<<>>(input, output, maxCount, channel, area, UP_DIV(channel, 8) * 8, + d_ocp, d_area); checkKernelErrors; return; } @@ -404,7 +487,26 @@ static void insideFormatConvert(T0* input, T1* output, MNN_DATA_FORMAT srcDataFo const int maxCount = batch * area * channel; const int block_num = runtime->blocks_num(maxCount); const int block_size = runtime->threads_num(); - NHWC8_2_NCHW<<>>(input, output, maxCount, channel, area, UP_DIV(channel, 8) * 8); + NHWC8_2_NCHW<<>>(input, output, maxCount, channel, area, UP_DIV(channel, 8) * 8, + d_oc, d_area); + checkKernelErrors; + return; + } + if(srcDataFormat == MNN_DATA_FORMAT_NC4HW4 && dstDataFormat == MNN_DATA_FORMAT_NHWC) { + const int maxCount = batch * area * channel; + const int block_num = runtime->blocks_num(maxCount); + const int block_size = runtime->threads_num(); + NHWC8_2_NHWC<<>>(input, output, maxCount, channel, area, UP_DIV(channel, 8) * 8, + d_oc, d_area); + checkKernelErrors; + return; + } + if(srcDataFormat == MNN_DATA_FORMAT_NCHW && dstDataFormat == MNN_DATA_FORMAT_NHWC) { + const int maxCount = batch * area * channel; + const int block_num = runtime->blocks_num(maxCount); + const int block_size = runtime->threads_num(); + NCHW_2_NHWC<<>>(input, output, maxCount, channel, area, UP_DIV(channel, 8) * 8, + d_oc, d_area); checkKernelErrors; return; } diff --git a/source/backend/cuda/execution/WinogradTrans.cuh b/source/backend/cuda/execution/WinogradTrans.cuh index a7cfb72e2..d6ec20ff2 100644 --- a/source/backend/cuda/execution/WinogradTrans.cuh +++ b/source/backend/cuda/execution/WinogradTrans.cuh @@ -16,45 +16,29 @@ __global__ void WinoInputTrans(const T* input, const int unit, const int block, const int ci, - const int ciDiv, - const int batch, - const int wLen, - const int hLen, - const int ePack, - const int lPack, + const int ci_p8, + const int maxCount, + DivModFast lD, + DivModFast whD, + DivModFast wD, const int pad_x, const int pad_y, const int width, const int height ) { - const int eU = (batch * wLen * hLen + 15) / 16; - const int lU = ciDiv; - const int eP = eU * ePack; - const int lP = lU * lPack; - const int maxCount = eP * lP; + const int l = ci_p8; for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += gridDim.x * blockDim.x) { - const int eU_idx = index / (lP * ePack); - const int tmp1 = index % (lP * ePack); - const int lU_idx = tmp1 / (ePack * lPack); - const int tmp2 = tmp1 % (ePack * lPack); - const int ePack_idx = tmp2 / lPack; - const int lPack_idx = tmp2 % lPack; - - const int e_idx = eU_idx * ePack + ePack_idx; - const int batch_idx = e_idx / (wLen * hLen); - const int tmp3 = e_idx % (wLen * hLen); - const int w_idx = tmp3 % wLen; - const int h_idx = tmp3 / wLen; + int e_idx, ci_idx, batch_idx, tmp, w_idx, h_idx; + lD.divmod(index, e_idx, ci_idx); + whD.divmod(e_idx, batch_idx, tmp); + wD.divmod(tmp, h_idx, w_idx); const int sxStart = w_idx * unit - pad_x; const int syStart = h_idx * unit - pad_y; T S00, S10, S20, S30, S01, S11, S21, S31, S02, S12, S22, S32, S03, S13, S23, S33; - int ci_p8 = ((ci + 7) / 8) * 8; - int ci_idx = lU_idx * lPack + lPack_idx; int inp_offset = ((batch_idx * height + syStart) * width + sxStart) * ci_p8 + ci_idx; - //(((lU_idx * batch + batch_idx) * height + syStart) * width + sxStart) * 16 + lPack_idx; { int sx = 0 + sxStart; int sy = 0 + syStart; @@ -74,14 +58,14 @@ __global__ void WinoInputTrans(const T* input, int sy = 0 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S20 = outBound ? (T)(0) : input[inp_offset+2*ci_p8]; + S20 = outBound ? (T)(0) : input[inp_offset+ci_p8+ci_p8]; } { int sx = 3 + sxStart; int sy = 0 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S30 = outBound ? (T)(0) : input[inp_offset+3*ci_p8]; + S30 = outBound ? (T)(0) : input[inp_offset+ci_p8+ci_p8+ci_p8]; } { int sx = 0 + sxStart; @@ -116,85 +100,85 @@ __global__ void WinoInputTrans(const T* input, int sy = 2 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S02 = outBound ? (T)(0) : input[inp_offset+(2*width+0)*ci_p8]; + S02 = outBound ? (T)(0) : input[inp_offset+(width+width+0)*ci_p8]; } { int sx = 1 + sxStart; int sy = 2 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S12 = outBound ? (T)(0) : input[inp_offset+(2*width+1)*ci_p8]; + S12 = outBound ? (T)(0) : input[inp_offset+(width+width+1)*ci_p8]; } { int sx = 2 + sxStart; int sy = 2 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S22 = outBound ? (T)(0) : input[inp_offset+(2*width+2)*ci_p8]; + S22 = outBound ? (T)(0) : input[inp_offset+(width+width+2)*ci_p8]; } { int sx = 3 + sxStart; int sy = 2 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S32 = outBound ? (T)(0) : input[inp_offset+(2*width+3)*ci_p8]; + S32 = outBound ? (T)(0) : input[inp_offset+(width+width+3)*ci_p8]; } { int sx = 0 + sxStart; int sy = 3 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S03 = outBound ? (T)(0) : input[inp_offset+(3*width+0)*ci_p8]; + S03 = outBound ? (T)(0) : input[inp_offset+(width+width+width+0)*ci_p8]; } { int sx = 1 + sxStart; int sy = 3 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S13 = outBound ? (T)(0) : input[inp_offset+(3*width+1)*ci_p8]; + S13 = outBound ? (T)(0) : input[inp_offset+(width+width+width+1)*ci_p8]; } { int sx = 2 + sxStart; int sy = 3 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S23 = outBound ? (T)(0) : input[inp_offset+(3*width+2)*ci_p8]; + S23 = outBound ? (T)(0) : input[inp_offset+(width+width+width+2)*ci_p8]; } { int sx = 3 + sxStart; int sy = 3 + syStart; bool outBound = (sx < 0 || sx >= width || sy < 0 || sy >= height || ci_idx >= ci); - S33 = outBound ? (T)(0) : input[inp_offset+(3*width+3)*ci_p8]; + S33 = outBound ? (T)(0) : input[inp_offset+(width+width+width+3)*ci_p8]; } T m00 = +S00 - S02; T m10 = +S10 - S12; T m20 = +S20 - S22; T m30 = +S30 - S32; - T m01 = +(T)0.5f * S01 + (T)0.5f * S02; - T m11 = +(T)0.5f * S11 + (T)0.5f * S12; - T m21 = +(T)0.5f * S21 + (T)0.5f * S22; - T m31 = +(T)0.5f * S31 + (T)0.5f * S32; - T m02 = -(T)0.5f * S01 + (T)0.5f * S02; - T m12 = -(T)0.5f * S11 + (T)0.5f * S12; - T m22 = -(T)0.5f * S21 + (T)0.5f * S22; - T m32 = -(T)0.5f * S31 + (T)0.5f * S32; + T m01 = +(T)0.5f * (S01 + S02); + T m11 = +(T)0.5f * (S11 + S12); + T m21 = +(T)0.5f * (S21 + S22); + T m31 = +(T)0.5f * (S31 + S32); + T m02 = +(T)0.5f * (-S01 + S02); + T m12 = +(T)0.5f * (-S11 + S12); + T m22 = +(T)0.5f * (-S21 + S22); + T m32 = +(T)0.5f * (-S31 + S32); T m03 = -S01 + S03; T m13 = -S11 + S13; T m23 = -S21 + S23; T m33 = -S31 + S33; BtdB[0*maxCount + index] = +m00 - m20; - BtdB[1*maxCount + index] = +(T)0.5f * m10 + (T)0.5f * m20; - BtdB[2*maxCount + index] = -(T)0.5f * m10 + (T)0.5f * m20; + BtdB[1*maxCount + index] = +(T)0.5f * (m10 + m20); + BtdB[2*maxCount + index] = +(T)0.5f * (-m10 + m20); BtdB[3*maxCount + index] = -m10 + m30; BtdB[4*maxCount + index] = +m01 - m21; - BtdB[5*maxCount + index] = +(T)0.5f * m11 + (T)0.5f * m21; - BtdB[6*maxCount + index] = -(T)0.5f * m11 + (T)0.5f * m21; + BtdB[5*maxCount + index] = +(T)0.5f * (m11 + m21); + BtdB[6*maxCount + index] = +(T)0.5f * (-m11 + m21); BtdB[7*maxCount + index] = -m11 + m31; BtdB[8*maxCount + index] = +m02 - m22; - BtdB[9*maxCount + index] = +(T)0.5f * m12 + (T)0.5f * m22; - BtdB[10*maxCount + index] = -(T)0.5f * m12 + (T)0.5f * m22; + BtdB[9*maxCount + index] = +(T)0.5f * (m12 + m22); + BtdB[10*maxCount + index] = +(T)0.5f * (-m12 + m22); BtdB[11*maxCount + index] = -m12 + m32; BtdB[12*maxCount + index] = +m03 - m23; - BtdB[13*maxCount + index] = +(T)0.5f * m13 + (T)0.5f * m23; - BtdB[14*maxCount + index] = -(T)0.5f * m13 + (T)0.5f * m23; + BtdB[13*maxCount + index] = +(T)0.5f * (m13 + m23); + BtdB[14*maxCount + index] = +(T)0.5f * (-m13 + m23); BtdB[15*maxCount + index] = -m13 + m33; } } @@ -208,48 +192,38 @@ __global__ void WinoTrans2Output(const T* matmulData, const int unit, const int block, const int co, - const int ciDiv, - const int batch, - const int wLen, - const int hLen, - const int ePack, - const int hPack, + const int co_p8, + const int maxCount, + DivModFast hD, + DivModFast whD, + DivModFast wD, const int width, const int height ) { - size_t e = param->elh[0]; - size_t hU = param->elhPack[2]; - const size_t maxCount = e * hU * hPack; - + const int h = co_p8; for(size_t index = blockIdx.x * blockDim.x + threadIdx.x; index < maxCount; index += gridDim.x * blockDim.x) { - const int hU_idx = index / (e * hPack); - const int tmp1 = index % (e * hPack); - const int e_idx = tmp1 / hPack; - const int hPack_idx = tmp1 % hPack; + int e_idx, co_idx, batch_idx, tmp, w_idx, h_idx; + hD.divmod(index, e_idx, co_idx); + whD.divmod(e_idx, batch_idx, tmp); + wD.divmod(tmp, h_idx, w_idx); - const int batch_idx = e_idx / (wLen * hLen); - const int tmp3 = e_idx % (wLen * hLen); - const int w_idx = tmp3 % wLen; - const int h_idx = tmp3 / wLen; - int basic_offset = (hU_idx * e + e_idx) * hPack + hPack_idx; - - auto S00 = matmulData[basic_offset]; - auto S10 = matmulData[basic_offset + maxCount]; - auto S20 = matmulData[basic_offset + maxCount * 2]; - auto S30 = matmulData[basic_offset + maxCount * 3]; - auto S01 = matmulData[basic_offset + maxCount * 4]; - auto S11 = matmulData[basic_offset + maxCount * 5]; - auto S21 = matmulData[basic_offset + maxCount * 6]; - auto S31 = matmulData[basic_offset + maxCount * 7]; - auto S02 = matmulData[basic_offset + maxCount * 8]; - auto S12 = matmulData[basic_offset + maxCount * 9]; - auto S22 = matmulData[basic_offset + maxCount * 10]; - auto S32 = matmulData[basic_offset + maxCount * 11]; - auto S03 = matmulData[basic_offset + maxCount * 12]; - auto S13 = matmulData[basic_offset + maxCount * 13]; - auto S23 = matmulData[basic_offset + maxCount * 14]; - auto S33 = matmulData[basic_offset + maxCount * 15]; + auto S00 = matmulData[index]; + auto S10 = matmulData[index + maxCount]; + auto S20 = matmulData[index + maxCount * 2]; + auto S30 = matmulData[index + maxCount * 3]; + auto S01 = matmulData[index + maxCount * 4]; + auto S11 = matmulData[index + maxCount * 5]; + auto S21 = matmulData[index + maxCount * 6]; + auto S31 = matmulData[index + maxCount * 7]; + auto S02 = matmulData[index + maxCount * 8]; + auto S12 = matmulData[index + maxCount * 9]; + auto S22 = matmulData[index + maxCount * 10]; + auto S32 = matmulData[index + maxCount * 11]; + auto S03 = matmulData[index + maxCount * 12]; + auto S13 = matmulData[index + maxCount * 13]; + auto S23 = matmulData[index + maxCount * 14]; + auto S33 = matmulData[index + maxCount * 15]; auto m00 = +S00 + S01 + S02; auto m10 = +S10 + S11 + S12; @@ -261,18 +235,15 @@ __global__ void WinoTrans2Output(const T* matmulData, auto m31 = +S31 - S32 + S33; // write output - float bias = biasData[hU_idx * hPack + hPack_idx]; + float bias = biasData[co_idx]; const int dxStart = w_idx * unit; const int dyStart = h_idx * unit; - int co_p8 = ((co + 7) / 8) * 8; - int co_idx = hU_idx * hPack + hPack_idx; if(co_idx >= co_p8) { continue; } int out_offset = ((batch_idx * height + dyStart) * width + dxStart) * co_p8 + co_idx; - //(((hU_idx * batch + batch_idx) * height + dyStart) * width + dxStart) * 16 + hPack_idx; /* if true */ { float res = bias + (float)(m00 + m10 + m20); diff --git a/source/backend/hiai/execution/NPUBinary.cpp b/source/backend/hiai/execution/NPUBinary.cpp index c247d8386..cc7a3a6ba 100644 --- a/source/backend/hiai/execution/NPUBinary.cpp +++ b/source/backend/hiai/execution/NPUBinary.cpp @@ -16,56 +16,129 @@ namespace MNN { void NPUBinary::OpInsert(int binary_type, string opName, ge::Operator& input0, ge::Operator& input1, - const std::vector &outputs){ + const std::vector &outputs, int activationType){ if(binary_type == BinaryOpOperation_ADD) { shared_ptr binary(new ge::op::Add(opName)); (*binary) .set_input_x1(input0) .set_input_x2(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } } else if(binary_type == BinaryOpOperation_MUL) { shared_ptr binary(new ge::op::Mul(opName)); (*binary) .set_input_x(input0) .set_input_y(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } } else if(binary_type == BinaryOpOperation_REALDIV) { shared_ptr binary(new ge::op::RealDiv(opName)); (*binary) .set_input_x1(input0) .set_input_x2(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } } else if(binary_type == BinaryOpOperation_SUB) { shared_ptr binary(new ge::op::Sub(opName)); (*binary) .set_input_x1(input0) .set_input_x2(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } } else if(binary_type == BinaryOpOperation_MINIMUM) { shared_ptr binary(new ge::op::Minimum(opName)); (*binary) .set_input_x1(input0) .set_input_x2(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } } else if(binary_type == BinaryOpOperation_MAXIMUM) { shared_ptr binary(new ge::op::Maximum(opName)); (*binary) .set_input_x1(input0) .set_input_x2(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } } else if(binary_type == BinaryOpOperation_EQUAL) { shared_ptr binary(new ge::op::Equal(opName)); (*binary) .set_input_x1(input0) .set_input_x2(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } } else if(binary_type == BinaryOpOperation_LESS_EQUAL) { shared_ptr binary(new hiai::op::LessEqual(opName)); (*binary) .set_input_x1(input0) .set_input_x2(input1); - mNpuBackend->setOutputOps(mOp, {binary}, outputs); + if(activationType == 1) { + shared_ptr binary_activation(new ge::op::Activation(opName + "_Relu")); + (*binary_activation) + .set_input_x(*binary.get()) + .set_attr_mode(1); + + mNpuBackend->setOutputOps(mOp, {binary, binary_activation}, outputs); + } else { + mNpuBackend->setOutputOps(mOp, {binary}, outputs); + } }else{ MNN_ERROR("npu binary not support type : %d \n", binary_type); MNN_ASSERT(false); @@ -149,21 +222,21 @@ ErrorCode NPUBinary::onResize(const std::vector &inputs, const std::ve vector, string>> ops; auto binary_type = mOp->main_as_BinaryOp()->opType(); - + int activationType = mOp->main_as_BinaryOp()->activationType(); if(!isConst0 && isConst1){ // auto inputIndex0 = mOp->inputIndexes()->data()[0]; auto iops0 = mNpuBackend->mGrapMap[inputIndex0]; // x auto xOp0 = iops0.back().first; - OpInsert(binary_type, opName, *xOp0.get(), mConst, outputs); + OpInsert(binary_type, opName, *xOp0.get(), mConst, outputs, activationType); }else if(isConst0 && !isConst1){ // auto inputIndex1 = mOp->inputIndexes()->data()[1]; auto iops1 = mNpuBackend->mGrapMap[inputIndex1]; // x auto xOp1 = iops1.back().first; - OpInsert(binary_type, opName, mConst, *xOp1.get(), outputs); + OpInsert(binary_type, opName, mConst, *xOp1.get(), outputs, activationType); }else{ @@ -177,7 +250,7 @@ ErrorCode NPUBinary::onResize(const std::vector &inputs, const std::ve auto iops1 = mNpuBackend->mGrapMap[inputIndex1]; // x auto xOp1 = iops1.back().first; - OpInsert(binary_type, opName, *xOp0.get(), *xOp1.get(), outputs); + OpInsert(binary_type, opName, *xOp0.get(), *xOp1.get(), outputs, activationType); } diff --git a/source/backend/hiai/execution/NPUBinary.hpp b/source/backend/hiai/execution/NPUBinary.hpp index a3144bdc4..20ed58cda 100644 --- a/source/backend/hiai/execution/NPUBinary.hpp +++ b/source/backend/hiai/execution/NPUBinary.hpp @@ -18,7 +18,7 @@ class NPUBinary : public NPUCommonExecution { public: void OpInsert(int binary_type, string opName, ge::Operator& input0, ge::Operator& input1, - const std::vector &outputs); + const std::vector &outputs, int activationType); NPUBinary(Backend *b, const Op *op, const std::vector &inputs, const std::vector &outputs); ErrorCode onResize(const std::vector &inputs, const std::vector &outputs); virtual ~NPUBinary() = default; diff --git a/source/backend/metal/AllShader.cpp b/source/backend/metal/AllShader.cpp index f569fdc8c..bf0b63166 100644 --- a/source/backend/metal/AllShader.cpp +++ b/source/backend/metal/AllShader.cpp @@ -2580,7 +2580,7 @@ const char* shader_MetalBinary_metal = " int i0stride;\n" " int i1stride;\n" " int output_data_count;\n" -" int output_width;\n" +" int activationType;\n" "};\n" "#define define_op(op) " "kernel void binary_##op##_x1(const device M *in0 [[buffer(0)]]," @@ -2591,7 +2591,11 @@ const char* shader_MetalBinary_metal = " if ((int)gid >= s.output_data_count) return;" " auto V0=in0[s.i0stride*int(gid)];" " auto V1=in1[s.i1stride*int(gid)];" -" out[int(gid)]=op(V0,V1);" +" auto val=op(V0,V1);" +" if(s.activationType == 1) {" +" val=(val<(M)0 ? (M)0 : val);" +" }" +" out[int(gid)]=val;" "}\n" "static inline M add(M V1,M V2) {\n" " return V1+V2;\n" diff --git a/source/backend/metal/MNNMetalContext.mm b/source/backend/metal/MNNMetalContext.mm index cc95b6170..d95c49561 100644 --- a/source/backend/metal/MNNMetalContext.mm +++ b/source/backend/metal/MNNMetalContext.mm @@ -56,6 +56,9 @@ static void createLibrary(id device, NSMutableDictionary device, NSMutableDictionary device = MTLCreateSystemDefaultDevice(); if (nil != device) { registerMetalOps(); - MNNInsertExtraRuntimeCreator(MNN_FORWARD_METAL, new MetalRuntimeCreator(device), false); + MNNInsertExtraRuntimeCreator(MNN_FORWARD_METAL, new MetalRuntimeCreator(device), true); } else { MNN_ERROR("Init Metal Error\n"); } diff --git a/source/backend/metal/MetalBinary.hpp b/source/backend/metal/MetalBinary.hpp index e6fca2b52..375c93b76 100644 --- a/source/backend/metal/MetalBinary.hpp +++ b/source/backend/metal/MetalBinary.hpp @@ -17,7 +17,7 @@ namespace MNN { class MetalBinary : public Execution { public: - MetalBinary(Backend *backend, std::string type); + MetalBinary(Backend *backend, std::string type, const MNN::Op *op); virtual ~MetalBinary() = default; virtual ErrorCode onExecute(const std::vector &inputs, const std::vector &outputs) override; virtual ErrorCode onResize(const std::vector &inputs, const std::vector &outputs) override; @@ -26,6 +26,7 @@ private: id mConstBuffer; id mPipeline; std::pair mThreads; + int mActivationType = 0; }; } // namespace MNN diff --git a/source/backend/metal/MetalBinary.mm b/source/backend/metal/MetalBinary.mm index bdf3867a8..d39f78a4e 100755 --- a/source/backend/metal/MetalBinary.mm +++ b/source/backend/metal/MetalBinary.mm @@ -14,13 +14,14 @@ #if MNN_METAL_ENABLED namespace MNN { -MetalBinary::MetalBinary(Backend *backend, std::string type) : Execution(backend) { +MetalBinary::MetalBinary(Backend *backend, std::string type, const MNN::Op *op) : Execution(backend) { auto mKernelName = "binary_" + type + "_x1"; auto mtbn = static_cast(backend); auto context = (__bridge MNNMetalContext *)mtbn->context(); mConstBuffer = [context newDeviceBuffer:4 * sizeof(int) access:CPUWriteOnly]; auto kn = [NSString stringWithCString:mKernelName.c_str() encoding:[NSString defaultCStringEncoding]]; mPipeline = [context pipelineWithName:kn]; + mActivationType = op->main_as_BinaryOp()->activationType(); } ErrorCode MetalBinary::onResize(const std::vector &inputs, const std::vector &outputs) { auto backend = static_cast(this->backend()); @@ -33,7 +34,7 @@ ErrorCode MetalBinary::onResize(const std::vector &inputs, const std:: ((int *)mConstBuffer.contents)[0] = input0_data_count == 1 ? 0 : 1; ((int *)mConstBuffer.contents)[1] = input1_data_count == 1 ? 0 : 1; ((int *)mConstBuffer.contents)[2] = outdatacount; - ((int *)mConstBuffer.contents)[3] = 0; + ((int *)mConstBuffer.contents)[3] = mActivationType; mThreads = [context computeBestGroupAndLocal:mPipeline threads:MTLSizeMake(outdatacount, 1, 1)]; return NO_ERROR; } @@ -94,7 +95,7 @@ public: FUNC_PRINT(binaryop->opType()); return nullptr; } - return new MetalBinary(backend, type); + return new MetalBinary(backend, type, op); } }; REGISTER_METAL_OP_CREATOR(MetalBinaryCreator, OpType_BinaryOp); diff --git a/source/backend/metal/shader/MetalBinary.metal b/source/backend/metal/shader/MetalBinary.metal index aa029251f..fbc15970a 100644 --- a/source/backend/metal/shader/MetalBinary.metal +++ b/source/backend/metal/shader/MetalBinary.metal @@ -2,7 +2,7 @@ struct binary_op_shape { int i0stride; int i1stride; int output_data_count; - int output_width; + int activationType; }; #define define_op(op) \ kernel void binary_##op##_x1(const device ftype *in0 [[buffer(0)]],\ @@ -13,7 +13,11 @@ kernel void binary_##op##_x1(const device ftype *in0 [[buffer(0)]],\ if ((int)gid >= s.output_data_count) return;\ auto value0 = in0[s.i0stride * int(gid)];\ auto value1 = in1[s.i1stride * int(gid)];\ - out[int(gid)] = op(value0, value1);\ + auto val = op(value0, value1);\ + if(s.activationType == 1) {\ + val = (val < (ftype)0 ? (ftype)0 : val);\ + }\ + out[int(gid)] = val;\ } static inline ftype add(ftype value1, ftype value2) { diff --git a/source/backend/nnapi/CMakeLists.txt b/source/backend/nnapi/CMakeLists.txt new file mode 100644 index 000000000..07e66fc42 --- /dev/null +++ b/source/backend/nnapi/CMakeLists.txt @@ -0,0 +1,20 @@ +# Android NN API +file(GLOB MNN_NNAPI_SRCS + ${CMAKE_CURRENT_LIST_DIR}/backend/*.cpp + ${CMAKE_CURRENT_LIST_DIR}/backend/*.hpp + ${CMAKE_CURRENT_LIST_DIR}/execution/*.cpp + ${CMAKE_CURRENT_LIST_DIR}/execution/*.hpp +) + +add_library( + MNN_NNAPI + STATIC + ${MNN_NNAPI_SRCS} +) + +target_compile_options(MNN_NNAPI PRIVATE -DMNN_NNAPI_ENABLED=1) + +target_include_directories(MNN_NNAPI PRIVATE + ${CMAKE_CURRENT_LIST_DIR}/backend + ${CMAKE_CURRENT_LIST_DIR}/execution +) \ No newline at end of file diff --git a/source/backend/nnapi/backend/NNAPIBackend.cpp b/source/backend/nnapi/backend/NNAPIBackend.cpp new file mode 100644 index 000000000..6c24027ae --- /dev/null +++ b/source/backend/nnapi/backend/NNAPIBackend.cpp @@ -0,0 +1,411 @@ +// +// NNAPIBackend.cpp +// MNN +// +// Created by MNN on 2021/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPIBackend.hpp" +#include "backend/cpu/CPUTensorConvert.hpp" +#include +#include +#include +#include +#include +// #define NNAPI_DEBUG +// #define USE_NCHW + +#define CHECK(func, ...) \ + do { \ + const auto _status = (func(__VA_ARGS__)); \ + if (_status != ANEURALNETWORKS_NO_ERROR) { \ + const auto ENUM_TO_STR = NNAPIEnumToString(_status); \ + MNN_PRINT("[NNAPI] Error: %s when call " #func " at line %d.\n", \ + ENUM_TO_STR.c_str(), __LINE__); \ + } \ + } while (0) + +namespace MNN { + void registerNNAPIOps(); + static inline std::map* getCreatorMap() { + static std::once_flag of; + static std::map* ret = nullptr; + std::call_once(of, [&]() { ret = new std::map; }); + return ret; + } + + std::string NNAPIEnumToString(int code) { + switch (code) { +#define ENUM_TO_STR(code) case ANEURALNETWORKS_##code: return #code + // ResultCode begin + ENUM_TO_STR(NO_ERROR); + ENUM_TO_STR(OUT_OF_MEMORY); + ENUM_TO_STR(INCOMPLETE); + ENUM_TO_STR(UNEXPECTED_NULL); + ENUM_TO_STR(BAD_DATA); + ENUM_TO_STR(OP_FAILED); + ENUM_TO_STR(BAD_STATE); + ENUM_TO_STR(UNMAPPABLE); + ENUM_TO_STR(OUTPUT_INSUFFICIENT_SIZE); + ENUM_TO_STR(UNAVAILABLE_DEVICE); + // ResultCode end + default: + return "UNKNOWN_ENUM"; +#undef ENUM_TO_STR + } + } + bool NNAPIBackend::addCreator(OpType t, Creator* c) { + auto map = getCreatorMap(); + if (map->find(t) != map->end()) { + MNN_PRINT("Error: %d type has be added\n", t); + return false; + } + map->insert(std::make_pair(t, c)); + return true; + } + + NNAPIBackend::NNAPIBackend(const NNAPIRuntime* runtime) : Backend(MNN_FORWARD_NN) { + mNPURuntime = runtime; + mPrecision = mNPURuntime->mPrecision; +#ifdef USE_NCHW + mNCHW = true; +#else + mNCHW = false; +#endif + MNN_PRINT("[NNAPI] DimensionFormat is %s\n", mNCHW ? "NCHW" : "NHWC"); + if (mNNAPIModel == nullptr) { + CHECK(ANeuralNetworksModel_create_27, &mNNAPIModel); + } + if (mNNAPIDevices.empty()) { + uint32_t numDevices = 0; + CHECK(ANeuralNetworks_getDeviceCount_29, &numDevices); + mNNAPIDevices.resize(numDevices); + MNN_PRINT("[NNAPI] numDevices = %d\n", numDevices); + for (int i = 0; i < numDevices; i++) { + CHECK(ANeuralNetworks_getDevice_29, i, &mNNAPIDevices[i].device); + CHECK(ANeuralNetworksDevice_getName_29, mNNAPIDevices[i].device, &mNNAPIDevices[i].name); + CHECK(ANeuralNetworksDevice_getType_29, mNNAPIDevices[i].device, &mNNAPIDevices[i].type); + MNN_PRINT("[NNAPI] device %d is : %s, %d\n", i, mNNAPIDevices[i].name, mNNAPIDevices[i].type); + } + } + } + + NNAPIBackend::~NNAPIBackend() { + ANeuralNetworksCompilation_free_27(mNNAPICompilation); + ANeuralNetworksModel_free_27(mNNAPIModel); + } + + Execution* NNAPIBackend::onCreate(const std::vector& inputs, const std::vector& outputs, const MNN::Op* op) { + auto map = getCreatorMap(); + auto iter = map->find(op->type()); + if (iter == map->end()) { + MNN_PRINT("[NNAPI] Don't support type %s.\n", MNN::EnumNameOpType(op->type())); + return nullptr; + } + auto exe = iter->second->onCreate(inputs, outputs, op, this); + if (nullptr == exe) { + MNN_PRINT("[NNAPI] The Creator Don't support type %s.\n", MNN::EnumNameOpType(op->type())); + return nullptr; + } + return exe; + } + + void NNAPIBackend::NNAPIBackend::onExecuteBegin() const { + } + + void NNAPIBackend::onExecuteEnd() const { + invokeModel(); + } + + Backend::MemObj* NNAPIBackend::onAcquire(const Tensor* tensor, StorageType storageType) { + bool isInputCopy = TensorUtils::getDescribe(tensor)->usage==Tensor::InsideDescribe::Usage::INPUT; + bool isOutputCopy = TensorUtils::getDescribe(tensor)->usage==Tensor::InsideDescribe::Usage::OUTPUT; + std::unique_ptr tensor_(new Tensor(tensor, mNCHW ? Tensor::DimensionType::CAFFE : Tensor::DimensionType::TENSORFLOW, true)); + if(isInputCopy){ + mInputTensors.push_back(tensor); + mInputContentTensors.push_back(std::move(tensor_)); + mInputIdxMap.insert(std::make_pair(tensor, mInputIdxMap.size())); + } + if(isOutputCopy){ + mOutputTensors.push_back(tensor); + mOutputContentTensors.push_back(std::move(tensor_)); + mOutputIdxMap.insert(std::make_pair(tensor, mOutputIdxMap.size())); + // TensorUtils::getDescribe(tensor)->memoryType = Tensor::InsideDescribe::MEMORY_HOST; + // const_cast(tensor->buffer()).host = (uint8_t*)MNNMemoryAllocAlign(tensor->size(), MNN_MEMORY_ALIGN_DEFAULT); + // MNN_ASSERT(tensor->buffer().host != nullptr); + } + getTensorIdx(tensor); + // Don't need release + return new Backend::MemObj; + } + + bool NNAPIBackend::onClearBuffer() { + mInputContentTensors.clear(); + mOutputContentTensors.clear(); + mInputTensors.clear(); + mOutputTensors.clear(); + mInputIdxMap.clear(); + mOutputIdxMap.clear(); + return true; + } + + void NNAPIBackend::onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) const { + bool isInputCopy = TensorUtils::getDescribe(dstTensor)->usage==Tensor::InsideDescribe::Usage::INPUT; + bool isOutputCopy = TensorUtils::getDescribe(srcTensor)->usage==Tensor::InsideDescribe::Usage::OUTPUT; + bool isConst = TensorUtils::getDescribe(srcTensor)->usage==Tensor::InsideDescribe::Usage::CONSTANT || TensorUtils::getDescribe(dstTensor)->usage==Tensor::InsideDescribe::Usage::CONSTANT; + + if(isConst){ return; } + + if (isInputCopy) { + const auto iter = mInputIdxMap.find(dstTensor); + MNN_ASSERT(iter != mInputIdxMap.end()); + // memcpy((void*)&mInputTensors[iter->second], &srcTensor, sizeof(void*)); + auto code = CPUTensorConverter::convert(srcTensor, mInputContentTensors[iter->second].get()); + if (NO_ERROR != code) { + MNN_ERROR("Error in NNAPIBackend::onCopyBuffer:convert\n"); + } + } else if (isOutputCopy) { + const auto iter = mOutputIdxMap.find(srcTensor); + MNN_ASSERT(iter != mOutputIdxMap.end()); + // memcpy(dstTensor->host(), srcTensor->host(), std::min(srcTensor->size(), dstTensor->size())); + auto code = CPUTensorConverter::convert(mOutputContentTensors[iter->second].get(), dstTensor); + if (NO_ERROR != code) { + MNN_ERROR("Error in NNAPIBackend::onCopyBuffer:convert\n"); + } + } + } + + void NNAPIBackend::onResizeBegin() { + } + + void NNAPIBackend::onResizeEnd() { + buildModel(); + } + + uint32_t NNAPIBackend::getTensorIdx(const Tensor* t) { + const auto& iter = mTensorIdxMap.find(t); + if (iter != mTensorIdxMap.end()) { + return iter->second; + } + std::vector dims; + for (auto d : t->shape()) { + dims.push_back(d); + } + std::vector udims(dims.begin(), dims.end()); + if (TensorUtils::getDescribe(t)->dimensionFormat != MNN_DATA_FORMAT_NHWC && !mNCHW) { + // NCHW -> NHWC + udims[0] = dims[0]; + udims[1] = dims[2]; + udims[2] = dims[3]; + udims[3] = dims[1]; + } + uint32_t idx = buildOperand(nullptr, 0, ANEURALNETWORKS_TENSOR_FLOAT32, udims); + mTensorIdxMap.insert(std::make_pair(t, idx)); + return idx; + } + uint32_t NNAPIBackend::buildScalar(int scalar) { + auto iter = mScalarIntMap.find(scalar); + if (iter != mScalarIntMap.end()) { + return iter->second; + } + auto scalarIdx = buildOperand(&scalar, 4, ANEURALNETWORKS_INT32); + mScalarIntMap.insert(std::make_pair(scalar, scalarIdx)); + return scalarIdx; + } + uint32_t NNAPIBackend::buildScalar(bool scalar) { + auto iter = mScalarBoolMap.find(scalar); + if (iter != mScalarBoolMap.end()) { + return iter->second; + } + uint8_t value = scalar; + auto scalarIdx = buildOperand(&value, 1, ANEURALNETWORKS_BOOL); + mScalarBoolMap.insert(std::make_pair(scalar, scalarIdx)); + return scalarIdx; + } + uint32_t NNAPIBackend::buildScalar(float scalar) { + auto iter = mScalarFloatMap.find(scalar); + if (iter != mScalarFloatMap.end()) { + return iter->second; + } + auto scalarIdx = buildOperand(&scalar, 4, ANEURALNETWORKS_FLOAT32); + mScalarFloatMap.insert(std::make_pair(scalar, scalarIdx)); + return scalarIdx; + } + + uint32_t NNAPIBackend::buildOperand(const void* data, size_t size, OperandCode code, std::vector dims) { + ANeuralNetworksOperandType operandType { + .type = code, + .dimensionCount = static_cast(dims.size()), + .dimensions = dims.empty() ? nullptr : dims.data(), + .scale = 0.0f, + .zeroPoint = 0, + }; + CHECK(ANeuralNetworksModel_addOperand_27, mNNAPIModel, &operandType); + uint32_t operandIdx = mTensorIdx++; +#ifdef NNAPI_DEBUG + MNN_PRINT("build operand : {\n"); + MNN_PRINT("\tidx : %d\n", operandIdx); + MNN_PRINT("\tdata : %p\n", data); + MNN_PRINT("\tsize : %d\n", size); + MNN_PRINT("\ttype : %d\n", operandType.type); + MNN_PRINT("\tdimensions : [ "); + for (auto i : dims) MNN_PRINT("%d, ", i); + MNN_PRINT("]\n}\n"); +#endif + if (data && size) { + CHECK(ANeuralNetworksModel_setOperandValue_27, mNNAPIModel, operandIdx, data, size); + } + return operandIdx; + } + + ErrorCode NNAPIBackend::buildOperation(int op, const std::vector &inputs, const std::vector &outputs, const char* name) { +#ifdef NNAPI_DEBUG + MNN_PRINT("build operation : {\n"); + MNN_PRINT("\ttype : %d\n", op); + MNN_PRINT("\tinputs : [ "); + for (auto i : inputs) MNN_PRINT("%d, ", i); + MNN_PRINT("]\n\toutputs : [ "); + for (auto i : outputs) MNN_PRINT("%d, ", i); + MNN_PRINT("]\n}\n"); +#endif + if (name) mOpNames.push_back(name); + CHECK(ANeuralNetworksModel_addOperation_27, + mNNAPIModel, op, + inputs.size(), inputs.data(), + outputs.size(), outputs.data()); + return NO_ERROR; + } + + void NNAPIBackend::buildModel() { + // set input and output of model + std::vector inputOperands(mInputTensors.size()), outputOperands(mOutputTensors.size()); + for (int i = 0; i < mInputTensors.size(); i++) { + inputOperands[i] = getTensorIdx(mInputTensors[i]); + } + for (int i = 0; i < mOutputTensors.size(); i++) { + outputOperands[i] = getTensorIdx(mOutputTensors[i]); + } +#ifdef NNAPI_DEBUG + MNN_PRINT("set model's inputs & outputs : {\n"); + MNN_PRINT("\tinputs : [ "); + for (auto i : inputOperands) MNN_PRINT("%d, ", i); + MNN_PRINT("]\n\toutputs : [ "); + for (auto i : outputOperands) MNN_PRINT("%d, ", i); + MNN_PRINT("]\n}\n"); +#endif + CHECK(ANeuralNetworksModel_identifyInputsAndOutputs_27, + mNNAPIModel, + inputOperands.size(), + inputOperands.data(), + outputOperands.size(), + outputOperands.data()); + // segment fault + CHECK(ANeuralNetworksModel_finish_27, mNNAPIModel); + std::unique_ptr supports(new bool[mOpNames.size()]); + int selectDeviceIdx = -1; + for (int i = 0; i < mNNAPIDevices.size(); i++) { + auto device = mNNAPIDevices[i].device; + auto name = mNNAPIDevices[i].name; + auto type = mNNAPIDevices[i].type; + CHECK(ANeuralNetworksModel_getSupportedOperationsForDevices_29, mNNAPIModel, &device, 1, supports.get()); + MNN_PRINT("[NNAPI] device [%d : %s] supportOps = {\n", i, name); + bool allsupport = true; + for (int i = 0; i < mOpNames.size(); i++) { + allsupport &= supports[i]; + MNN_PRINT("\t%s : %d\n", mOpNames[i], supports[i]); + } + MNN_PRINT("}\n"); + if (allsupport) { + selectDeviceIdx = i; + MNN_PRINT("[NNAPI] using device [%d : %s : %d].\n", i, name, type); + break; + } + } + MNN_PRINT("[NNAPI] using device [%d : %s].\n", selectDeviceIdx, mNNAPIDevices[selectDeviceIdx].name); + CHECK(ANeuralNetworksCompilation_createForDevices_29, mNNAPIModel, &mNNAPIDevices[selectDeviceIdx].device, 1, &mNNAPICompilation); + CHECK(ANeuralNetworksCompilation_setPreference_27, mNNAPICompilation, ANEURALNETWORKS_PREFER_SUSTAINED_SPEED); + CHECK(ANeuralNetworksCompilation_finish_27, mNNAPICompilation); + CHECK(ANeuralNetworksBurst_create_29, mNNAPICompilation, &mNNAPIBurst); + } + + void NNAPIBackend::invokeModel() const { +// #define NNAPI_PROFILE + ANeuralNetworksExecution *execution; + CHECK(ANeuralNetworksExecution_create_27, mNNAPICompilation, &execution); +#ifdef NNAPI_PROFILE + CHECK(ANeuralNetworksExecution_setMeasureTiming, execution, true); +#endif + for (int i = 0; i < mInputTensors.size(); i++) { + const void* data = mInputContentTensors[i]->host(); + size_t size = mInputContentTensors[i]->size(); + CHECK(ANeuralNetworksExecution_setInput_27, execution, i, nullptr, data, size); + } + for (int i = 0; i < mOutputTensors.size(); i++) { + void* data = mOutputContentTensors[i]->host(); + size_t size = mOutputContentTensors[i]->size(); + CHECK(ANeuralNetworksExecution_setOutput_27, execution, i, nullptr, data, size); + } +#if 0 + ANeuralNetworksEvent *event = nullptr; + CHECK(ANeuralNetworksExecution_startCompute, execution, &event); + CHECK(ANeuralNetworksEvent_wait, event); + ANeuralNetworksEvent_free(event); +#else + CHECK(ANeuralNetworksExecution_compute_29, execution); + // CHECK(ANeuralNetworksExecution_burstCompute_29, execution, mNNAPIBurst); +#endif +#ifdef NNAPI_PROFILE + uint64_t duration; + CHECK(ANeuralNetworksExecution_getDuration, execution, ANEURALNETWORKS_DURATION_IN_DRIVER, &duration); + if (duration != UINT64_MAX) MNN_PRINT("[NNAPI] driver time : %f ms\n", duration / 1000000.0); + CHECK(ANeuralNetworksExecution_getDuration, execution, ANEURALNETWORKS_DURATION_ON_HARDWARE, &duration); + if (duration != UINT64_MAX) MNN_PRINT("[NNAPI] hardware time : %f ms\n", duration / 1000000.0); +#endif + ANeuralNetworksExecution_free_27(execution); + } + + NNAPIRuntime::NNAPIRuntime(const Backend::Info& info) { + mInfo = info; + BackendConfig::PrecisionMode precision = BackendConfig::Precision_Normal; + BackendConfig::PowerMode power = BackendConfig::Power_Normal; + if (nullptr != mInfo.user) { + precision = mInfo.user->precision; + power = mInfo.user->power; + } + + mPrecision = precision; + } + + NNAPIRuntime::~NNAPIRuntime() {} + + Backend* NNAPIRuntime::onCreate(const BackendConfig* config) const { + return new NNAPIBackend(this); + } + + void NNAPIRuntime::onGabageCollect(int level) { + // nothing now + } + NNAPIRuntime::CompilerType NNAPIRuntime::onGetCompilerType() const { + return Compiler_Geometry; + } + + struct NNAPIBackendCreator : RuntimeCreator { + + virtual Runtime* onCreate(const Backend::Info& info) const override { + return new NNAPIRuntime(info); + } + + virtual bool onValid(Backend::Info& info) const override { + return true; + } + }; + + void registerNNAPIRuntimeCreator() { + if (!loadNNAPISymbol()) { + return; + } + registerNNAPIOps(); + MNNInsertExtraRuntimeCreator(MNN_FORWARD_NN, new NNAPIBackendCreator, true); + } +} diff --git a/source/backend/nnapi/backend/NNAPIBackend.hpp b/source/backend/nnapi/backend/NNAPIBackend.hpp new file mode 100644 index 000000000..053cab74e --- /dev/null +++ b/source/backend/nnapi/backend/NNAPIBackend.hpp @@ -0,0 +1,134 @@ +// +// NNAPIBackend.hpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef MNN_NNAPIBACKEND_H +#define MNN_NNAPIBACKEND_H + +#include +#include +#include +#include +#include +#include +#include "MNN_generated.h" +#include "NNAPIDefine.hpp" +#include "NNAPISymbol.hpp" + +namespace MNN { + class NNAPIRuntime : public Runtime { + public: + NNAPIRuntime(const Backend::Info& info); + virtual ~NNAPIRuntime(); + virtual CompilerType onGetCompilerType() const override; + virtual Backend* onCreate(const BackendConfig* conf) const override; + virtual void onGabageCollect(int level) override; + virtual std::pair onGetCache() override { + return std::make_pair(mCacheBuffer, mCacheSize); + } + + private: + Backend::Info mInfo; + BackendConfig::PrecisionMode mPrecision; + const void* mCacheBuffer = nullptr; + size_t mCacheSize = 0; + + friend class NNAPIBackend; + }; + + class NNAPIBackend : public Backend { + public: + + NNAPIBackend(const NNAPIRuntime* runtime); + virtual ~NNAPIBackend(); + + virtual Execution* onCreate(const std::vector& inputs, const std::vector& outputs, const MNN::Op* op) override; + + virtual void onExecuteBegin() const override; + virtual void onExecuteEnd() const override; + + virtual Backend::MemObj* onAcquire(const Tensor* tensor, StorageType storageType) override; + virtual bool onClearBuffer() override; + virtual void onCopyBuffer(const Tensor* srcTensor, const Tensor* dstTensor) const override; + + virtual void onResizeBegin() override; + virtual void onResizeEnd() override; + + public: + class Creator { + public: + virtual Execution* onCreate(const std::vector& inputs, const std::vector& outputs, + const MNN::Op* op, Backend* backend) const = 0; + }; + static bool addCreator(OpType t, Creator* c); + // NNAPI functions + bool NCHW() { return mNCHW; } + uint32_t getTensorIdx(const Tensor* t); + uint32_t buildScalar(int scalar); + uint32_t buildScalar(bool scalar); + uint32_t buildScalar(float scalar); + uint32_t buildOperand(const void* data, size_t size, OperandCode code, std::vector dims = {}); + ErrorCode buildOperation(int op, const std::vector &inputs, const std::vector &outputs, const char* name = nullptr); + void buildModel(); + void invokeModel() const; + private: + bool mNCHW = false; + std::vector mModelName; + const NNAPIRuntime* mNPURuntime; + BackendConfig::PrecisionMode mPrecision; + std::vector> mInputContentTensors, mOutputContentTensors; + std::vector mInputTensors, mOutputTensors; + // tensor idx map + std::map mTensorIdxMap, mInputIdxMap, mOutputIdxMap; + uint32_t mTensorIdx = 0; + std::vector mOpNames; + // scalar idx map + std::map mScalarIntMap; + std::map mScalarBoolMap; + std::map mScalarFloatMap; + // NNAPI resource + struct NNAPIDevice { + ANeuralNetworksDevice* device; + const char* name; + int32_t type; + }; + std::vector mNNAPIDevices; + ANeuralNetworksModel *mNNAPIModel = nullptr; + ANeuralNetworksCompilation *mNNAPICompilation = nullptr; + ANeuralNetworksBurst* mNNAPIBurst = NULL; + }; + + template + class NNAPICreatorRegister { + public: + NNAPICreatorRegister(OpType type) { + T *t = new T; + NNAPIBackend::addCreator(type, t); + } + ~NNAPICreatorRegister() = default; + }; + + template + class TypedCreator : public NNAPIBackend::Creator { + public: + virtual ~TypedCreator() = default; + virtual Execution *onCreate(const std::vector &inputs, const std::vector &outputs, const MNN::Op *op, + Backend *backend) const override { + auto newOp = new T(backend, op, inputs, outputs); + return newOp; + } + }; + +#define REGISTER_NNAPI_OP_CREATOR(name, opType) \ + void ___##name##__##opType##__() { \ + static TypedCreator _temp;\ + NNAPIBackend::addCreator(opType, &_temp); \ + } + +} + +#endif //MNN_NNAPIBACKEND_H diff --git a/source/backend/nnapi/backend/NNAPIDefine.hpp b/source/backend/nnapi/backend/NNAPIDefine.hpp new file mode 100644 index 000000000..dbf517965 --- /dev/null +++ b/source/backend/nnapi/backend/NNAPIDefine.hpp @@ -0,0 +1,23 @@ +// +// NNAPIDefine.hpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef NNAPIDefine_h +#define NNAPIDefine_h + +#ifdef MNN_NNAPI_ENABLED +#ifdef __ANDROID__ +#include "NNAPINeuralNetworks.h" +#define ANDROID_API_LEVEL (android_get_device_api_level()) +#else +#undef MNN_NNAPI_ENABLED +#define MNN_NNAPI_ENABLED 0 +#define ANDROID_API_LEVEL (0) +#endif +#endif + +#endif /* NNAPIDefine_h */ diff --git a/source/backend/nnapi/backend/NNAPINeuralNetworks.h b/source/backend/nnapi/backend/NNAPINeuralNetworks.h new file mode 100644 index 000000000..2342f5f1c --- /dev/null +++ b/source/backend/nnapi/backend/NNAPINeuralNetworks.h @@ -0,0 +1,6504 @@ +/* + * Copyright (C) 2017 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/** + * @addtogroup MNNNeuralNetworks + * @{ + */ + +/** + * @file MNNNeuralNetworks.h + * copy this file From NDK, comment out the `__ANDROID_API__` code for low api compile. + * the symbol will be loaded by `dlopen`. + */ + +#ifndef ANDROID_FRAMEWORKS_ML_NN_RUNTIME_NEURAL_NETWORKS_H +#define ANDROID_FRAMEWORKS_ML_NN_RUNTIME_NEURAL_NETWORKS_H + +/****************************************************************** + * + * IMPORTANT NOTICE: + * + * This file is part of Android's set of stable system headers + * exposed by the Android NDK (Native Development Kit). + * + * Third-party source AND binary code relies on the definitions + * here to be FROZEN ON ALL UPCOMING PLATFORM RELEASES. + * + * - DO NOT MODIFY ENUMS (EXCEPT IF YOU ADD NEW 32-BIT VALUES) + * - DO NOT MODIFY CONSTANTS OR FUNCTIONAL MACROS + * - DO NOT CHANGE THE SIGNATURE OF FUNCTIONS IN ANY WAY + * - DO NOT CHANGE THE LAYOUT OR SIZE OF STRUCTURES + */ + +#include +#include +#include +#include + +__BEGIN_DECLS + +/** + * Operand types. + * + * The type of an operand in a model. + * + * Types prefaced with ANEURALNETWORKS_TENSOR_* must be used for tensor data (i.e., tensors + * with at least one dimension). Types not prefaced by ANEURALNETWORKS_TENSOR_* represent + * scalar values and must have no dimensions. + * + * Although we define many types, most operators accept just a few + * types. Most used are {@link ANEURALNETWORKS_TENSOR_FLOAT32}, + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * and {@link ANEURALNETWORKS_INT32}. + * + * Available since API level 27. + */ +typedef enum { + /** A 32 bit floating point scalar value. */ + ANEURALNETWORKS_FLOAT32 = 0, + /** A signed 32 bit integer scalar value. */ + ANEURALNETWORKS_INT32 = 1, + /** An unsigned 32 bit integer scalar value. */ + ANEURALNETWORKS_UINT32 = 2, + /** A tensor of 32 bit floating point values. */ + ANEURALNETWORKS_TENSOR_FLOAT32 = 3, + /** A tensor of 32 bit integer values. */ + ANEURALNETWORKS_TENSOR_INT32 = 4, + /** + * A tensor of 8 bit unsigned integers that represent real numbers. + * + * Attached to this tensor are two numbers that can be used to convert the + * 8 bit integer to the real value and vice versa. These two numbers are: + * - scale: a 32 bit floating point value greater than zero. + * - zeroPoint: a 32 bit integer, in range [0, 255]. + * + * The formula is: + * real_value = (integer_value - zeroPoint) * scale. + */ + ANEURALNETWORKS_TENSOR_QUANT8_ASYMM = 5, +// #if __ANDROID_API__ >= __ANDROID_API_Q__ + /** + * An 8 bit boolean scalar value. + * + * Values of this operand type are either true or false. A zero value + * represents false; any other value represents true. + * + * Available since API level 29. + */ + ANEURALNETWORKS_BOOL = 6, + /** + * A tensor of 16 bit signed integers that represent real numbers. + * + * Attached to this tensor is a number representing real value scale that is + * used to convert the 16 bit number to a real value in the following way: + * realValue = integerValue * scale. + * + * scale is a 32 bit floating point with value greater than zero. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TENSOR_QUANT16_SYMM = 7, + /** + * A tensor of IEEE 754 16 bit floating point values. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TENSOR_FLOAT16 = 8, + /** + * A tensor of 8 bit boolean values. + * + * Values of this operand type are either true or false. A zero value + * represents false; any other value represents true. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TENSOR_BOOL8 = 9, + /** + * An IEEE 754 16 bit floating point scalar value. + * + * Available since API level 29. + */ + ANEURALNETWORKS_FLOAT16 = 10, + /** + * A tensor of 8 bit signed integers that represent real numbers. + * + * This tensor is associated with additional fields that can + * be used to convert the 8 bit signed integer to the real value and vice versa. + * These fields are: + * - channelDim: a 32 bit unsigned integer indicating channel dimension. + * - scales: an array of positive 32 bit floating point values. + * The size of the scales array must be equal to dimensions[channelDim]. + * + * {@link ANeuralNetworksModel_setOperandSymmPerChannelQuantParams} must be used + * to set the parameters for an Operand of this type. + * + * The channel dimension of this tensor must not be unknown (dimensions[channelDim] != 0). + * + * The formula is: + * realValue[..., C, ...] = + * integerValue[..., C, ...] * scales[C] + * where C is an index in the Channel dimension. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL = 11, + /** + * A tensor of 16 bit unsigned integers that represent real numbers. + * + * Attached to this tensor are two numbers that can be used to convert the + * 16 bit integer to the real value and vice versa. These two numbers are: + * - scale: a 32 bit floating point value greater than zero. + * - zeroPoint: a 32 bit integer, in range [0, 65535]. + * + * The formula is: + * real_value = (integer_value - zeroPoint) * scale. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TENSOR_QUANT16_ASYMM = 12, + /** + * A tensor of 8 bit signed integers that represent real numbers. + * + * Attached to this tensor is a number representing real value scale that is + * used to convert the 8 bit number to a real value in the following way: + * realValue = integerValue * scale. + * + * scale is a 32 bit floating point with value greater than zero. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TENSOR_QUANT8_SYMM = 13, +// #endif // __ANDROID_API__ >= __ANDROID_API_Q__ +} OperandCode; + +/** + * Operation types. + * + * The type of an operation in a model. + * + * Available since API level 27. + */ +typedef enum { + // Operations below are available since API level 27. + + /** + * Adds two tensors, element-wise. + * + * Takes two input tensors of identical {@link OperandCode} and compatible + * dimensions. The output is the sum of both input tensors, optionally + * modified by an activation function. + * + * Two dimensions are compatible when: + * 1. they are equal, or + * 2. one of them is 1 + * + * The size of the output is the maximum size along each dimension of the + * input operands. It starts with the trailing dimensions, and works its + * way forward. + * + * Example: + * + * input1.dimension = {4, 1, 2} + * input2.dimension = {5, 4, 3, 1} + * output.dimension = {5, 4, 3, 2} + * + * Since API level 29, generic zero-sized input tensor is supported. Zero + * dimension is only compatible with 0 or 1. The size of the output + * dimension is zero if either of corresponding input dimension is zero. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions + * as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scales and zeroPoint can be different from input0 scale and zeroPoint. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * + * Outputs: + * * 0: The sum, a tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from inputs' scale and zeroPoint. + * + * Available since API level 27. + */ + ANEURALNETWORKS_ADD = 0, + + /** + * Performs a 2-D average pooling operation. + * + * The output dimensions are functions of the filter dimensions, stride, and + * padding. + * + * The values in the output tensor are computed as: + * + * output[b, i, j, channel] = + * sum_{di, dj}( + * input[b, strides[1] * i + di, strides[2] * j + dj, channel] + * ) / sum(1) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Both explicit padding and implicit padding are supported. + * + * Inputs (explicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the left, in the ‘width’ dimension. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the right, in the ‘width’ dimension. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the top, in the ‘height’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the bottom, in the ‘height’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * width. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * height. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Inputs (implicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit + * padding scheme, has to be one of the + * {@link PaddingCode} values. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * width. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * height. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, out_height, out_width, depth]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_AVERAGE_POOL_2D = 1, + + /** + * Concatenates the input tensors along the given dimension. + * + * The input tensors must have identical {@link OperandCode} and the same + * dimensions except the dimension along the concatenation axis. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * (full support since API level 29, see the input section) + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0 ~ n-1: The list of n input tensors, of shape + * [D0, D1, ..., Daxis(i), ..., Dm]. + * Before API level 29, all input tensors of + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * must have the same scale and zeroPoint as the output tensor. + * Since API level 29, zero-sized tensors are supported. + * * n: An {@link ANEURALNETWORKS_INT32} scalar, specifying the + * concatenation axis. + * + * Outputs: + * * 0: The output, a tensor of the same {@link OperandCode} as the input + * tensors. The output shape is [D0, D1, ..., sum(Daxis(i)), ..., Dm]. + * Since API level 29, for a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint values can be different from + * input tensors. Before API level 29 they have to be the same as for the input tensors. + * + * Available since API level 27. + */ + ANEURALNETWORKS_CONCATENATION = 2, + + /** + * Performs a 2-D convolution operation. + * + * The CONV_2D op sweeps a 2-D filter that can mix channels together over a + * batch of images, applying the filter to each window of each image of the + * appropriate size. + * + * The output dimensions are functions of the filter dimensions, stride, and + * padding. + * + * The values in the output tensor are computed as: + * + * output[b, i, j, channel] = + * sum_{di, dj, k} ( + * input[b, strides[1] * i + di, strides[2] * j + dj, k] * + * filter[channel, di, dj, k] + * ) + bias[channel] + * + * Supported tensor {@link OperandCode} configurations: + * * 32 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias. + * + * * Quantized: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to + * * * input.scale * filter.scale). + * + * Available since API level 29: + * * 16 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias. + * + * * Quantized with symmetric per channel quantization for the filter: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output. + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0, + * * * each value scaling is separate and equal to input.scale * filter.scales[channel]). + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Both explicit padding and implicit padding are supported. + * + * Inputs (explicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: A 4-D tensor, of shape + * [depth_out, filter_height, filter_width, depth_in], specifying the + * filter. + * For tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} + * the channel dimension (ANeuralNetworksSymmPerChannelQuantParams::channelDim) + * must be set to 0. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * or {@link ANEURALNETWORKS_TENSOR_FLOAT16} the bias must be of the same + * type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint + * of 0 and bias_scale == input_scale * filter_scale. + * For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 + * and bias_scale of 0. The actual scale of each value 'i' is equal to + * bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the left, in the ‘width’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the right, in the ‘width’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the top, in the ‘height’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the bottom, in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * * 11: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on width dimension. If this input is set, + * input 12 (dilation factor for height) must be specified as well. + * Available since API level 29. + * * 12: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on height dimension. If this input is set, + * input 11 (dilation factor for width) must be specified as well. + * Available since API level 29. + * + * Inputs (implicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: A 4-D tensor, of shape + * [depth_out, filter_height, filter_width, depth_in], specifying the + * filter. + * For tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} + * the channel dimension (ANeuralNetworksSymmPerChannelQuantParams::channelDim) + * must be set to 0. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * or {@link ANEURALNETWORKS_TENSOR_FLOAT16} the bias must be of the same + * type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint + * of 0 and bias_scale == input_scale * filter_scale. + * For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 + * and bias_scale of 0. The actual scale of each value 'i' is equal to + * bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit + * padding scheme, has to be one of the + * {@link PaddingCode} values. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * * 8: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on width dimension. If this input is set, + * input 9 (dilation factor for height) must be specified as well. + * Available since API level 29. + * * 9: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on height dimension. If this input is set, + * input 8 (dilation factor for width) must be specified as well. + * Available since API level 29. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, out_height, out_width, depth_out]. + * Before API level 29, for output tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the following condition must be satisfied: output_scale > input_scale * filter_scale + * + * Available since API level 27. + */ + ANEURALNETWORKS_CONV_2D = 3, + + /** + * Performs a depthwise 2-D convolution operation. + * + * Given an input tensor of shape [batches, height, width, depth_in] and a + * filter tensor of shape [1, filter_height, filter_width, depth_out] + * containing depth_out convolutional filters of depth 1, DEPTHWISE_CONV + * applies a different filter to each input channel (expanding from 1 + * channel to channel_multiplier channels for each), then concatenates the + * results together. + * + * The output has depth_out = depth_in * depth_multiplier channels. + * The output dimensions are functions of the filter dimensions, stride, and + * padding. + * + * The values in the output tensor are computed as: + * + * output[b, i, j, k * channel_multiplier + q] = + * sum_{di, dj} ( + * input[b, strides[1] * i + di, strides[2] * j + dj, k] * + * filter[1, di, dj, k * channel_multiplier + q] + * ) + bias[k * channel_multiplier + q] + * + * Supported tensor {@link OperandCode} configurations: + * * 32 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias. + * + * * Quantized: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to + * * * input.scale * filter.scale). + * + * Available since API level 29: + * * 16 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias. + * + * * Quantized with symmetric per channel quantization for the filter: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output. + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0, + * * * each value scaling is separate and equal to input.scale * filter.scales[channel]). + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Both explicit padding and implicit padding are supported. + * + * Inputs (explicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * * 1: A 4-D tensor, of shape [1, filter_height, filter_width, depth_out], + * specifying the filter. + * For tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} + * the channel dimension (ANeuralNetworksSymmPerChannelQuantParams::channelDim) + * must be set to 3. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * or {@link ANEURALNETWORKS_TENSOR_FLOAT16} the bias must be of the same + * type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint + * of 0 and bias_scale == input_scale * filter_scale. + * For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 + * and bias_scale of 0. The actual scale of each value 'i' is equal to + * bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the left, in the ‘width’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the right, in the ‘width’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the top, in the ‘height’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the bottom, in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, specifying the depthwise + * multiplier. + * * 10: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 11: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * * 12: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on width dimension. If this input is set, + * input 13 (dilation factor for height) must be specified as well. + * Available since API level 29. + * * 13: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on height dimension. If this input is set, + * input 12 (dilation factor for width) must be specified as well. + * Available since API level 29. + * + * Inputs (implicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * * 1: A 4-D tensor, of shape [1, filter_height, filter_width, depth_out], + * specifying the filter. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * or {@link ANEURALNETWORKS_TENSOR_FLOAT16} the bias must be of the same + * type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint + * of 0 and bias_scale == input_scale * filter_scale. + * For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 + * and bias_scale of 0. The actual scale of each value 'i' is equal to + * bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit + * padding scheme, has to be one of the + * {@link PaddingCode} values. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the depthwise + * multiplier. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 8: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * * 9: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for width. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on width dimension. If this input is set, + * input 10 (dilation factor for height) must be specified as well. + * Available since API level 29. + * * 10: An optional {@link ANEURALNETWORKS_INT32} scalar, specifying the dilation + * factor for height. Defaults to 1. If set to k > 1, there will be k-1 skipped + * cells between each filter element on height dimension. If this input is set, + * input 9 (dilation factor for width) must be specified as well. + * Available since API level 29. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, out_height, out_width, depth_out]. Before API level 29, for + * output tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the following condition must be satisfied: + * output_scale > input_scale * filter_scale + * + * Available since API level 27. + */ + ANEURALNETWORKS_DEPTHWISE_CONV_2D = 4, + + /** + * Rearranges data from depth into blocks of spatial data. + * + * More specifically, this op outputs a copy of the input tensor where + * values from the depth dimension are moved in spatial blocks to the height + * and width dimensions. The value block_size indicates the input block size + * and how the data is moved. + * + * Chunks of data of size block_size * block_size from depth are rearranged + * into non-overlapping blocks of size block_size x block_size. + * + * The width of the output tensor is input_depth * block_size, whereas the + * height is input_height * block_size. The depth of the input tensor must + * be divisible by block_size * block_size + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Inputs: + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the block_size. + * block_size must be >=1 and block_size * block_size must be a divisor + * of the input depth. + * * 2: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Outputs: + * * 0: The output 4-D tensor, of shape [batch, height*block_size, + * width*block_size, depth/(block_size*block_size)]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_DEPTH_TO_SPACE = 5, + + /** + * Dequantizes the input tensor. + * + * The formula is: + * + * output = (input - zeroPoint) * scale. + * + * Supported input tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} (since API level 29) + * + * Supported output tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32}. + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: A tensor. + * Since API level 29, this tensor may be zero-sized. + * + * Outputs: + * * 0: A tensor with the same shape as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_DEQUANTIZE = 6, + + /** + * Looks up sub-tensors in the input tensor. + * + * This operator takes for input a tensor of values (Values) and + * a one-dimensional tensor of selection indices (Lookups). + * The output tensor is the concatenation of sub-tensors of Values as + * selected by Lookups. + * + * Think of Values as being sliced along its first dimension: + * The entries in Lookups select which slices are concatenated together + * to create the output tensor. + * + * For example, if Values has shape of [40, 200, 300] and + * Lookups has shape of [3], all three values found in Lookups are + * expected to be between 0 and 39. The resulting tensor must + * have shape of [3, 200, 300]. + * + * If a value in Lookups is out of bounds, the operation must fail + * and an error must be reported. + * + * Supported value tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported value tensor rank: from 2 + * + * Inputs: + * * 0: Lookups. A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. + * The values are indices into the first dimension of Values. + * * 1: Values. An n-D tensor, where n >= 2, from which sub-tensors are + * extracted. + * + * Output: + * * 0: A n-D tensor with the same rank and shape as the Values + * tensor, except for the first dimension which has the same size + * as Lookups' only dimension. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input1. + * + * Available since API level 27. + */ + ANEURALNETWORKS_EMBEDDING_LOOKUP = 7, + + /** + * Computes element-wise floor() on the input tensor. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor, of the same {@link OperandCode} and dimensions as + * the input tensor. + * + * Available since API level 27. + */ + ANEURALNETWORKS_FLOOR = 8, + + /** + * Denotes a fully (densely) connected layer, which connects all elements + * in the input tensor with each element in the output tensor. + * + * This layer implements the operation: + * + * outputs = activation(inputs * weights’ + bias) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4. + * + * Inputs: + * * 0: A tensor of at least rank 2, specifying the input. If rank is + * greater than 2, then it gets flattened to a 2-D Tensor. The + * (flattened) 2-D Tensor is reshaped (if necessary) to + * [batch_size, input_size], where "input_size" corresponds to the + * number of inputs to the layer, matching the second dimension of + * weights, and "batch_size" is calculated by dividing the number of + * elements by "input_size". + * Since API level 29, zero batch_size is supported for this tensor. + * * 1: A 2-D tensor, specifying the weights, of shape + * [num_units, input_size], where "num_units" corresponds to the number + * of output nodes. + * * 2: A 1-D tensor, of shape [num_units], specifying the bias. For input + * tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the bias should + * also be of {@link ANEURALNETWORKS_TENSOR_FLOAT32}. For input tensor + * of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the bias should be + * of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 and + * bias_scale == input_scale * filter_scale. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * + * Outputs: + * * 0: The output tensor, of shape [batch_size, num_units]. Before API level 29, for + * output tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the following + * condition must be satisfied: output_scale > input_scale * filter_scale. + * + * Available since API level 27. + */ + ANEURALNETWORKS_FULLY_CONNECTED = 9, + + /** + * Looks up sub-tensors in the input tensor using a key-value map. + * + * This operator takes for input a tensor of values (Values), + * a one-dimensional tensor of selection values (Lookups) and + * a one-dimensional tensor that maps these values to Values + * indexes. The output tensor is the concatenation of sub-tensors of + * Values as selected by Lookups via Keys. + * + * Think of Values as being sliced along its outer-most dimension. + * The output is a concatenation of selected slices, with one slice + * for each entry of Lookups. The slice selected is the one at the + * same index as the Maps entry that matches the value in Lookups. + * + * For a hit, the corresponding sub-tensor of Values is included + * in the Output tensor. For a miss, the corresponding sub-tensor in + * Output must have zero values. + * + * For example, if Values has shape of [40, 200, 300], + * Keys should have a shape of [40]. If Lookups tensor has shape + * of [3], three slices are being concatenated, so the resulting tensor + * must have the shape of [3, 200, 300]. If the first entry in Lookups + * has the value 123456, that value must be located in Keys tensor. + * If the sixth entry of Keys contains 123456, the sixth slice of Values + * must be selected. If no entry in Keys has 123456, a slice of zeroes + * must be concatenated. + * + * Supported value tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported value tensor rank: from 2 + * + * Inputs: + * * 0: Lookups. A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with + * shape [ k ]. + * * 1: Keys. A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with shape + * [ n ]; Keys and Values pair represent a map, i.e., the ith element + * in Keys (Keys[i]) is the key to select the ith sub-tensor in Values + * (Values[i]), where 0 <= i <= n-1. Keys tensor *MUST* be sorted in + * ascending order. + * * 2: Values. A tensor with shape of [ n, … ]; i.e., the first dimension + * must be n. + * + * Outputs: + * * 0: Output. A tensor with shape [ k …]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input2. + * * 1: Hits. A boolean tensor with shape [ k ] indicates whether the lookup + * hits (True) or not (False). + * Stored as {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} with offset 0 + * and scale 1.0f. + * A non-zero byte represents True, a hit. A zero indicates otherwise. + * + * Available since API level 27. + */ + ANEURALNETWORKS_HASHTABLE_LOOKUP = 10, + + /** + * Applies L2 normalization along the depth dimension. + * + * The values in the output tensor are computed as: + * + * output[batch, row, col, channel] = + * input[batch, row, col, channel] / + * sqrt(sum_{c} pow(input[batch, row, col, c], 2)) + * + * For input tensor with rank less than 4, independently normalizes each + * 1-D slice along dimension dim. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29) + * + * Supported tensor rank: up to 4 + * Tensors with rank less than 4 are only supported since API level 29. + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be normalized. + * * 1: An optional {@link ANEURALNETWORKS_INT32} scalar, default to -1, + * specifying the dimension normalization would be performed on. + * Negative index is used to specify axis from the end (e.g. -1 for + * the last axis). Must be in the range [-n, n). + * Available since API level 29. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} and same shape as input0. + * For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the scale must be 1.f / 128 and the zeroPoint must be 128. + * + * Available since API level 27. + */ + ANEURALNETWORKS_L2_NORMALIZATION = 11, + + /** + * Performs an 2-D L2 pooling operation. + * + * The output dimensions are functions of the filter dimensions, stride, and + * padding. + * + * The values in the output tensor are computed as: + * + * output[b, i, j, c] = + * sqrt(sum_{di, dj} pow(input[b, strides[1] * i + di, strides[2] * j + dj, c], 2) / + * sum(1)) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Both explicit padding and implicit padding are supported. + * + * Inputs (explicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the left, in the ‘width’ dimension. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the right, in the ‘width’ dimension. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the top, in the ‘height’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the bottom, in the ‘height’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * width. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * height. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Inputs (implicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit + * padding scheme, has to be one of the + * {@link PaddingCode} values. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * width. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * height. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, out_height, out_width, depth]. + * + * Available since API level 27. + */ + ANEURALNETWORKS_L2_POOL_2D = 12, + + /** + * Applies Local Response Normalization along the depth dimension. + * + * The 4-D input tensor is treated as a 3-D array of 1-D vectors (along the + * last dimension), and each vector is normalized independently. Within a + * given vector, each component is divided by the weighted, squared sum of + * inputs within depth_radius. + * + * The output is calculated using this formula: + * + * sqr_sum[a, b, c, d] = sum( + * pow(input[a, b, c, d - depth_radius : d + depth_radius + 1], 2)) + * output = input / pow((bias + alpha * sqr_sum), beta) + * + * For input tensor with rank less than 4, independently normalizes each + * 1-D slice along specified dimension. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: up to 4 + * Tensors with rank less than 4 are only supported since API level 29. + * + * Inputs: + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the radius of + * the normalization window. + * * 2: A scalar, specifying the bias, must not be zero. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias + * value must be of {@link ANEURALNETWORKS_FLOAT16}. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the bias + * value must be of {@link ANEURALNETWORKS_FLOAT32}. + * * 3: A scalar, specifying the scale factor, alpha. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the + * alpha value must be of {@link ANEURALNETWORKS_FLOAT16}. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the + * alpha value must be of {@link ANEURALNETWORKS_FLOAT32}. + * * 4: A scalar, specifying the exponent, beta. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the beta + * value must be of {@link ANEURALNETWORKS_FLOAT16}. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the beta + * value must be of {@link ANEURALNETWORKS_FLOAT32}. + * * 5: An optional {@link ANEURALNETWORKS_INT32} scalar, default to -1, + * specifying the dimension normalization would be performed on. + * Negative index is used to specify axis from the end (e.g. -1 for + * the last axis). Must be in the range [-n, n). + * Available since API level 29. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_LOCAL_RESPONSE_NORMALIZATION = 13, + + /** + * Computes sigmoid activation on the input tensor element-wise. + * + * The output is calculated using this formula: + * + * output = 1 / (1 + exp(-input)) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4. + * + * Inputs: + * * 0: A tensor, specifying the input. + * Since API level 29, this tensor may be zero-sized. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the scale must be 1.f / 256 and the zeroPoint must be 0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_LOGISTIC = 14, + + /** + * Projects an input to a bit vector via locality senstive hashing. + * + * Supported input tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported input tensor rank: from 1 + * + * Inputs: + * * 0: Hash functions. Dim.size == 2, DataType: Float. + * Tensor[0].Dim[0]: Number of hash functions. + * Tensor[0].Dim[1]: Number of projected output bits generated by each + * hash function. + * If the projection type is Sparse: + * Tensor[0].Dim[1] + ceil(log2(Tensor[0].Dim[0])) <= 32 + * + * * 1: Input. Dim.size >= 1, no restriction on DataType. + * * 2: Weight. Optional. Dim.size == 1, DataType: Float. + * If not set, each input element is considered to have the same weight + * of 1.0. + * Tensor[1].Dim[0] == Tensor[2].Dim[0] + * * 3: Type: + * Sparse: + * Value LSHProjectionType_SPARSE(=3) (since API level 29). + * Computed bit vector is considered to be sparse. + * Each output element is an int32 made up of multiple bits + * computed from hash functions. + * + * NOTE: To avoid collisions across hash functions, an offset value + * of k * (1 << Tensor[0].Dim[1]) will be added to each signature, + * where k is the index of the hash function. + * + * Value LSHProjectionType_SPARSE_DEPRECATED(=1). + * Legacy behavior that does not include the offset value. + * + * Dense: + * Value LSHProjectionType_DENSE(=2). + * Computed bit vector is considered to be dense. Each output + * element represents a bit and can take the value of either + * 0 or 1. + * + * Outputs: + * * 0: If the projection type is Sparse: + * Output.Dim == { Tensor[0].Dim[0] } + * A tensor of int32 that represents hash signatures. + * + * If the projection type is Dense: + * Output.Dim == { Tensor[0].Dim[0] * Tensor[0].Dim[1] } + * A flattened tensor that represents projected bit vectors. + * + * Available since API level 27. + * The offset value for sparse projections was added in API level 29. + */ + ANEURALNETWORKS_LSH_PROJECTION = 15, + + /** + * Performs a single time step in a Long Short-Term Memory (LSTM) layer + * + * The LSTM operation is described by the following equations. + * + * \f{eqnarray*}{ + * i_t =& \sigma(W_{xi}x_t+W_{hi}h_{t-1}+W_{ci}C_{t-1}+b_i) & \\ + * f_t =& \sigma(W_{xf}x_t+W_{hf}h_{t-1}+W_{cf}C_{t-1}+b_f) & \\ + * C_t =& clip(f_t \odot C_{t-1} + i_t \odot + * g(W_{xc}x_t+W_{hc}h_{t-1}+b_c),\ t_{cell}) & \\ + * o_t =& \sigma(W_{xo}x_t+W_{ho}h_{t-1}+W_{co}C_t+b_o) & \\ + * & & \\ + * & clip(W_{proj}(o_t \odot g(C_t))+b_{proj},\ t_{proj}) + * & if\ there\ is\ a\ projection; \\ + * h_t =& & \\ + * & o_t \odot g(C_t) & otherwise. \\ + * \f} + * Where: + * * \f$x_t\f$ is the input, + * * \f$i_t\f$ is the input gate, + * * \f$f_t\f$ is the forget gate, + * * \f$C_t\f$ is the cell state, + * * \f$o_t\f$ is the output, + * * \f$h_t\f$ is the output state, + * * \f$\sigma\f$ is the logistic sigmoid function, + * * \f$g\f$ is the cell input and cell output activation function, usually + * \f$tahn\f$, + * * \f$W_{xi}\f$ is the input-to-input weight matrix, + * * \f$W_{hi}\f$ is the recurrent to input weight matrix, + * * \f$W_{ci}\f$ is the cell-to-input weight matrix, + * * \f$b_i\f$ is the input gate bias, + * * \f$W_{xf}\f$ is the input-to-forget weight matrix, + * * \f$W_{hf}\f$ is the recurrent-to-forget weight matrix, + * * \f$W_{cf}\f$ is the cell-to-forget weight matrix, + * * \f$b_f\f$ is the forget gate bias, + * * \f$W_{xc}\f$ is the input-to-cell weight matrix, + * * \f$W_{hc}\f$ is the recurrent-to-cell weight matrix, + * * \f$b_c\f$ is the cell bias, + * * \f$W_{xo}\f$ is the input-to-output weight matrix, + * * \f$W_{ho}\f$ is the recurrent-to-output weight matrix, + * * \f$W_{co}\f$ is the cell-to-output weight matrix, + * * \f$b_o\f$ is the output gate bias, + * * \f$W_{proj}\f$ is the projection weight matrix, + * * \f$b_{proj}\f$ is the projection bias, + * * \f$t_{cell}\f$ is the threshold for clipping the cell state, and + * * \f$t_{proj}\f$ is the threshold for clipping the projected output. + * * \f$\odot\f$ is the + * + * Hadamard product that takes two matrices and produces another + * matrix, each element of which is the product of the corresponding + * elements of the input matrices. + * + * Since API level 29 LSTM supports layer normalization. + * In case layer normalization is used, the inputs to internal activation + * functions (sigmoid and \f$g\f$) are normalized, rescaled and recentered + * following an approach from section 3.1 from + * https://arxiv.org/pdf/1607.06450.pdf + * + * The operation has the following independently optional inputs: + * * The cell-to-input weights (\f$W_{ci}\f$), cell-to-forget weights + * (\f$W_{cf}\f$) and cell-to-output weights (\f$W_{co}\f$) either all + * have values or neither of them have values (i.e., all set to null). If + * they have values, the peephole optimization is used. + * * The input-to-input weights (\f$W_{xi}\f$), recurrent-to-input weights + * (\f$W_{hi}\f$) and input gate bias (\f$b_i\f$) either all have values, + * or none of them have values. If they have no values, coupling of input + * and forget gates (CIFG) is used, in which case the input gate + * (\f$i_t\f$) is calculated using the following equation instead. + * \f{eqnarray*}{ + * i_t = 1 - f_t + * \f} + * In case peephole optimization is used and CIFG is not used + * cell-to-input (\f$W_{ci}\f$) weights must be present. Otherwise, the + * cell-to-input weights must have no value. + * * The projection weights (\f$W_{proj}\f$) is required only for the + * recurrent projection layer, and should otherwise have no value. + * * The projection bias (\f$b_{proj}\f$) may (but not required to) have a + * value if the recurrent projection layer exists, and should otherwise + * have no value. + * * (API level 29 or later) The four layer normalization weights either all have + * values or none of them have values. Additionally, if CIFG is used, + * input layer normalization weights tensor is omitted and the other layer + * normalization weights either all have values or none of them have + * values. Layer normalization is used when the values of all the layer + * normalization weights are present. + * + * References: + * + * The default non-peephole non-CIFG implementation is based on: + * http://www.bioinf.jku.at/publications/older/2604.pdf + * S. Hochreiter and J. Schmidhuber. "Long Short-Term Memory". Neural + * Computation, 9(8):1735-1780, 1997. + * + * The peephole implementation and projection layer is based on: + * https://research.google.com/pubs/archive/43905.pdf + * Hasim Sak, Andrew Senior, and Francoise Beaufays. "Long short-term memory + * recurrent neural network architectures for large scale acoustic + * modeling." INTERSPEECH, 2014. + * (However, the concept of peephole optimization was introduced in work + * prior to this paper.) + * + * The coupling of input and forget gate (CIFG) is based on: + * http://arxiv.org/pdf/1503.04069.pdf + * Greff et al. "LSTM: A Search Space Odyssey" + * + * The layer normalization is based on: + * https://arxiv.org/pdf/1607.06450.pdf + * Jimmy Ba et al. "Layer Normalization" + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * All input and output tensors must be of the same type. + * + * Inputs: + * * 0: The input (\f$x_t\f$). + * A 2-D tensor of shape [batch_size, input_size], where “batch_size” + * corresponds to the batching dimension, and “input_size” is the size + * of the input. + * * 1: The input-to-input weights (\f$W_{xi}\f$). Optional. + * A 2-D tensor of shape [num_units, input_size], where “num_units” + * corresponds to the number of cell units. + * * 2: The input-to-forget weights (\f$W_{xf}\f$). + * A 2-D tensor of shape [num_units, input_size]. + * * 3: The input-to-cell weights (\f$W_{xc}\f$). + * A 2-D tensor of shape [num_units, input_size]. + * * 4: The input-to-output weights (\f$W_{xo}\f$). + * A 2-D tensor of shape [num_units, input_size]. + * * 5: The recurrent-to-input weights (\f$W_{hi}\f$). Optional. + * A 2-D tensor of shape [num_units, output_size], where “output_size” + * corresponds to either the number of cell units (i.e., “num_units”), + * or the second dimension of the “projection_weights”, if defined. + * * 6: The recurrent-to-forget weights (\f$W_{hf}\f$). + * A 2-D tensor of shape [num_units, output_size]. + * * 7: The recurrent-to-cell weights (\f$W_{hc}\f$). + * A 2-D tensor of shape [num_units, output_size]. + * * 8: The recurrent-to-output weights (\f$W_{ho}\f$). + * A 2-D tensor of shape [num_units, output_size]. + * * 9: The cell-to-input weights (\f$W_{ci}\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 10:The cell-to-forget weights (\f$W_{cf}\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 11:The cell-to-output weights (\f$W_{co}\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 12:The input gate bias (\f$b_i\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 13:The forget gate bias (\f$b_f\f$). + * A 1-D tensor of shape [num_units]. + * * 14:The cell bias (\f$b_c\f$). + * A 1-D tensor of shape [num_units]. + * * 15:The output gate bias (\f$b_o\f$). + * A 1-D tensor of shape [num_units]. + * * 16:The projection weights (\f$W_{proj}\f$). Optional. + * A 2-D tensor of shape [output_size, num_units]. + * * 17:The projection bias (\f$b_{proj}\f$). Optional. + * A 1-D tensor of shape [output_size]. + * * 18:The output state (in) (\f$h_{t-1}\f$). + * A 2-D tensor of shape [batch_size, output_size]. + * * 19:The cell state (in) (\f$C_{t-1}\f$). + * A 2-D tensor of shape [batch_size, num_units]. + * * 20:The activation function (\f$g\f$). + * A value indicating the activation function: + *
    + *
  • 0: None; + *
  • 1: Relu; + *
  • 3: Relu6; + *
  • 4: Tanh; + *
  • 6: Sigmoid. + *
+ * * 21:The clipping threshold (\f$t_{cell}\f$) for the cell state, such + * that values are bound within [-cell_clip, cell_clip]. If set to 0.0 + * then clipping is disabled. + * Until API level 29 this scalar must be of type {@link + * ANEURALNETWORKS_FLOAT32}. Since API level 29, if all the input + * tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32}, this + * scalar must be of the type {@link ANEURALNETWORKS_FLOAT32}, + * otherwise if all the input tensors have the type {@link + * ANEURALNETWORKS_TENSOR_FLOAT16}, this scalar must be of type {@link + * ANEURALNETWORKS_FLOAT16}. + * * 22:The clipping threshold (\f$t_{proj}\f$) for the output from the + * projection layer, such that values are bound within + * [-proj_clip, proj_clip]. If set to 0.0 then clipping is disabled. + * Until API level 29 this scalar must be of type {@link + * ANEURALNETWORKS_FLOAT32}. Since API level 29, if all the input + * tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32}, this + * scalar must be of the type {@link ANEURALNETWORKS_FLOAT32}, + * otherwise if all the input tensors have the type {@link + * ANEURALNETWORKS_TENSOR_FLOAT16}, this scalar must be of type {@link + * ANEURALNETWORKS_FLOAT16}. + * Since API level 29 there are additional inputs to this op: + * * 23:The input layer normalization weights. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at input gate. + * * 24:The forget layer normalization weights. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at forget gate. + * * 25:The cell layer normalization weights. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at cell gate. + * * 26:The output layer normalization weights. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at output gate. + * + * Outputs: + * * 0: The scratch buffer. + * A 2-D tensor of shape [batch_size, num_units * 3] with CIFG, or + * [batch_size, num_units * 4] without CIFG. + * * 1: The output state (out) (\f$h_t\f$). + * A 2-D tensor of shape [batch_size, output_size]. + * * 2: The cell state (out) (\f$C_t\f$). + * A 2-D tensor of shape [batch_size, num_units]. + * * 3: The output (\f$o_t\f$). + * A 2-D tensor of shape [batch_size, output_size]. This is effectively + * the same as the current “output state (out)” value. + * + * Available since API level 27. + */ + ANEURALNETWORKS_LSTM = 16, + + /** + * Performs an 2-D max pooling operation. + * + * The output dimensions are functions of the filter dimensions, stride, and + * padding. + * + * The values in the output tensor are computed as: + * + * output[b, i, j, channel] = + * max_{di, dj} ( + * input[b, strides[1] * i + di, strides[2] * j + dj, channel] + * ) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Both explicit padding and implicit padding are supported. + * + * Inputs (explicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the left, in the ‘width’ dimension. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the right, in the ‘width’ dimension. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the top, in the ‘height’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the bottom, in the ‘height’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * width. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * height. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 10: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Inputs (implicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit + * padding scheme, has to be one of the + * {@link PaddingCode} values. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * width. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the filter + * height. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 7: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, out_height, out_width, depth]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_MAX_POOL_2D = 17, + + /** + * Multiplies two tensors, element-wise. + * + * Takes two input tensors of identical {@link OperandCode} and compatible + * dimensions. The output is the product of both input tensors, optionally + * modified by an activation function. + * + * Two dimensions are compatible when: + * 1. they are equal, or + * 2. one of them is 1 + * + * The size of the resulting output is the maximum size along each dimension + * of the input operands. It starts with the trailing dimensions, and works + * its way forward. + * + * Since API level 29, generic zero-sized input tensor is supported. Zero + * dimension is only compatible with 0 or 1. The size of the output + * dimension is zero if either of corresponding input dimension is zero. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions + * as input0. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * + * Outputs: + * * 0: The product, a tensor of the same {@link OperandCode} as input0. + * For output tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the following condition must be satisfied: + * output_scale > input1_scale * input2_scale. + * + * Available since API level 27. + */ + ANEURALNETWORKS_MUL = 18, + + /** + * Computes rectified linear activation on the input tensor element-wise. + * + * The output is calculated using this formula: + * + * output = max(0, input) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4. + * + * Inputs: + * * 0: A tensor, specifying the input. + * Since API level 29, this tensor may be zero-sized. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_RELU = 19, + + /** + * Computes rectified linear 1 activation on the input tensor element-wise. + * + * The output is calculated using this formula: + * + * output = min(1.f, max(-1.f, input)) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4. + * + * Inputs: + * * 0: A tensor, specifying the input. + * Since API level 29, this tensor may be zero-sized. + * + * Outputs: + * * 0: The output tensor of the same shape as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_RELU1 = 20, + + /** + * Computes rectified linear 6 activation on the input tensor element-wise. + * + * The output is calculated using this formula: + * + * output = min(6, max(0, input)) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4. + * + * Inputs: + * * 0: A tensor, specifying the input. + * Since API level 29, this tensor may be zero-sized. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_RELU6 = 21, + + /** + * Reshapes a tensor. + * + * Given tensor, this operation returns a tensor that has the same values as + * tensor, but with a newly specified shape. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4. + * + * Inputs: + * * 0: A tensor, specifying the tensor to be reshaped. + * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, defining the + * shape of the output tensor. The number of elements implied by shape + * must be the same as the number of elements in the input tensor. + * + * If one component of shape is the special value -1, the size of that + * dimension is computed so that the total size remains constant. In + * particular, a shape of [-1] flattens into 1-D. At most one component + * of shape can be -1. + * + * Outputs: + * * 0: The output tensor, of shape specified by the input shape. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_RESHAPE = 22, + + /** + * Resizes images to given size using the bilinear interpretation. + * + * Resized images must be distorted if their output aspect ratio is not the + * same as input aspect ratio. The corner pixels of output may not be the + * same as corner pixels of input. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29) + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Both resizing by shape and resizing by scale are supported. + * + * Inputs (resizing by shape): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * width of the output tensor. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * height of the output tensor. + * * 3: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Inputs (resizing by scale, since API level 29): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. Zero batches is supported for this tensor. + * * 1: A scalar, specifying width_scale, the scaling factor of the width + * dimension from the input tensor to the output tensor. The output + * width is calculated as new_width = floor(width * width_scale). + * The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is + * of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} otherwise. + * * 2: A scalar, specifying height_scale, the scaling factor of the height + * dimension from the input tensor to the output tensor. The output + * height is calculated as new_height = floor(height * height_scale). + * The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is + * of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} otherwise. + * * 3: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, new_height, new_width, depth]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_RESIZE_BILINEAR = 23, + + /** + * A basic recurrent neural network layer. + * + * This layer implements the operation: + * outputs = state = activation(inputs * input_weights + + * state * recurrent_weights + bias) + * + * Where: + * * “input_weights” is a weight matrix that multiplies the inputs; + * * “recurrent_weights” is a weight matrix that multiplies the current + * “state” which itself is the output from the previous time step + * computation; + * * “bias” is a bias vector (added to each output vector in the batch); + * * “activation” is the function passed as the “fused_activation_function” + * argument (if not “NONE”). + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * The input tensors must all be the same type. + * + * Inputs: + * * 0: input. + * A 2-D tensor of shape [batch_size, input_size], where “batch_size” + * corresponds to the batching dimension, and “input_size” is the size + * of the input. + * * 1: weights. + * A 2-D tensor of shape [num_units, input_size], where “num_units” + * corresponds to the number of units. + * * 2: recurrent_weights. + * A 2-D tensor of shape [num_units, num_units], with columns + * corresponding to the weights from each unit. + * * 3: bias. + * A 1-D tensor of shape [num_units]. + * * 4: hidden state (in). + * A 2-D tensor of shape [batch_size, num_units]. + * * 5: fused_activation_function. + * An optional {@link FuseCode} value indicating the + * activation function. If “NONE” is specified then it results in a + * linear activation. + * + * Outputs: + * * 0: hidden state (out). + * A 2-D tensor of shape [batch_size, num_units]. + * + * * 1: output. + * A 2-D tensor of shape [batch_size, num_units]. This is effectively + * the same as the current state value. + * + * Available since API level 27. + */ + ANEURALNETWORKS_RNN = 24, + + /** + * Computes the softmax activation on the input tensor element-wise, per + * batch, by normalizing the input vector so the maximum coefficient is + * zero. + * + * The output is calculated using this formula: + * + * output[batch, i] = + * exp((input[batch, i] - max(input[batch, :])) * beta) / + * sum_{k}{exp((input[batch, k] - max(input[batch, :])) * beta)} + * + * For input tensor with rank other than 2, the activation will be applied + * independently on each 1-D slice along specified dimension. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4. + * Tensors with rank other than 2 or 4 are only supported since API level 29. + * + * Inputs: + * * 0: A 2-D or 4-D tensor, specifying the tensor to be reshaped. + * Since API level 29, this tensor may be zero-sized. + * * 1: A scalar, specifying the positive scaling factor for the exponent, + * beta. If input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT32} or + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the scalar must be of + * {@link ANEURALNETWORKS_FLOAT32}. + * If input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, then the + * scalar must be of {@link ANEURALNETWORKS_FLOAT16}. + * * 2: An optional {@link ANEURALNETWORKS_INT32} scalar, default to -1, + * specifying the dimension the activation would be performed on. + * Negative index is used to specify axis from the end (e.g. -1 for + * the last axis). Must be in the range [-n, n). + * Available since API level 29. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the scale must be 1.f / 256 and the zeroPoint must be 0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_SOFTMAX = 25, + + /** + * Rearranges blocks of spatial data, into depth. + * + * More specifically, this op outputs a copy of the input tensor where + * values from the height and width dimensions are moved to the depth + * dimension. The value block_size indicates the input block size and how + * the data is moved. + * + * Chunks of data of size block_size * block_size from depth are rearranged + * into non-overlapping blocks of size block_size x block_size. + * + * The depth of the output tensor is input_depth * block_size * block_size. + * The input tensor's height and width must be divisible by block_size. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Inputs: + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the block_size. + * block_size must be >=1 and block_size must be a divisor of both the + * input height and width. + * * 2: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Outputs: + * * 0: The output 4-D tensor, of shape [batches, height/block_size, + * width/block_size, depth_in*block_size*block_size]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 27. + */ + ANEURALNETWORKS_SPACE_TO_DEPTH = 26, + + /** + * SVDF op is a kind of stateful layer derived from the notion that a + * densely connected layer that's processing a sequence of input frames can + * be approximated by using a singular value decomposition of each of its + * nodes. The implementation is based on: + * + * https://research.google.com/pubs/archive/43813.pdf + * + * P. Nakkiran, R. Alvarez, R. Prabhavalkar, C. Parada. + * “Compressing Deep Neural Networks using a Rank-Constrained Topology”. + * INTERSPEECH, 2015. + * + * It processes the incoming input using a 2-stage filtering mechanism: + * * stage 1 performs filtering on the "features" dimension, whose outputs + * get pushed into a memory of fixed-size memory_size. + * * stage 2 performs filtering on the "time" dimension of the memory_size + * memoized outputs of stage 1. + * + * Specifically, for rank 1, this layer implements the operation: + * + * memory = push(conv1d(inputs, weights_feature, feature_dim, + * "ANEURALNETWORKS_PADDING_VALID")); + * outputs = activation(memory * weights_time + bias); + * + * Where: + * * “weights_feature” is a weights matrix that processes the inputs (by + * convolving the input with every “feature filter”), and whose outputs + * get pushed, stacked in order, into the fixed-size “memory” (the oldest + * entry gets dropped); + * * “weights_time” is a weights matrix that processes the “memory” (by a + * batched matrix multiplication on the num_units); + * * “bias” is an optional bias vector (added to each output vector in the + * batch); and + * * “activation” is the function passed as the “fused_activation_function” + * argument (if not “NONE”). + * + * Each rank adds a dimension to the weights matrices by means of stacking + * the filters. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * All input tensors must be the same type. + * + * Inputs: + * * 0: input. + * A 2-D tensor of shape [batch_size, input_size], where “batch_size” + * corresponds to the batching dimension, and “input_size” is the size + * of the input. + * * 1: weights_feature. + * A 2-D tensor of shape [num_units, input_size], where “num_units” + * corresponds to the number of units. + * * 2: weights_time. + * A 2-D tensor of shape [num_units, memory_size], where “memory_size” + * corresponds to the fixed-size of the memory. + * * 3: bias. + * An optional 1-D tensor of shape [num_units]. + * * 4: state (in). + * A 2-D tensor of shape [batch_size, (memory_size - 1) * num_units * rank]. + * * 5: rank. + * The rank of the SVD approximation. + * * 6: fused_activation_function. + * An optional {@link FuseCode} value indicating the + * activation function. If “NONE” is specified then it results in a + * linear activation. + * + * Outputs: + * * 0: state (out). + * A 2-D tensor of the same {@link OperandCode} as the inputs, with shape + * [batch_size, (memory_size - 1) * num_units * rank]. + * * 1: output. + * A 2-D tensor of the same {@link OperandCode} as the inputs, with shape + * [batch_size, num_units]. + * + * Available since API level 27. + */ + ANEURALNETWORKS_SVDF = 27, + + /** + * Computes hyperbolic tangent of input tensor element-wise. + * + * The output is calculated using this formula: + * + * output = tanh(input) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29) + * + * Supported tensor rank: up to 4. + * + * Inputs: + * * 0: A tensor, specifying the input. + * Since API level 29, this tensor may be zero-sized. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * For {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the scale must be 1.f / 128 and the zeroPoint must be 128. + * + * Available since API level 27. + */ + ANEURALNETWORKS_TANH = 28, + + // Operations below are available since API level 28. + + /** + * BatchToSpace for N-dimensional tensors. + * + * This operation reshapes the batch dimension (dimension 0) into M + 1 + * dimensions of shape block_shape + [batch], interleaves these blocks back + * into the grid defined by the spatial dimensions [1, ..., M], to obtain a + * result with the same rank as the input. + * + * This is the reverse of SpaceToBatch. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be reshaped + * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the block + * sizes for each spatial dimension of the input tensor. All values + * must be >= 1. + * * 2: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 28. + */ + ANEURALNETWORKS_BATCH_TO_SPACE_ND = 29, + + /** + * Element-wise division of two tensors. + * + * Takes two input tensors of identical {@link OperandCode} and compatible + * dimensions. The output is the result of dividing the first input tensor + * by the second, optionally modified by an activation function. + * + * Two dimensions are compatible when: + * 1. they are equal, or + * 2. one of them is 1 + * + * The size of the output is the maximum size along each dimension of the + * input operands. It starts with the trailing dimensions, and works its way + * forward. + * + * Example: + * input1.dimension = {4, 1, 2} + * input2.dimension = {5, 4, 3, 1} + * output.dimension = {5, 4, 3, 2} + * + * Since API level 29, generic zero-sized input tensor is supported. Zero + * dimension is only compatible with 0 or 1. The size of the output + * dimension is zero if either of corresponding input dimension is zero. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, specifying the first input. + * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions + * as input0. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * + * Available since API level 28. + */ + ANEURALNETWORKS_DIV = 30, + + /** + * Computes the mean of elements across dimensions of a tensor. + * + * Reduces the input tensor along the given dimensions to reduce. Unless + * keep_dims is true, the rank of the tensor is reduced by 1 for each entry + * in axis. If keep_dims is true, the reduced dimensions are retained with + * length 1. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: A tensor, specifying the input. + * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions + * to reduce. Must be in the range + * [-rank(input_tensor), rank(input_tensor)). + * + * NOTE: When the operation was introduced, the documentation + * incorrectly stated that if dimensions were empty, the operation + * would reduce across all dimensions. This behavior was never + * implemented. + * + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, keep_dims. If positive, + * retains reduced dimensions with length 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be same as input0. + * + * Available since API level 28. + */ + ANEURALNETWORKS_MEAN = 31, + + /** + * Pads a tensor. + * + * This operation pads a tensor according to the specified paddings. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * (full support since API level 29, see the output section) + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be padded. + * * 1: A 2-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the paddings + * for each spatial dimension of the input tensor. The shape of the + * tensor must be {rank(input0), 2}. + * padding[i, 0] specifies the number of elements to be padded in the + * front of dimension i. + * padding[i, 1] specifies the number of elements to be padded after the + * end of dimension i. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. The + * output tensor has the same rank as input0, and each + * dimension of the output tensor has the same size as the + * corresponding dimension of the input tensor plus the size + * of the padding: + * output0.dimension[i] = + * padding[i, 0] + input0.dimension[i] + padding[i, 1] + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * NOTE: Before API level 29, the pad value for + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} is undefined. + * Since API level 29, the pad value is always the logical zero. + * + * Available since API level 28. + */ + ANEURALNETWORKS_PAD = 32, + + /** + * SpaceToBatch for N-Dimensional tensors. + * + * This operation divides "spatial" dimensions [1, ..., M] of the input into + * a grid of blocks of shape block_shape, and interleaves these blocks with + * the "batch" dimension (0) such that in the output, the spatial dimensions + * [1, ..., M] correspond to the position within the grid, and the batch + * dimension combines both the position within a spatial block and the + * original batch position. Prior to division into blocks, the spatial + * dimensions of the input are optionally zero padded according to paddings. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * (full support since API level 29, see the output section) + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * NCHW is supported since API level 29. + * + * Inputs: + * * 0: An n-D tensor, specifying the input. + * * 1: A 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the block + * sizes for each spatial dimension of the input tensor. All values + * must be >= 1. + * * 2: A 2-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the paddings + * for each spatial dimension of the input tensor. All values must be + * >= 0. The shape of the tensor must be {M, 2}, where M is the number + * of spatial dimensions. + * padding[i, 0] specifies the number of element to be padded in the + * front of dimension i. + * padding[i, 1] specifies the number of element to be padded after the + * end of dimension i. + * * 3: An optional {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * Available since API level 29. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * NOTE: Before API level 29, the pad value for + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} is undefined. + * Since API level 29, the pad value is always the logical zero. + * + * Available since API level 28. + */ + ANEURALNETWORKS_SPACE_TO_BATCH_ND = 33, + + /** + * Removes dimensions of size 1 from the shape of a tensor. + * + * Given a tensor input, this operation returns a tensor of the same + * {@link OperandCode} with all dimensions of size 1 removed. If you don't + * want to remove all size 1 dimensions, you can remove specific size 1 + * dimensions by specifying the axes (input1). + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, the tensor to be squeezed. + * * 1: An optional 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The + * dimensions to squeeze. If specified only squeezes the dimensions + * listed. Otherwise, squeezes all dimensions. The dimension index + * starts at 0. An error must be reported if squeezing a dimension that + * is not 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. Contains the + * same data as input, but has one or more dimensions of size 1 + * removed. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 28. + */ + ANEURALNETWORKS_SQUEEZE = 34, + + /** + * Extracts a strided slice of a tensor. + * + * Roughly speaking, this op extracts a slice of size (end - begin) / stride + * from the given input tensor. Starting at the location specified by begin + * the slice continues by adding stride to the index until all dimensions + * are not less than end. Note that a stride can be negative, which causes a + * reverse slice. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be sliced. + * * 1: begin, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The + * starts of the dimensions of the input tensor to be sliced. The + * length must be of rank(input0). + * * 2: end, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The + * ends of the dimensions of the input tensor to be sliced. The length + * must be of rank(input0). + * * 3: strides, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The + * strides of the dimensions of the input tensor to be sliced. The + * length must be of rank(input0). The entries must be non-zero. + * * 4: begin_mask, an {@link ANEURALNETWORKS_INT32} scalar. If the ith bit + * of begin_mask is set, begin[i] is ignored and the fullest possible + * range in that dimension is used instead. + * * 5: end_mask, an {@link ANEURALNETWORKS_INT32} scalar. If the ith bit of + * end_mask is set, end[i] is ignored and the fullest possible range in + * that dimension is used instead. + * * 6: shrink_axis_mask, an {@link ANEURALNETWORKS_INT32} scalar. If the + * ith bit of shrink_axis_mask is set, the ith dimension specification + * shrinks the dimensionality by 1, taking on the value at index + * begin[i]. In this case, the ith specification must define a + * slice of size 1, e.g. begin[i] = x, end[i] = x + 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0 and rank (n - k), + * where k is the number of bits set in shrink_axis_mask. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 28. + */ + ANEURALNETWORKS_STRIDED_SLICE = 35, + + /** + * Element-wise subtraction of two tensors. + * + * Takes two input tensors of identical {@link OperandCode} and compatible + * dimensions. The output is the result of subtracting the second input + * tensor from the first one, optionally modified by an activation function. + * + * Two dimensions are compatible when: + * 1. they are equal, or + * 2. one of them is 1 + * + * The size of the output is the maximum size along each dimension of the + * input operands. It starts with the trailing dimensions, and works its way + * forward. + * + * Example: + * input1.dimension = {4, 1, 2} + * input2.dimension = {5, 4, 3, 1} + * output.dimension = {5, 4, 3, 2} + * + * Since API level 29, generic zero-sized input tensor is supported. Zero + * dimension is only compatible with 0 or 1. The size of the output + * dimension is zero if either of corresponding input dimension is zero. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} (since API level 29) + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, specifying the first input. + * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions + * as input0. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from inputs' scale and zeroPoint. + * + * Available since API level 28. + */ + ANEURALNETWORKS_SUB = 36, + + /** + * Transposes the input tensor, permuting the dimensions according to the + * perm tensor. + * + * The returned tensor's dimension i corresponds to the input dimension + * perm[i]. If perm is not given, it is set to (n-1...0), where n is the + * rank of the input tensor. Hence by default, this operation performs a + * regular matrix transpose on 2-D input Tensors. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} (since API level 29) + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be transposed. + * Since API level 29, this tensor may be zero-sized. + * * 1: An optional 1-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, + * the permutation of the dimensions of the input tensor. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 28. + */ + ANEURALNETWORKS_TRANSPOSE = 37, + + // Operations below are available since API level 29. + + /** + * Computes the absolute value of a tensor, element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_ABS = 38, + + /** + * Returns the index of the largest element along an axis. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: An n-D tensor specifying the input. Must be non-empty. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis to + * reduce across. Negative index is used to specify axis from the + * end (e.g. -1 for the last axis). Must be in the range [-n, n). + * + * Outputs: + * * 0: An (n - 1)-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor. + * + * Available since API level 29. + */ + // There is no underscore in ARG_MAX to avoid name conflict with + // the macro defined in libc/kernel/uapi/linux/limits.h. + ANEURALNETWORKS_ARGMAX = 39, + + /** + * Returns the index of the smallest element along an axis. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: An n-D tensor specifying the input. Must be non-empty. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis to + * reduce across. Negative index is used to specify axis from the + * end (e.g. -1 for the last axis). Must be in the range [-n, n). + * + * Outputs: + * * 0: An (n - 1)-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor. + * + * Available since API level 29. + */ + ANEURALNETWORKS_ARGMIN = 40, // See ARGMAX for naming discussion. + + /** + * Transform axis-aligned bounding box proposals using bounding box deltas. + * + * Given the positions of bounding box proposals and the corresponding + * bounding box deltas for each class, return the refined bounding box + * regions. The resulting bounding boxes are cliped against the edges of + * the image. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM} + * + * Inputs: + * * 0: A 2-D Tensor of shape [num_rois, 4], specifying the locations of the + * bounding box proposals, each line with format [x1, y1, x2, y2]. + * For tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, + * the zeroPoint must be 0 and the scale must be 0.125. Zero num_rois + * is supported for this tensor. + * * 1: A 2-D Tensor of shape [num_rois, num_classes * 4], specifying the + * bounding box delta for each region of interest and each class. The + * bounding box deltas are organized in the following order + * [dx, dy, dw, dh], where dx and dy is the relative correction factor + * for the center position of the bounding box with respect to the width + * and height, dw and dh is the log-scale relative correction factor + * for the width and height. For input0 of type + * {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, this tensor should be + * of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}. Zero num_rois is + * supported for this tensor. + * * 2: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [num_rois], specifying the batch index of each box. Boxes with + * the same batch index are grouped together. Zero num_rois is + * supported for this tensor. + * * 3: A 2-D Tensor of shape [batches, 2], specifying the information of + * each image in the batch, each line with format + * [image_height, image_width]. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0, with shape + * [num_rois, num_classes * 4], specifying the coordinates of each + * output bounding box for each class, with format [x1, y1, x2, y2]. + * For type of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the + * scale must be 0.125 and the zero point must be 0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_AXIS_ALIGNED_BBOX_TRANSFORM = 41, + + /** + * Performs a forward LSTM on the input followed by a backward LSTM. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: 3, either time-major or batch-major. + * + * All input and output tensors must be of the same type. + * + * + * Inputs: + * * 0: The input. + * A 3-D tensor of shape: + * If time-major: [max_time, batch_size, input_size] + * If batch-major: [batch_size, max_time, input_size] + * where "max_time" is the number of timesteps (sequence length), + * "batch_size" corresponds to the batching dimension, and + * "input_size" is the size of the input. + * * 1: The forward input-to-input weights. Optional. + * A 2-D tensor of shape [fw_num_units, input_size], where “fw_num_units” + * corresponds to the number of forward cell units. + * * 2: The forward input-to-forget weights. + * A 2-D tensor of shape [fw_num_units, input_size]. + * * 3: The forward input-to-cell weights. + * A 2-D tensor of shape [fw_num_units, input_size]. + * * 4: The forward input-to-output weights. + * A 2-D tensor of shape [fw_num_units, input_size]. + * * 5: The forward recurrent-to-input weights. Optional. + * A 2-D tensor of shape [fw_num_units, fw_output_size], where “fw_output_size” + * corresponds to either the number of cell units (i.e., fw_num_units), + * or the second dimension of the “fw_projection_weights”, if defined. + * * 6: The forward recurrent-to-forget weights. + * A 2-D tensor of shape [fw_num_units, fw_output_size]. + * * 7: The forward recurrent-to-cell weights. + * A 2-D tensor of shape [fw_num_units, fw_output_size]. + * * 8: The forward recurrent-to-output weights. + * A 2-D tensor of shape [fw_num_units, fw_output_size]. + * * 9: The forward cell-to-input weights. Optional. + * A 1-D tensor of shape [fw_num_units]. + * * 10: The forward cell-to-forget weights. Optional. + * A 1-D tensor of shape [fw_num_units]. + * * 11: The forward cell-to-output weights. Optional. + * A 1-D tensor of shape [fw_num_units]. + * * 12: The forward input gate bias. Optional. + * A 1-D tensor of shape [fw_num_units]. + * * 13: The forward forget gate bias. + * A 1-D tensor of shape [fw_num_units]. + * * 14: The forward cell gate bias. + * A 1-D tensor of shape [fw_num_units]. + * * 15: The forward output gate bias. + * A 1-D tensor of shape [fw_num_units]. + * * 16: The forward projection weights. Optional. + * A 2-D tensor of shape [fw_output_size, fw_num_units]. + * * 17: The forward projection bias. Optional. + * A 1-D tensor of shape [fw_output_size]. + * * 18: The backward input-to-input weights. Optional. + * A 2-D tensor of shape [bw_num_units, input_size], where “bw_num_units” + * corresponds to the number of backward cell units. + * * 19: The backward input-to-forget weights. + * A 2-D tensor of shape [bw_num_units, input_size]. + * * 20: The backward input-to-cell weights. + * A 2-D tensor of shape [bw_num_units, input_size]. + * * 21: The backward input-to-output weights. + * A 2-D tensor of shape [bw_num_units, input_size]. + * * 22: The backward recurrent-to-input weights. Optional. + * A 2-D tensor of shape [bw_num_units, bw_output_size], where “bw_output_size” + * corresponds to either the number of cell units (i.e., “bw_num_units”), + * or the second dimension of the “bw_projection_weights”, if defined. + * * 23: The backward recurrent-to-forget weights. + * A 2-D tensor of shape [bw_num_units, bw_output_size]. + * * 24: The backward recurrent-to-cell weights. + * A 2-D tensor of shape [bw_num_units, bw_output_size]. + * * 25: The backward recurrent-to-output weights. + * A 2-D tensor of shape [bw_num_units, bw_output_size]. + * * 26: The backward cell-to-input weights. Optional. + * A 1-D tensor of shape [bw_num_units]. + * * 27: The backward cell-to-forget weights. Optional. + * A 1-D tensor of shape [bw_num_units]. + * * 28: The backward cell-to-output weights. Optional. + * A 1-D tensor of shape [bw_num_units]. + * * 29: The backward input gate bias. Optional. + * A 1-D tensor of shape [bw_num_units]. + * * 30: The backward forget gate bias. + * A 1-D tensor of shape [bw_num_units]. + * * 31: The backward cell gate bias. + * A 1-D tensor of shape [bw_num_units]. + * * 32: The backward output gate bias. + * A 1-D tensor of shape [bw_num_units]. + * * 33: The backward projection weights. Optional. + * A 2-D tensor of shape [bw_output_size, bw_num_units]. + * * 34: The backward projection bias. Optional. + * A 1-D tensor of shape [bw_output_size]. + * * 35: The forward input activation state. + * A 2-D tensor of shape [batch_size, bw_output_size]. + * * 36: The forward input cell state. + * A 2-D tensor of shape [batch_size, bw_num_units]. + * * 37: The backward input activation state. + * A 2-D tensor of shape [batch_size, bw_output_size]. + * * 38: The backward input cell state. + * A 2-D tensor of shape [batch_size, bw_num_units]. + * * 39: The auxiliary input. Optional. + * A 3-D tensor of shape [max_time, batch_size, input_size], where “batch_size” + * corresponds to the batching dimension, and “input_size” is the size + * of the input. + * * 40: The forward auxiliary input-to-input weights. Optional. + * A 2-D tensor of shape [fw_num_units, input_size]. + * * 41: The forward auxiliary input-to-forget weights. Optional. + * A 2-D tensor of shape [fw_num_units, input_size]. + * * 42: The forward auxiliary input-to-cell weights. Optional. + * A 2-D tensor of shape [fw_num_units, input_size]. + * * 43: The forward auxiliary input-to-output weights. Optional. + * A 2-D tensor of shape [fw_num_units, input_size]. + * * 44: The backward auxiliary input-to-input weights. Optional. + * A 2-D tensor of shape [bw_num_units, input_size]. + * * 45: The backward auxiliary input-to-forget weights. Optional. + * A 2-D tensor of shape [bw_num_units, input_size]. + * * 46: The backward auxiliary input-to-cell weights. Optional. + * A 2-D tensor of shape [bw_num_units, input_size]. + * * 47: The backward auxiliary input-to-output weights. Optional. + * A 2-D tensor of shape [bw_num_units, input_size]. + * * 48: The activation function. + * A value indicating the activation function: + *
    + *
  • 0: None; + *
  • 1: Relu; + *
  • 3: Relu6; + *
  • 4: Tanh; + *
  • 6: Sigmoid. + *
+ * * 49: The clipping threshold for the cell state, such + * that values are bound within [-cell_clip, cell_clip]. If set to 0.0 + * then clipping is disabled. + * If all the input tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32}, + * this scalar must be of the type {@link ANEURALNETWORKS_FLOAT32}, + * otherwise if all the input tensors have the type {@link ANEURALNETWORKS_TENSOR_FLOAT16}, + * this scalar must be of type {@link ANEURALNETWORKS_FLOAT16}. + * * 50: The clipping threshold for the output from the + * projection layer, such that values are bound within + * [-proj_clip, proj_clip]. If set to 0.0 then clipping is disabled. + * If all the input tensors have type {@link ANEURALNETWORKS_TENSOR_FLOAT32}, + * this scalar must be of the type {@link ANEURALNETWORKS_FLOAT32}, + * otherwise if all the input tensors have the type {@link ANEURALNETWORKS_TENSOR_FLOAT16}, + * this scalar must be of type {@link ANEURALNETWORKS_FLOAT16}. + * * 51: merge_outputs + * An {@link ANEURALNETWORKS_BOOL} scalar specifying if the outputs + * from forward and backward cells should be merged. + * * 52: time_major + * An {@link ANEURALNETWORKS_BOOL} scalar specifying the shape format + * of input and output tensors. + * * 53: The forward input layer normalization weights. Optional. + * A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs + * to activation at input gate. + * * 54: The forward forget layer normalization weights. Optional. + * A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs + * to activation at forget gate. + * * 55: The forward cell layer normalization weights. Optional. + * A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs + * to activation at cell gate. + * * 56: The forward output layer normalization weights. Optional. + * A 1-D tensor of shape [fw_num_units]. Used to rescale normalized inputs + * to activation at output gate. + * * 57: The backward input layer normalization weights. Optional. + * A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs + * to activation at input gate. + * * 58: The backward forget layer normalization weights. Optional. + * A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs + * to activation at forget gate. + * * 59: The backward cell layer normalization weights. Optional. + * A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs + * to activation at cell gate. + * * 60: The backward output layer normalization weights. Optional. + * A 1-D tensor of shape [bw_num_units]. Used to rescale normalized inputs + * to activation at output gate. + * + * Outputs: + * * 0: The forward output. + * A 3-D tensor of shape: + * If time-major and not merge_outputs: + * [max_time, batch_size, fw_output_size] + * If time-major and merge_outputs: + * [max_time, batch_size, fw_output_size + bw_output_size] + * If batch-major and not merge_outputs: + * [batch_size, max_time, fw_output_size] + * If batch-major and merge_outputs: + * [batch_size, max_time, fw_output_size + bw_output_size] + * * 1: The backward output. Unused if merge_outputs is true. + * A 3-D tensor of shape: + * If time-major: [max_time, batch_size, bw_output_size] + * If batch-major: [batch_size, max_time, bw_output_size] + * + * Available since API level 29. + * + * Important: As of API level 29, there is no way to get the output state tensors out and NNAPI + * does not maintain internal states. This operator does not support the usage pattern in which + * multiple cells are chained and state tensors are propagated. + */ + ANEURALNETWORKS_BIDIRECTIONAL_SEQUENCE_LSTM = 42, + + /** + * A recurrent neural network layer that applies a basic RNN cell to a + * sequence of inputs in forward and backward directions. + * + * This Op unrolls the input along the sequence dimension, and implements + * the following operation for each element in the sequence s = + * 1...sequence_length: + * fw_outputs[s] = fw_state = activation(inputs[s] * fw_input_weights’ + + * fw_state * fw_recurrent_weights’ + fw_bias) + * + * And for each element in sequence t = sequence_length : 1 + * bw_outputs[t] = bw_state = activation(inputs[t] * bw_input_weights’ + + * bw_state * bw_recurrent_weights’ + bw_bias) + * + * Where: + * * “{fw,bw}_input_weights” is a weight matrix that multiplies the inputs; + * * “{fw,bw}_recurrent_weights” is a weight matrix that multiplies the + * current “state” which itself is the output from the previous time step + * computation; + * * “{fw,bw}_bias” is a bias vector (added to each output vector in the + * batch); + * * “activation” is the function passed as the “fused_activation_function” + * argument (if not “NONE”). + * + * The op also supports an auxiliary input. Regular cell feeds one input + * into the two RNN cells in the following way: + * + * INPUT (INPUT_REVERSED) + * | | + * --------------------- + * | FW_RNN BW_RNN | + * --------------------- + * | | + * FW_OUT BW_OUT + * + * An op with an auxiliary input takes two inputs and feeds them into the + * RNN cells in the following way: + * + * AUX_INPUT (AUX_INPUT_REVERSED) + * | | + * INPUT | (INPUT_R'D.)| + * | | | | + * ----------------------- + * | \ / \ / | + * | FW_RNN BW_RNN | + * ----------------------- + * | | + * FW_OUT BW_OUT + * + * While stacking this op on top of itself, this allows to connect both + * forward and backward outputs from previous cell to the next cell's + * inputs. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * The input tensors must all be the same type. + * + * Inputs: + * * 0: input. + * A 3-D tensor. The shape is defined by the input 6 (timeMajor). If + * it is set to true, then the input has a shape [maxTime, batchSize, + * inputSize], otherwise the input has a shape [batchSize, maxTime, + * inputSize]. + * * 1: fwWeights. + * A 2-D tensor of shape [fwNumUnits, inputSize]. + * * 2: fwRecurrentWeights. + * A 2-D tensor of shape [fwNumUnits, fwNumUnits]. + * * 3: fwBias. + * A 1-D tensor of shape [fwNumUnits]. + * * 4: fwHiddenState. + * A 2-D tensor of shape [batchSize, fwNumUnits]. Specifies a hidden + * state input for the first time step of the computation. + * * 5: bwWeights. + * A 2-D tensor of shape [bwNumUnits, inputSize]. + * * 6: bwRecurrentWeights. + * A 2-D tensor of shape [bwNumUnits, bwNumUnits]. + * * 7: bwBias. + * A 1-D tensor of shape [bwNumUnits]. + * * 8: bwHiddenState + * A 2-D tensor of shape [batchSize, bwNumUnits]. Specifies a hidden + * state input for the first time step of the computation. + * * 9: auxInput. + * A 3-D tensor. The shape is the same as of the input 0. + * * 10:fwAuxWeights. + * A 2-D tensor of shape [fwNumUnits, inputSize]. + * * 11:bwAuxWeights. + * A 2-D tensor of shape [bwNumUnits, inputSize]. + * * 12:fusedActivationFunction. + * A {@link FuseCode} value indicating the activation function. If + * “NONE” is specified then it results in a linear activation. + * * 13:timeMajor + * An {@link ANEURALNETWORKS_BOOL} scalar specifying the shape format + * of input and output tensors. + * * 14:mergeOutputs + * An {@link ANEURALNETWORKS_BOOL} scalar specifying if the outputs + * from forward and backward cells are separate (if set to false) or + * concatenated (if set to true). + * Outputs: + * * 0: fwOutput. + * A 3-D tensor. The first two dimensions of the shape are defined by + * the input 6 (timeMajor) and the third dimension is defined by the + * input 14 (mergeOutputs). If timeMajor is set to true, then the first + * two dimensions are [maxTime, batchSize], otherwise they are set to + * [batchSize, maxTime]. If mergeOutputs is set to true, then the third + * dimension is equal to (fwNumUnits + bwNumUnits), otherwise it is set + * to fwNumUnits. + * * 1: bwOutput. + * A 3-D tensor. If the input 14 (mergeOutputs) is set to true, then + * this tensor is not produced. The shape is defined by the input 6 + * (timeMajor). If it is set to true, then the shape is set to + * [maxTime, batchSize, bwNumUnits], otherwise the shape is set to + * [batchSize, maxTime, bwNumUnits]. + * + * Available since API level 29. + * + * Important: As of API level 29, there is no way to get the output state tensors out and NNAPI + * does not maintain internal states. This operator does not support the usage pattern in which + * multiple cells are chained and state tensors are propagated. + */ + ANEURALNETWORKS_BIDIRECTIONAL_SEQUENCE_RNN = 43, + + /** + * Greedily selects a subset of bounding boxes in descending order of score. + * + * This op applies NMS algorithm to each class. In each loop of execution, + * the box with maximum score gets selected and removed from the pending set. + * The scores of the rest of boxes are lowered according to the + * intersection-over-union (IOU) overlapping with the previously selected + * boxes and a specified NMS kernel method. Any boxes with score less + * than a threshold are removed from the pending set. + * + * Three NMS kernels are supported: + * * Hard: score_new = score_old * (1 if IoU < threshold else 0) + * * Linear: score_new = score_old * (1 if IoU < threshold else 1 - IoU) + * * Gaussian: score_new = score_old * exp(- IoU^2 / sigma) + * + * Axis-aligned bounding boxes are represented by its upper-left corner + * coordinate (x1,y1) and lower-right corner coordinate (x2,y2). A valid + * bounding box should satisfy x1 <= x2 and y1 <= y2. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Inputs: + * * 0: A 2-D Tensor of shape [num_rois, num_classes], specifying the score + * of each bounding box proposal. The boxes are grouped by batches in the + * first dimension. Zero num_rois is supported for this tensor. + * * 1: A 2-D Tensor specifying the bounding boxes of shape + * [num_rois, num_classes * 4], organized in the order [x1, y1, x2, y2]. + * The boxes are grouped by batches in the first dimension. The sequential + * order of the boxes corresponds with input0. For input0 of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this tensor should be of + * {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, with zeroPoint of 0 and + * scale of 0.125. Zero num_rois is supported for this tensor. + * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [num_rois], specifying the batch index of each box. Boxes with + * the same batch index are grouped together. + * * 3: An {@link ANEURALNETWORKS_FLOAT32} scalar, score_threshold. Boxes + * with scores lower than the threshold are filtered before sending + * to the NMS algorithm. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the maximum + * number of selected bounding boxes for each image. Set to a negative + * value for unlimited number of output bounding boxes. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the NMS + * kernel method, options are 0:hard, 1:linear, 2:gaussian. + * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the IoU + * threshold in hard and linear NMS kernel. This field is ignored if + * gaussian kernel is selected. + * * 7: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the sigma in + * gaussian NMS kernel. This field is ignored if gaussian kernel is + * not selected. + * * 8: An {@link ANEURALNETWORKS_FLOAT32} scalar, nms_score_threshold. + * Boxes with scores lower than the threshold are dropped during the + * score updating phase in soft NMS. + * + * Outputs: + * * 0: A 1-D Tensor of the same {@link OperandCode} as input0, with shape + * [num_output_rois], specifying the score of each output box. The boxes + * are grouped by batches, but the sequential order in each batch is not + * guaranteed. For type of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the scale and zero point must be the same as input0. + * * 1: A 2-D Tensor of the same {@link OperandCode} as input1, with shape + * [num_output_rois, 4], specifying the coordinates of each + * output bounding box with the same format as input1. The sequential + * order of the boxes corresponds with output0. For type of + * {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the scale must be + * 0.125 and the zero point must be 0. + * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [num_output_rois], specifying the class of each output box. The + * sequential order of the boxes corresponds with output0. + * * 3: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [num_output_rois], specifying the batch index of each box. Boxes + * with the same batch index are grouped together. + * + * Available since API level 29. + */ + ANEURALNETWORKS_BOX_WITH_NMS_LIMIT = 44, + + /** + * Casts a tensor to a new type. + * + * This operation ignores the scale and zeroPoint of quanized tensors, + * e.g. it treats a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} input + * as a tensor of uint8 values. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: A tensor with the same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_CAST = 45, + + /** + * Shuffle the channels of the input tensor. + * + * Given an input tensor and a integer value of num_groups, CHANNEL_SHUFFLE + * divide the channel dimension into num_groups groups, and reorganize the + * channels by grouping channels with the same index in each group. + * + * Along the channel dimension, the output is calculated using this formula: + * + * output_channel[k * num_groups + g] = input_channel[g * group_size + k] + * + * where group_size = num_channels / num_groups + * + * The number of channels must be divisible by num_groups. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be shuffled. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of + * groups. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the dimension + * channel shuffle would be performed on. Negative index is used to + * specify axis from the end (e.g. -1 for the last axis). Must be in + * the range [-n, n). + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} and same shape as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_CHANNEL_SHUFFLE = 46, + + /** + * Apply postprocessing steps to bounding box detections. + * + * Bounding box detections are generated by applying transformation on a set + * of predefined anchors with the bounding box deltas from bounding box + * regression. A final step of hard NMS is applied to limit the number of + * returned boxes. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Inputs: + * * 0: A 3-D Tensor of shape [batches, num_anchors, num_classes], specifying + * the score of each anchor with each class. Class 0 for each + * [batches, num_anchors, 0] is background and will be ignored. + * * 1: A 3-D Tensor of shape [batches, num_anchors, length_box_encoding], with + * the first four values in length_box_encoding specifying the bounding + * box deltas. The box deltas are encoded in the order of [dy, dx, dh, dw], + * where dy and dx is the linear-scale relative correction factor for the + * center position of the bounding box with respect to the width and height, + * dh and dw is the log-scale relative correction factor for the width and + * height. All the entries in length_box_encoding beyond the first four + * values are ignored in this operation. + * * 2: A 2-D Tensor of shape [num_anchors, 4], specifying the shape of each + * predefined anchor, with format [ctr_y, ctr_x, h, w], where ctr_y and + * ctr_x are the center position of the box, and h and w are the height + * and the width. + * * 3: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling + * factor for dy in bounding box deltas. + * * 4: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling + * factor for dx in bounding box deltas. + * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling + * factor for dh in bounding box deltas. + * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the scaling + * factor for dw in bounding box deltas. + * * 7: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to use regular + * multi-class NMS algorithm that do NMS separately for each class, + * set to false for a faster algorithm that only do one single NMS + * using the highest class score.. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, max_num_detections, specifying + * the maximum number of boxes for the output. Boxes with the lowest + * scores are discarded to meet the limit. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, only used when input7 is + * set to false, specifying the maximum number of classes per detection. + * * 10: An {@link ANEURALNETWORKS_INT32} scalar, only used when input7 is + * set to true, specifying the maximum number of detections when + * applying NMS algorithm for each single class. + * * 11: A scalar, score_threshold. Boxes with scores lower than the + * threshold are filtered before sending to the NMS algorithm. The + * scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is of + * {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} if input0 is of + * {@link ANEURALNETWORKS_TENSOR_FLOAT32}. + * * 12: A scalar, specifying the IoU threshold for hard NMS. The scalar + * must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is of + * {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} if input0 is of + * {@link ANEURALNETWORKS_TENSOR_FLOAT32}. + * * 13: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to include + * background class in the list of label map for the output, set + * to false to not include the background. When the background + * class is included, it has label 0 and the output classes start + * at 1 in the label map, otherwise, the output classes start at 0. + * + * Outputs: + * * 0: A 2-D tensor of the same {@link OperandCode} as input0, with shape + * [batches, max_num_detections], specifying the score of each output + * detections. + * * 1: A 3-D tensor of shape [batches, max_num_detections, 4], specifying the + * coordinates of each output bounding box, with format + * [y1, x1, y2, x2]. + * * 2: A 2-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [batches, max_num_detections], specifying the class label for each + * output detection. + * * 3: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape [batches], + * specifying the number of valid output detections for each batch. + * + * Available since API level 29. + */ + ANEURALNETWORKS_DETECTION_POSTPROCESSING = 47, + + /** + * For input tensors x and y, computes x == y elementwise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and dimensions compatible + * with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_EQUAL = 48, + + /** + * Computes exponential of x element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_EXP = 49, + + /** + * Inserts a dimension of 1 into a tensor's shape. + * + * Given a tensor input, this operation inserts a dimension of 1 at the + * given dimension index of input's shape. The dimension index starts at + * zero; if you specify a negative dimension index, it is counted backward + * from the end. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: An n-D tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the dimension + * index to expand. Must be in the range [-(n + 1), (n + 1)). + * + * Outputs: + * * 0: An (n + 1)-D tensor with the same {@link OperandCode} and data as + * input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_EXPAND_DIMS = 50, + + /** + * Gathers values along an axis. + * + * Produces an output tensor with shape + * input0.dimension[:axis] + indices.dimension + input0.dimension[axis + 1:] + * where: + * # Vector indices (output is rank(input0)). + * output[a_0, ..., a_n, i, b_0, ..., b_n] = + * input0[a_0, ..., a_n, indices[i], b_0, ..., b_n] + * + * # Higher rank indices (output is rank(input0) + rank(indices) - 1). + * output[a_0, ..., a_n, i, ..., j, b_0, ... b_n] = + * input0[a_0, ..., a_n, indices[i, ..., j], b_0, ..., b_n] + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: An n-D tensor from which to gather values. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis. + * Negative index is used to specify axis from the end + * (e.g. -1 for the last axis). Must be in the range [-n, n). + * * 2: A k-D tensor {@link ANEURALNETWORKS_TENSOR_INT32} of indices. + * The values must be in the bounds of the corresponding dimensions + * of input0. + * + * Outputs: + * * 0: An (n + k - 1)-D tensor with the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_GATHER = 51, + + /** + * Generate aixs-aligned bounding box proposals. + * + * Bounding box proposals are generated by applying transformation on a set + * of predefined anchors with the bounding box deltas from bounding box + * regression. A final step of hard NMS is applied to limit the number of + * returned boxes. + * + * Axis-aligned bounding boxes are represented by its upper-left corner + * coordinate (x1,y1) and lower-right corner coordinate (x2,y2). A valid + * bounding box should satisfy x1 <= x2 and y1 <= y2. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Inputs: + * * 0: A 4-D Tensor specifying the score of each anchor at each + * location. With "NHWC" data layout, the tensor shape is + * [batches, height, width, num_anchors]. With "NCHW" data layout, + * the tensor shape is [batches, num_anchors, height, width]. + * * 1: A 4-D Tensor specifying the bounding box deltas. With "NHWC" data + * layout, the tensor shape is [batches, height, width, num_anchors * 4]. + * With "NCHW" data layout, the tensor shape is + * [batches, num_anchors * 4, height, width]. The box deltas are encoded + * in the order of [dx, dy, dw, dh], where dx and dy is the linear-scale + * relative correction factor for the center position of the bounding box + * with respect to the width and height, dw and dh is the log-scale + * relative correction factor for the width and height. The last + * dimensions is the channel dimension. + * * 2: A 2-D Tensor of shape [num_anchors, 4], specifying the shape of each + * predefined anchor, with format [x1, y1, x2, y2]. For input0 of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this tensor should be of + * {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM}, with scale of 0.125. + * * 3: A 2-D Tensor of shape [batches, 2], specifying the size of + * each image in the batch, with format [image_height, image_width]. + * For input0 of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this + * tensor should be of {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM}, with + * scale of 0.125. + * * 4: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio + * from the height of original image to the height of feature map. + * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio + * from the width of original image to the width of feature map. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the maximum + * number of boxes before going into the hard NMS algorithm. Boxes + * with the lowest scores are discarded to meet the limit. Set to + * a non-positive value for unlimited number. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the maximum + * number of boxes returning from the hard NMS algorithm. Boxes + * with the lowest scores are discarded to meet the limit. Set to + * a non-positive value for unlimited number. + * * 8: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the IoU + * threshold for hard NMS. + * * 9: An {@link ANEURALNETWORKS_FLOAT32} scalar, min_size. Boxes with + * height or width lower than the absolute threshold are filtered out. + * * 10: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and input1. Set to false for NHWC. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0, of shape + * [num_output_rois], specifying the score of each output box. + * The boxes are grouped by batches, but the sequential order in + * each batch is not guaranteed. For type of + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the scale and zero + * point must be the same as input0. + * * 1: A tensor of the same {@link OperandCode} as input3, of shape + * [num_output_rois, 4], specifying the coordinates of each output + * bounding box for each class, with format [x1, y1, x2, y2]. + * The sequential order of the boxes corresponds with output0. + * For type of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the + * scale must be 0.125 and the zero point must be 0. + * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [num_output_rois], specifying the batch index of each box. Boxes + * with the same batch index are grouped together. + * + * Available since API level 29. + */ + ANEURALNETWORKS_GENERATE_PROPOSALS = 52, + + /** + * For input tensors x and y, computes x > y elementwise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and dimensions compatible + * with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_GREATER = 53, + /** + * For input tensors x and y, computes x >= y elementwise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and dimensions compatible + * with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_GREATER_EQUAL = 54, + + /** + * Performs a grouped 2-D convolution operation. + * + * Given an input tensor of shape [batches, height, width, depth_in] and a + * filter tensor of shape [depth_out, filter_height, filter_width, depth_group] + * containing depth_out convolutional filters of depth depth_group, GROUPED_CONV + * applies a group of different filters to each input channel group, then + * concatenates the results together. + * + * Specifically, the input channels are divided into num_groups groups, each with + * depth depth_group, i.e. depth_in = num_groups * depth_group. The convolutional + * filters are also divided into num_groups groups, i.e. depth_out is divisible + * by num_groups. GROUPED_CONV applies each group of filters to the corresponding + * input channel group, and the result are concatenated together. + * + * The output dimensions are functions of the filter dimensions, stride, and + * padding. + * + * The values in the output tensor are computed as: + * + * output[b, i, j, g * channel_multiplier + q] = + * sum_{di, dj, dk} ( + * input[b, strides[1] * i + di, strides[2] * j + dj, + * g * depth_group + dk] * + * filter[g * channel_multiplier + q, di, dj, dk] + * ) + bias[channel] + * + * where channel_multiplier = depth_out / num_groups + * + * Supported tensor {@link OperandCode} configurations: + * * 16 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias. + * + * * 32 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias. + * + * * Quantized: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to + * * * input.scale * filter.scale). + * + * * Quantized with symmetric per channel quantization for the filter: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output. + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0, + * * * each value scaling is separate and equal to input.scale * filter.scales[channel]). + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * + * Both explicit padding and implicit padding are supported. + * + * Inputs (explicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input, where depth_in = num_groups * depth_group. + * * 1: A 4-D tensor, of shape + * [depth_out, filter_height, filter_width, depth_group], specifying + * the filter, where depth_out must be divisible by num_groups. For + * tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} + * the channel dimension (channelDim at + * {@link ANeuralNetworksSymmPerChannelQuantParams}) must be set to 0. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or + * {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same + * type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint + * of 0 and bias_scale == input_scale * filter_scale. For filter tensor + * of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias + * should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of + * 0 and bias_scale of 0. The actual scale of each value 'i' is equal to + * bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the left, in the ‘width’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the right, in the ‘width’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the top, in the ‘height’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the bottom, in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of + groups. + * * 10: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 11: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and output0. Set to false for NHWC. + * + * Inputs (implicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input, where depth_in = num_groups * depth_group. + * * 1: A 4-D tensor, of shape + * [depth_out, filter_height, filter_width, depth_group], specifying + * the filter, where depth_out must be divisible by num_groups. For + * tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} + * the channel dimension (ANeuralNetworksSymmPerChannelQuantParams::channelDim) + * must be set to 0. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or + * {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias must be of the same + * type. For filter tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the bias should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint + * of 0 and bias_scale == input_scale * filter_scale. For filter tensor + * of {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias + * should be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of + * 0 and bias_scale of 0. The actual scale of each value 'i' is equal to + * bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit + * padding scheme, has to be one of the + * {@link PaddingCode} values. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of + * groups. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 8: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and output0. Set to false for NHWC. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, out_height, out_width, depth_out]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from inputs' scale and zeroPoint. + * + * Available since API level 29. + */ + ANEURALNETWORKS_GROUPED_CONV_2D = 55, + + /** + * Localize the maximum keypoints from heatmaps. + * + * This operation approximates the accurate maximum keypoint scores and + * indices after bicubic upscaling by using Taylor expansion up to the + * quadratic term. + * + * The bounding box is represented by its upper-left corner coordinate + * (x1,y1) and lower-right corner coordinate (x2,y2) in the original image. + * A valid bounding box should satisfy x1 <= x2 and y1 <= y2. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * + * Inputs: + * * 0: A 4-D Tensor of shape + * [num_boxes, heatmap_size, heatmap_size, num_keypoints], + * specifying the heatmaps, the height and width of heatmaps should + * be the same, and must be greater than or equal to 2. + * * 1: A 2-D Tensor of shape [num_boxes, 4], specifying the bounding boxes, + * each with format [x1, y1, x2, y2]. For input0 of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, this tensor should + * be of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, with zeroPoint + * of 0 and scale of 0.125. + * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0. Set to false for NHWC. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0, with shape + * [num_boxes, num_keypoints], specifying score of the keypoints. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from input0 scale and zeroPoint. + * * 1: A tensor of the same {@link OperandCode} as input1, with shape + * [num_boxes, num_keypoints, 2], specifying the location of + * the keypoints, the second dimension is organized as + * [keypoint_x, keypoint_y]. + * For type of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, the + * scale must be 0.125 and the zero point must be 0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_HEATMAP_MAX_KEYPOINT = 56, + + /** + * Applies instance normalization to the input tensor. + * + * The values in the output tensor are computed as: + * + * output[b, h, w, c] = + * (input[b, h, w, c] - mean[b, c]) * gamma / + * sqrt(var[b, c] + epsilon) + beta + * + * Where the mean and variance are computed across the spatial dimensions: + * + * mean[b, c] = + * sum_{h, w}(input[b, h, w, c]) / sum(1) + * + * var[b, c] = + * sum_{h, w}(pow(input[b, h, w, c] - mean[b, c], 2)) / sum(1) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be normalized. + * * 1: A scalar, specifying gamma, the scale applied to the normalized + * tensor. The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if + * input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} if input0 is of + * {@link ANEURALNETWORKS_TENSOR_FLOAT32}. + * * 2: A scalar, specifying beta, the offset applied to the normalized + * tensor. The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if + * input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} if input0 is of + * {@link ANEURALNETWORKS_TENSOR_FLOAT32}. + * * 3: A scalar, specifying epsilon, the small value added to variance to + * avoid dividing by zero. The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if + * input0 is of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} if input0 is of + * {@link ANEURALNETWORKS_TENSOR_FLOAT32}. + * * 4: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and output0. Set to false for NHWC. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} and same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_INSTANCE_NORMALIZATION = 57, + + /** + * For input tensors x and y, computes x < y elementwise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and dimensions compatible + * with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_LESS = 58, + + /** + * For input tensors x and y, computes x <= y elementwise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and dimensions compatible + * with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_LESS_EQUAL = 59, + + /** + * Computes natural logarithm of x element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_LOG = 60, + + /** + * Returns the truth value of x AND y element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * * 1: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8} and dimensions + * compatible with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_LOGICAL_AND = 61, + + /** + * Computes the truth value of NOT x element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_LOGICAL_NOT = 62, + + /** + * Returns the truth value of x OR y element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * * 1: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8} and dimensions + * compatible with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_LOGICAL_OR = 63, + + /** + * Computes the log softmax activations given logits. + * + * The output is calculated using this formula: + * + * output = logits * beta - log(reduce_sum(exp(logits * beta), axis)) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor specifying the input logits. + * * 1: A scalar, specifying the positive scaling factor for the exponent, + * beta. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the beta + * value must be of {@link ANEURALNETWORKS_FLOAT16}. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the beta + * value must be of {@link ANEURALNETWORKS_FLOAT32}. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis to + * reduce across. Negative index is used to specify axis from the + * end (e.g. -1 for the last axis). Must be in the range [-n, n). + * + * Outputs: + * * 0: The output tensor of the same {@link OperandCode} and shape as + * input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_LOG_SOFTMAX = 64, + + /** + * Returns the element-wise maximum of two tensors. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and compatible dimensions + * with input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scales and zeroPoint can be different from input0 scale and zeroPoint. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from inputs' scale and zeroPoint. + * + * Available since API level 29. + */ + ANEURALNETWORKS_MAXIMUM = 65, + + /** + * Returns the element-wise minimum of two tensors. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and compatible dimensions + * with input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scales and zeroPoint can be different from input0 scale and zeroPoint. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from inputs' scale and zeroPoint. + * + * Available since API level 29. + */ + ANEURALNETWORKS_MINIMUM = 66, + + /** + * Computes numerical negative value element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_NEG = 67, + + /** + * For input tensors x and y, computes x != y elementwise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * This operation supports broadcasting. + * + * Inputs: + * * 0: A tensor. + * * 1: A tensor of the same {@link OperandCode} and dimensions compatible + * with input0. + * + * Outputs: + * * 0: A tensor of {@link ANEURALNETWORKS_TENSOR_BOOL8}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_NOT_EQUAL = 68, + + /** + * Pads a tensor with the given constant value according to the specified + * paddings. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor, specifying the tensor to be padded. + * * 1: A 2-D Tensor of {@link ANEURALNETWORKS_TENSOR_INT32}, the paddings + * for each spatial dimension of the input tensor. The shape of the + * tensor must be {rank(input0), 2}. + * padding[i, 0] specifies the number of elements to be padded in the + * front of dimension i. + * padding[i, 1] specifies the number of elements to be padded after + * the end of dimension i. + * * 2: An scalar specifying the value to use for padding input0. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the + * pad value must be of {@link ANEURALNETWORKS_FLOAT16}. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_FLOAT32}, the + * pad value must be of {@link ANEURALNETWORKS_FLOAT32}. + * For input tensor of {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * the pad value must be of {@link ANEURALNETWORKS_INT32}. The + * scale and zeroPoint are assumed to be the same as in input0. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. The + * output tensor has the same rank as input0, and each + * dimension of the output tensor has the same size as the + * corresponding dimension of the input tensor plus the size + * of the padding: + * output0.dimension[i] = + * padding[i, 0] + input0.dimension[i] + padding[i, 1] + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_PAD_V2 = 69, + + /** + * Computes the power of one value to another. + * + * Given a tensor base and a tensor exponent, this operation computes + * base^exponent elementwise. + * + * This operations supports broadcasting. The size of the output is the + * maximum size along each dimension of the input operands. It starts with + * the trailing dimensions, and works its way forward. + * + * For example: + * base.dimension = {4, 1, 2} + * exponent.dimension = {5, 4, 3, 1} + * output.dimension = {5, 4, 3, 2} + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: A tensor specifying the base. + * * 1: A tensor specifying the exponent. + * + * Outputs: + * * 0: An output tensor. + * + * Available since API level 29. + */ + ANEURALNETWORKS_POW = 70, + + /** + * Parametric Rectified Linear Unit. + * + * It follows: f(x) = alpha * x for x < 0, f(x) = x for x >= 0, where alpha + * is a learned array with the same {@link OperandCode} and compatible + * dimensions as input x. + * + * Two dimensions are compatible when: + * 1. they are equal, or + * 2. one of them is 1 + * + * The size of the output is the maximum size along each dimension of the + * input operands. It starts with the trailing dimensions, and works its way + * forward. + * + * Example: + * input.dimension = {4, 1, 2} + * alpha.dimension = {5, 4, 3, 1} + * output.dimension = {5, 4, 3, 2} + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: A tensor, specifying the input. + * * 1: A tensor of the same {@link OperandCode}, and compatible dimensions + * as input0, specifying the alpha. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be diffent from the input0 scale and zeroPoint. + * + * Available since API level 29. + */ + ANEURALNETWORKS_PRELU = 71, + + /** + * Quantizes the input tensor. + * + * The formula is: + * + * output = max(0, min(255, round(input / scale) + zeroPoint) + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: A tensor, may be zero-sized. + * + * Outputs: + * * 0: The output tensor of same shape as input0, but with + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}. + * + * Available since API level 29. + */ + ANEURALNETWORKS_QUANTIZE = 72, + + /** + * A version of quantized LSTM, using 16 bit quantization for internal + * state. + * + * There is no projection layer, so cell state size is equal to the output + * size. + * + * Inputs: + * * 0: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [numBatches, inputSize] specifying the input to the LSTM + * cell. Tensor is quantized with a fixed quantization range of + * [-1, 127/128] (scale = 1/128, zeroPoint = 128). + * * 1: The input-to-input weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, inputSize] specifying input-to-input part of + * weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 2: The input-to-forget weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, inputSize] specifying input-to-forget part of + * weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 3: The input-to-cell weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, inputSize] specifying input-to-cell part of + * weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 4: The input-to-output weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, inputSize] specifying input-to-output part of + * weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 5: The recurrent-to-input weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, outputSize] specifying recurrent-to-input part + * of weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 6: The recurrent-to-forget weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, outputSize] specifying recurrent-to-forget + * part of weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 7: The recurrent-to-cell weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, outputSize] specifying recurrent-to-cell part + * of weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 8: The recurrent-to-output weights. + * A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [outputSize, outputSize] specifying recurrent-to-output + * part of weights for fully-connected layer inside the LSTM cell. + * Quantization zero point and scale must be the same across all the + * weights. + * * 9: The input gate bias. + * A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape + * [outputSize] specifying the bias for the fully-connected layer + * inside the LSTM cell. Bias is quantized with scale being a product + * of input and weights scales and zeroPoint equal to 0. + * * 10:The forget gate bias. + * A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape + * [outputSize] specifying the bias for the fully-connected layer + * inside the LSTM cell. Bias is quantized with scale being a product + * of input and weights scales and zeroPoint equal to 0. + * * 11:The cell bias. + * A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape + * [outputSize] specifying the bias for the fully-connected layer + * inside the LSTM cell. Bias is quantized with scale being a product + * of input and weights scales and zeroPoint equal to 0. + * * 12:The output gate bias. + * A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} and shape + * [outputSize] specifying the bias for the fully-connected layer + * inside the LSTM cell. Bias is quantized with scale being a product + * of input and weights scales and zeroPoint equal to 0. + * * 13: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM} + * and shape [numBatches, outputSize] specifying the cell state from the + * previous time step of the LSTM cell. It is quantized using a + * quantization range of [-2^4, 2^4 * 32767/32768] (scale = 2^4 / + * 32768, zeroPoint = 0). + * * 14: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [numBathes, outputSize] specifying the output of the LSTM + * cell from previous time-step. Tensor is quantized with a fixed + * quantization range of [-1, 127/128] (scale = 1/128, zeroPoint = + * 128). + * + * + * Outputs: + * * 0: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT16_SYMM} + * and shape [numBatches, outputSize] which contains a cell state from + * the current time step. Tensor is quantized using a quantization + * range of [-2^4, 2^4 * 32767/32768] (scale = 2^4 / 32768, zeroPoint = + * 0). + * * 1: A 2-D tensor of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * and shape [numBathes, outputSize] which contains the output value. + * Tensor is quantized with a fixed quantization range of [-1, 127/128] + * (scale = 1/128, zeroPoint = 128). + */ + ANEURALNETWORKS_QUANTIZED_16BIT_LSTM = 73, + + /** + * Draws samples from a multinomial distribution. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Inputs: + * * 0: A 2-D tensor with shape [batches, classes], specifying the + * unnormalized log-probabilities for all classes. + * * 1: A scalar {@link ANEURALNETWORKS_INT32}, specifying the number of + * independent samples to draw for each row slice. + * * 2: A 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with shape [2], + * specifying seeds used to initialize the random distribution. + * Outputs: + * * 0: A 2-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor with shape + * [batches, samples], containing the drawn samples. + * + * Available since API level 29. + */ + ANEURALNETWORKS_RANDOM_MULTINOMIAL = 74, + + /** + * Reduces a tensor by computing the "logical and" of elements along given + * dimensions. + * + * If keep_dims is true, the reduced dimensions are + * retained with length 1. Otherwise, the rank of the tensor is reduced by + * 1 for each entry in dimensions. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor. + * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions + * to reduce. Dimension values must be in the range [-n, n). + * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true, + * retains reduced dimensions with length 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_REDUCE_ALL = 75, + + /** + * Reduces a tensor by computing the "logical or" of elements along given + * dimensions. + * + * If keep_dims is true, the reduced dimensions are + * retained with length 1. Otherwise, the rank of the tensor is reduced by + * 1 for each entry in dimensions. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_BOOL8} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor. + * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions + * to reduce. Dimension values must be in the range [-n, n). + * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true, + * retains reduced dimensions with length 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_REDUCE_ANY = 76, + + /** + * Reduces a tensor by computing the maximum of elements along given + * dimensions. + * + * If keep_dims is true, the reduced dimensions are + * retained with length 1. Otherwise, the rank of the tensor is reduced by + * 1 for each entry in dimensions. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor. + * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions + * to reduce. Dimension values must be in the range [-n, n). + * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true, + * retains reduced dimensions with length 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_REDUCE_MAX = 77, + + /** + * Reduces a tensor by computing the minimum of elements along given + * dimensions. + * + * If keep_dims is true, the reduced dimensions are + * retained with length 1. Otherwise, the rank of the tensor is reduced by + * 1 for each entry in dimensions. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor. + * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions + * to reduce. Dimension values must be in the range [-n, n). + * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true, + * retains reduced dimensions with length 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_REDUCE_MIN = 78, + + /** + * Reduces a tensor by multiplying elements along given dimensions. + * + * If keep_dims is true, the reduced dimensions are + * retained with length 1. Otherwise, the rank of the tensor is reduced by + * 1 for each entry in dimensions. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor. + * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions + * to reduce. Dimension values must be in the range [-n, n). + * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true, + * retains reduced dimensions with length 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_REDUCE_PROD = 79, + + /** + * Reduces a tensor by summing elements along given dimensions. + * + * If keep_dims is true, the reduced dimensions are + * retained with length 1. Otherwise, the rank of the tensor is reduced by + * 1 for each entry in dimensions. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: up to 4 + * + * Inputs: + * * 0: An n-D tensor. + * * 1: A 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. The dimensions + * to reduce. Dimension values must be in the range [-n, n). + * * 2: An {@link ANEURALNETWORKS_BOOL} scalar, keep_dims. If true, + * retains reduced dimensions with length 1. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_REDUCE_SUM = 80, + + /** + * Select and scale the feature map of each region of interest to a unified + * output size by average pooling sampling points from bilinear interpolation. + * + * The region of interest is represented by its upper-left corner coordinate + * (x1,y1) and lower-right corner coordinate (x2,y2) in the original image. + * A spatial scaling factor is applied to map into feature map coordinate. + * A valid region of interest should satisfy x1 <= x2 and y1 <= y2. + * + * No rounding is applied in this operation. The sampling points are unified + * distributed in the pooling bin and their values are calculated by bilinear + * interpolation. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * + * Inputs: + * * 0: A 4-D tensor, specifying the feature map. + * * 1: A 2-D Tensor of shape [num_rois, 4], specifying the locations of + * the regions of interest, each line with format [x1, y1, x2, y2]. + * For input0 of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * this tensor should be of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, + * with zeroPoint of 0 and scale of 0.125. Zero num_rois is + * supported for this tensor. + * * 2: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [num_rois], specifying the batch index of each box. Boxes with + * the same batch index are grouped together. Zero num_rois is + * supported for this tensor. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * height of the output tensor. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * width of the output tensor. + * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio + * from the height of original image to the height of feature map. + * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio + * from the width of original image to the width of feature map. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of + * sampling points in height dimension used to compute the output. + * Set to 0 for adaptive value of ceil(roi_height/out_height). + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the number of + * sampling points in width dimension used to compute the output. + * Set to 0 for adaptive value of ceil(roi_width/out_width). + * * 9: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and output0. Set to false for NHWC. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. The output + * shape is [num_rois, out_height, out_width, depth]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from the input0 scale and zeroPoint. + * + * Available since API level 29. + */ + ANEURALNETWORKS_ROI_ALIGN = 81, + + /** + * Select and scale the feature map of each region of interest to a unified + * output size by max-pooling. + * + * The region of interest is represented by its upper-left corner coordinate + * (x1,y1) and lower-right corner coordinate (x2,y2) in the original image. + * A spatial scaling factor is applied to map into feature map coordinate. + * A valid region of interest should satisfy x1 <= x2 and y1 <= y2. + * + * Rounding is applied in this operation to ensure integer boundary for + * regions of interest and pooling bins. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * + * Inputs: + * * 0: A 4-D tensor, specifying the feature map. + * * 1: A 2-D Tensor of shape [num_rois, 4], specifying the locations of + * the regions of interest, each line with format [x1, y1, x2, y2]. + * For input0 of type {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, + * this tensor should be of {@link ANEURALNETWORKS_TENSOR_QUANT16_ASYMM}, + * with zeroPoint of 0 and scale of 0.125. + * * 2: An 1-D {@link ANEURALNETWORKS_TENSOR_INT32} tensor, of shape + * [num_rois], specifying the batch index of each box. Boxes with + * the same batch index are grouped together. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * height of the output tensor. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * width of the output tensor. + * * 5: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio + * from the height of original image to the height of feature map. + * * 6: An {@link ANEURALNETWORKS_FLOAT32} scalar, specifying the ratio + * from the width of original image to the width of feature map. + * * 7: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and output0. Set to false for NHWC. + * + * Outputs: + * * 0: A tensor of the same {@link OperandCode} as input0. The output + * shape is [num_rois, out_height, out_width, depth]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_ROI_POOLING = 82, + + /** + * Computes reciprocal of square root of x element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_RSQRT = 83, + + /** + * Using a tensor of booleans c and input tensors x and y select values + * elementwise from both input tensors: + * + * O[i] = C[i] ? x[i] : y[i]. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: A tensor of type {@link ANEURALNETWORKS_TENSOR_BOOL8} acting as a + * mask that chooses, based on the value at each element, whether the + * corresponding element in the output should be taken from input1 (if + * true) or input2 (if false). + * * 1: An input tensor of the same shape as input0. + * * 2: An input tensor of the same shape and type as input1. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scales and zeroPoint can be different from input1 scale and zeroPoint. + * + * Outputs: + * * 0: A tensor of the same type and shape as input1 and input2. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from inputs' scale and zeroPoint. + * + */ + ANEURALNETWORKS_SELECT = 84, + + /** + * Computes sin of x element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_SIN = 85, + + /** + * Extracts a slice of specified size from the input tensor starting at a + * specified location. + * + * The starting location is specified as a 1-D tensor containing offsets + * for each dimension. The size is specified as a 1-D tensor containing + * either size of a slice along corresponding dimension or -1. In the latter + * case, all the remaining elements in dimension are included in the slice. + * + * A sum of begin offset and a size of a slice must not exceed size of a + * corresponding dimension. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: An n-D tensor to take slice from, may be zero-sized. + * * 1: A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} specifying + * the beginning indices of the slice in each dimension. + * * 2: A 1-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} specifying + * the size of the slice in each dimension. + * + * Outputs: + * * 0: An n-D tensor of the same type as the input containing the slice. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * its scale and zeroPoint has to be same as the input0 scale and zeroPoint. + * + * Available since API level 29. + */ + ANEURALNETWORKS_SLICE = 86, + + /** + * Splits a tensor along a given axis into num_splits subtensors. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: An n-D tensor to split. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar specifying the axis along + * which to split. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar indicating the number of + * splits along given axis. Must evenly divide axis size. + * + * Outputs: + * * 0 ~ (num_splits - 1): Resulting subtensors. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_SPLIT = 87, + + /** + * Computes square root of x element-wise. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: from 1. + * + * Inputs: + * * 0: A tensor. + * + * Outputs: + * * 0: The output tensor of same shape as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_SQRT = 88, + + /** + * Constructs a tensor by tiling a given tensor. + * + * This operation creates a new tensor by replicating `input` `multiples` + * times. The output tensor's i-th dimension has `input.dims(i) * multiples[i]` + * elements, and the values of `input` are replicated `multiples[i]` times + * along the i-th dimension. + * For example, tiling `[a b c d]` by `[2]` produces `[a b c d a b c d]`. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: input, an n-D tensor specifying the input. + * * 1: multiples, a 1-D tensor of {@link ANEURALNETWORKS_TENSOR_INT32}. + * The length of multiples must be n. + * + * Outputs: + * * 0: A tiled tensor of the same {@link OperandCode} and rank as `input`. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TILE = 89, + + /** + * Finds values and indices of the k largest entries for the last dimension. + * + * Resulting values in each dimensions are sorted in descending order. If + * two values are equal, the one with larger index appears first. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_INT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: from 1 + * + * Inputs: + * * 0: input, an n-D tensor specifying the input. + * * 1: k, an {@link ANEURALNETWORKS_INT32} scalar, specifying the number of + * top elements to look for along the last dimension. + * + * Outputs: + * * 0: An n-D tensor of the same type as the input, containing the k + * largest elements along each last dimensional slice. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * * 1: An n-D tensor of type {@link ANEURALNETWORKS_TENSOR_INT32} + * containing the indices of values within the last dimension of input. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TOPK_V2 = 90, + + /** + * Performs the transpose of 2-D convolution operation. + * + * This operation is sometimes called "deconvolution" after Deconvolutional + * Networks, but is actually the transpose (gradient) of + * {@link ANEURALNETWORKS_CONV_2D} rather than an actual deconvolution. + * + * The output dimensions are functions of the filter dimensions, stride, and + * padding. + * + * Supported tensor {@link OperandCode} configurations: + * * 16 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} for input, filter, output, and bias. + * + * * 32 bit floating point: + * * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} for input, filter, output, and bias. + * + * * Quantized: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, filter, and output. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (with scale set to + * * * input.scale * filter.scale). + * + * * Quantized with symmetric per channel quantization for the filter: + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} for input, and output. + * * * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} for filter. + * * * {@link ANEURALNETWORKS_TENSOR_INT32} for bias (scale set to 0.0, + * * * each value scaling is separate and equal to input.scale * filter.scales[channel]). + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * + * Both explicit padding and implicit padding are supported. + * + * Inputs (explicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: A 4-D tensor, of shape + * [depth_out, filter_height, filter_width, depth_in], specifying the + * filter. For tensor of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} the channel + * dimension (ANeuralNetworksSymmPerChannelQuantParams::channelDim) must be set to 0. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or + * {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias should be of the + * same type. For input tensor of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the bias should be + * of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 and + * bias_scale == input_scale * filter_scale. For filter tensor of + * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias + * must be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of + * 0 and bias_scale of 0. The actual scale of each value 'i' is equal + * to bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the left, in the ‘width’ dimension. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the right, in the ‘width’ dimension. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the top, in the ‘height’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the padding on + * the bottom, in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 8: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 9: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 10: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and output0. Set to false for NHWC. + * + * Inputs (implicit padding): + * * 0: A 4-D tensor, of shape [batches, height, width, depth_in], + * specifying the input. + * Since API level 29, zero batches is supported for this tensor. + * * 1: A 4-D tensor, of shape + * [depth_out, filter_height, filter_width, depth_in], specifying the + * filter. For tensor of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} the channel + * dimension (ANeuralNetworksSymmPerChannelQuantParams::channelDim) must be set to 0. + * * 2: A 1-D tensor, of shape [depth_out], specifying the bias. For input + * tensor of type {@link ANEURALNETWORKS_TENSOR_FLOAT32} or + * {@link ANEURALNETWORKS_TENSOR_FLOAT16}, the bias should be of the + * same type. For input tensor of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM}, the bias should be + * of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of 0 and + * bias_scale == input_scale * filter_scale. For filter tensor of + * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}, the bias + * must be of {@link ANEURALNETWORKS_TENSOR_INT32}, with zeroPoint of + * 0 and bias_scale of 0. The actual scale of each value 'i' is equal + * to bias_scale[i] = input_scale * filter_scale[i]. + * * 3: An {@link ANEURALNETWORKS_TENSOR_INT32} tensor, specifying the output + * tensor shape. + * * 4: An {@link ANEURALNETWORKS_INT32} scalar, specifying the implicit + * padding scheme, has to be one of the + * {@link PaddingCode} values. + * * 5: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘width’ dimension. + * * 6: An {@link ANEURALNETWORKS_INT32} scalar, specifying the stride when + * walking through input in the ‘height’ dimension. + * * 7: An {@link ANEURALNETWORKS_INT32} scalar, and has to be one of the + * {@link FuseCode} values. Specifies the activation to + * invoke on the result. + * * 8: An {@link ANEURALNETWORKS_BOOL} scalar, set to true to specify + * NCHW data layout for input0 and output0. Set to false for NHWC. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, out_height, out_width, depth_out]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint can be different from inputs' scale and zeroPoint. + * + * Available since API level 29. + */ + ANEURALNETWORKS_TRANSPOSE_CONV_2D = 91, + + /** + * A recurrent neural network specified by an LSTM cell. + * + * Performs (fully) dynamic unrolling of input. + * + * This Op unrolls the input along the time dimension, and implements the + * following operation for each element in the sequence + * s = 1...sequence_length: + * outputs[s] = projection(state = activation(LSTMOp(inputs[s]))) + * + * Where LSTMOp is the LSTM op as in {@link ANEURALNETWORKS_LSTM}, + * the "projection" is an optional projection layer from state and output + * and the “activation” is the function passed as the + * “fused_activation_function” argument (if not “NONE”). + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * Supported tensor rank: 3, either time-major or batch-major. + * + * All input and output tensors must be of the same type. + * + * Inputs: + * * 0: The input (\f$x_t\f$). + * A 3-D tensor of shape: + * If time-major: [max_time, batch_size, input_size] + * If batch-major: [batch_size, max_time, input_size] + * where “max_time” is the number of timesteps (sequence length), + * “batch_size” corresponds to the batching dimension, and + * “input_size” is the size of the input. + * * 1: The input-to-input weights (\f$W_{xi}\f$). Optional. + * A 2-D tensor of shape [num_units, input_size], where “num_units” + * corresponds to the number of cell units. + * * 2: The input-to-forget weights (\f$W_{xf}\f$). + * A 2-D tensor of shape [num_units, input_size]. + * * 3: The input-to-cell weights (\f$W_{xc}\f$). + * A 2-D tensor of shape [num_units, input_size]. + * * 4: The input-to-output weights (\f$W_{xo}\f$). + * A 2-D tensor of shape [num_units, input_size]. + * * 5: The recurrent-to-input weights (\f$W_{hi}\f$). Optional. + * A 2-D tensor of shape [num_units, output_size], where “output_size” + * corresponds to either the number of cell units (i.e., “num_units”), + * or the second dimension of the “projection_weights”, if defined. + * * 6: The recurrent-to-forget weights (\f$W_{hf}\f$). + * A 2-D tensor of shape [num_units, output_size]. + * * 7: The recurrent-to-cell weights (\f$W_{hc}\f$). + * A 2-D tensor of shape [num_units, output_size]. + * * 8: The recurrent-to-output weights (\f$W_{ho}\f$). + * A 2-D tensor of shape [num_units, output_size]. + * * 9: The cell-to-input weights (\f$W_{ci}\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 10:The cell-to-forget weights (\f$W_{cf}\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 11:The cell-to-output weights (\f$W_{co}\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 12:The input gate bias (\f$b_i\f$). Optional. + * A 1-D tensor of shape [num_units]. + * * 13:The forget gate bias (\f$b_f\f$). + * A 1-D tensor of shape [num_units]. + * * 14:The cell bias (\f$b_c\f$). + * A 1-D tensor of shape [num_units]. + * * 15:The output gate bias (\f$b_o\f$). + * A 1-D tensor of shape [num_units]. + * * 16:The projection weights (\f$W_{proj}\f$). Optional. + * A 2-D tensor of shape [output_size, num_units]. + * * 17:The projection bias (\f$b_{proj}\f$). Optional. + * A 1-D tensor of shape [output_size]. + * * 18:The output state (in) (\f$h_{t-1}\f$). + * A 2-D tensor of shape [batch_size, output_size]. + * * 19:The cell state (in) (\f$C_{t-1}\f$). + * A 2-D tensor of shape [batch_size, num_units]. + * * 20:The activation function (\f$g\f$). + * A value indicating the activation function: + *
    + *
  • 0: None; + *
  • 1: Relu; + *
  • 3: Relu6; + *
  • 4: Tanh; + *
  • 6: Sigmoid. + *
+ * * 21:The clipping threshold (\f$t_{cell}\f$) for the cell state, such + * that values are bound within [-cell_clip, cell_clip]. If set to 0.0 + * then clipping is disabled. + * * 22:The clipping threshold (\f$t_{proj}\f$) for the output from the + * projection layer, such that values are bound within + * [-proj_clip, proj_clip]. If set to 0.0 then clipping is disabled. + * * 23:Time-major if true, batch-major if false. + * * 24:The input layer normalization weights. Optional. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at input gate. + * * 25:The forget layer normalization weights. Optional. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at forget gate. + * * 26:The cell layer normalization weights. Optional. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at cell gate. + * * 27:The output layer normalization weights. Optional. + * A 1-D tensor of shape [num_units]. Used to rescale normalized inputs + * to activation at output gate. + * + * Outputs: + * * 0: The output (\f$o_t\f$). + * A 3-D tensor of shape: + * If time-major: [max_time, batch_size, output_size] + * If batch-major: [batch_size, max_time, output_size] + * + * Available since API level 29. + * + * Important: As of API level 29, there is no way to get the output state tensors out and NNAPI + * does not maintain internal states. This operator does not support the usage pattern in which + * multiple cells are chained and state tensors are propagated. + */ + ANEURALNETWORKS_UNIDIRECTIONAL_SEQUENCE_LSTM = 92, + + /** + * A recurrent neural network layer that applies a basic RNN cell to a + * sequence of inputs. + * + * This layer unrolls the input along the sequence dimension, and implements + * the following operation + * for each element in the sequence s = 1...sequence_length: + * outputs[s] = state = activation(inputs[s] * input_weights’ + state * + * recurrent_weights’ + bias) + * + * Where: + * * “input_weights” is a weight matrix that multiplies the inputs; + * * “recurrent_weights” is a weight matrix that multiplies the current + * “state” which itself is the output from the previous time step + * computation; + * * “bias” is a bias vector (added to each output vector in the batch); + * * “activation” is the function passed as the “fused_activation_function” + * argument (if not “NONE”). + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * + * The input tensors must all be the same type. + * + * Inputs: + * * 0: input. + * A 3-D tensor. The shape is defined by the input 6 (timeMajor). If + * it is set to 1, then the input has a shape [maxTime, batchSize, + * inputSize], otherwise the input has a shape [batchSize, maxTime, + * inputSize]. + * * 1: weights. + * A 2-D tensor of shape [numUnits, inputSize]. + * * 2: recurrent_weights. + * A 2-D tensor of shape [numUnits, numUnits]. + * * 3: bias. + * A 1-D tensor of shape [numUnits]. + * * 4: hidden state + * A 2-D tensor of shape [batchSize, numUnits]. Specifies a hidden + * state input for the first time step of the computation. + * * 5: fusedActivationFunction. + * A {@link FuseCode} value indicating the activation function. If + * “NONE” is specified then it results in a linear activation. + * * 6: timeMajor + * An {@link ANEURALNETWORKS_INT32} scalar specifying the shape format + * of input and output tensors. Must be set to either 0 or 1. + * Outputs: + * * 0: output. + * A 3-D tensor. The shape is defined by the input 6 (timeMajor). If + * it is set to 1, then the output has a shape [maxTime, batchSize, + * numUnits], otherwise the output has a shape [batchSize, maxTime, + * numUnits]. + * + * Available since API level 29. + * + * Important: As of API level 29, there is no way to get the output state tensors out and NNAPI + * does not maintain internal states. This operator does not support the usage pattern in which + * multiple cells are chained and state tensors are propagated. + */ + ANEURALNETWORKS_UNIDIRECTIONAL_SEQUENCE_RNN = 93, + + /** + * Resizes images to given size using the nearest neighbor interpretation. + * + * Resized images must be distorted if their output aspect ratio is not the + * same as input aspect ratio. The corner pixels of output may not be the + * same as corner pixels of input. + * + * Supported tensor {@link OperandCode}: + * * {@link ANEURALNETWORKS_TENSOR_FLOAT16} + * * {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * * {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} + * + * Supported tensor rank: 4, with "NHWC" or "NCHW" data layout. + * With the default data layout NHWC, the data is stored in the order of: + * [batch, height, width, channels]. Alternatively, the data layout could + * be NCHW, the data storage order of: [batch, channels, height, width]. + * + * Both resizing by shape and resizing by scale are supported. + * + * Inputs (resizing by shape): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. Zero batches is supported for this tensor. + * * 1: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * width of the output tensor. + * * 2: An {@link ANEURALNETWORKS_INT32} scalar, specifying the output + * height of the output tensor. + * * 3: An {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * + * Inputs (resizing by scale): + * * 0: A 4-D tensor, of shape [batches, height, width, depth], specifying + * the input. Zero batches is supported for this tensor. + * * 1: A scalar, specifying width_scale, the scaling factor of the width + * dimension from the input tensor to the output tensor. The output + * width is calculated as new_width = floor(width * width_scale). + * The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is + * of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} otherwise. + * * 2: A scalar, specifying height_scale, the scaling factor of the height + * dimension from the input tensor to the output tensor. The output + * height is calculated as new_height = floor(height * height_scale). + * The scalar must be of {@link ANEURALNETWORKS_FLOAT16} if input0 is + * of {@link ANEURALNETWORKS_TENSOR_FLOAT16} and of + * {@link ANEURALNETWORKS_FLOAT32} otherwise. + * * 3: An {@link ANEURALNETWORKS_BOOL} scalar, default to false. + * Set to true to specify NCHW data layout for input0 and output0. + * + * Outputs: + * * 0: The output 4-D tensor, of shape + * [batches, new_height, new_width, depth]. + * For a {@link ANEURALNETWORKS_TENSOR_QUANT8_ASYMM} tensor, + * the scale and zeroPoint must be the same as input0. + * + * Available since API level 29. + */ + ANEURALNETWORKS_RESIZE_NEAREST_NEIGHBOR = 94, +} OperationCode; + +/** + * Fused activation function types. + * + * + * Available since API level 27. + */ +typedef enum { + /** NO fused activation function. */ + ANEURALNETWORKS_FUSED_NONE = 0, + /** Fused ReLU activation function. */ + ANEURALNETWORKS_FUSED_RELU = 1, + /** Fused ReLU1 activation function. */ + ANEURALNETWORKS_FUSED_RELU1 = 2, + /** Fused ReLU6 activation function. */ + ANEURALNETWORKS_FUSED_RELU6 = 3, +} FuseCode; + +/** + * Implicit padding algorithms. + * + * + * Available since API level 27. + */ +typedef enum { + /** + * SAME padding. + * Padding on both ends are the "same": + * padding_to_beginning = total_padding / 2 + * padding_to_end = (total_padding + 1)/2. + * i.e., for even number of padding, padding to both ends are exactly + * the same; for odd number of padding, padding to the ending is bigger + * than the padding to the beginning by 1. + * + * total_padding is a function of input, stride, dilation and filter size. + * It could be computed as follows: + * out_size = (input + stride - 1) / stride + * effective_filter_size = (filter_size - 1) * dilation + 1 + * needed_input = (out_size - 1) * stride + effective_filter_size + * total_padding = max(0, needed_input - input_size) + * The computation is the same for the horizontal and vertical directions. + */ + ANEURALNETWORKS_PADDING_SAME = 1, + + /** + * VALID padding. + * No padding. When the input size is not evenly divisible by + * the filter size, the input at the end that could not fill + * the whole filter tile will simply be ignored. + */ + ANEURALNETWORKS_PADDING_VALID = 2, +} PaddingCode; + +/** + * Execution preferences. + * + * Available since API level 27. + */ +typedef enum { + /** + * Prefer executing in a way that minimizes battery drain. + * This is desirable for compilations that will be executed often. + */ + ANEURALNETWORKS_PREFER_LOW_POWER = 0, + /** + * Prefer returning a single answer as fast as possible, even if this causes + * more power consumption. + */ + ANEURALNETWORKS_PREFER_FAST_SINGLE_ANSWER = 1, + /** + * Prefer maximizing the throughput of successive frames, for example when + * processing successive frames coming from the camera. + */ + ANEURALNETWORKS_PREFER_SUSTAINED_SPEED = 2, +} PreferenceCode; + +/** + * Device types. + * + * The type of NNAPI device. + */ +typedef enum { + /** The device type cannot be provided. */ + ANEURALNETWORKS_DEVICE_UNKNOWN = 0, + /** The device does not fall into any category below. */ + ANEURALNETWORKS_DEVICE_OTHER = 1, + /** The device runs NNAPI models on single or multi-core CPU. */ + ANEURALNETWORKS_DEVICE_CPU = 2, + /** The device can run NNAPI models and also accelerate graphics APIs such + * as OpenGL ES and Vulkan. */ + ANEURALNETWORKS_DEVICE_GPU = 3, + /** Dedicated accelerator for Machine Learning workloads. */ + ANEURALNETWORKS_DEVICE_ACCELERATOR = 4, +} DeviceTypeCode; + +/** + * Result codes. + * + *

Any NNAPI function can return any result code, including result codes not + * currently documented. Any value other than {@link ANEURALNETWORKS_NO_ERROR} + * indicates a failure of some kind.

+ * + *

Additional information about the nature of a failure can be obtained from + * the device log after enabling NNAPI debugging by setting the debug.nn.vlog + * property to 1, e.g., by calling "adb shell setprop debug.nn.vlog 1".

+ * + * Available since API level 27. + */ +typedef enum { + /** + * Operation was succesful. + */ + ANEURALNETWORKS_NO_ERROR = 0, + + /** + * Failure caused by not enough available memory. + */ + ANEURALNETWORKS_OUT_OF_MEMORY = 1, + + ANEURALNETWORKS_INCOMPLETE = 2, + + /** + * Failure caused by unexpected null argument. + */ + ANEURALNETWORKS_UNEXPECTED_NULL = 3, + + /** + * Failure caused by invalid function arguments, invalid model definition, + * invalid execution definition or invalid data at execution time. + */ + ANEURALNETWORKS_BAD_DATA = 4, + + /** + * Failure caused by failed model execution. + */ + ANEURALNETWORKS_OP_FAILED = 5, + + /** + * Failure caused by object being in the wrong state. + */ + ANEURALNETWORKS_BAD_STATE = 6, + + /** + * Failure caused by not being able to map a file into memory. + * This may be caused by a file descriptor not being mappable, or an AHardwareBuffer + * not supported by the device. + * Mitigate by reading its content into memory. + */ + ANEURALNETWORKS_UNMAPPABLE = 7, + + /** + * Failure caused by insufficient buffer size provided to a model output. + */ + ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE = 8, + + /** + * Failure caused by a device not being available. + */ + ANEURALNETWORKS_UNAVAILABLE_DEVICE = 9, +} ResultCode; + +/** + * For {@link ANeuralNetworksModel_setOperandValue}, values with a + * length smaller or equal to this will be immediately copied into + * the model. The size is in bytes. + * + * Available since API level 27. + */ +enum { ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES = 128 }; + +/** + * For {@link ANeuralNetworksCompilation_setCaching}, specify the size + * of the cache token required from the application. The size is in bytes. + * + * Available since API level 29. + */ +enum { ANEURALNETWORKS_BYTE_SIZE_OF_CACHE_TOKEN = 32 }; + +/** + * ANeuralNetworksMemory is an opaque type that represents memory. + * + * This type is used to represent shared memory, memory mapped files, + * and similar memories. + * + * By using shared memory, a program can efficiently communicate to the + * runtime and drivers the tensors that define a model. See + * {@link ANeuralNetworksModel_setOperandValueFromMemory}. An application + * should typically create one shared memory object that contains every constant tensor + * needed to define a model. {@link ANeuralNetworksMemory_createFromFd} can be used to + * create shared memory from a file handle. + * {@link ANeuralNetworksMemory_createFromAHardwareBuffer} can be used to + * create shared memory from an AHardwareBuffer handle. + * + * Memory objects can also be used to specify the input and output arguments of + * an execution. See {@link ANeuralNetworksExecution_setInputFromMemory} + * and {@link ANeuralNetworksExecution_setOutputFromMemory}. + * + * When calling {@link ANeuralNetworksModel_setOperandValueFromMemory}, + * {@link ANeuralNetworksExecution_setInputFromMemory} and + * {@link ANeuralNetworksExecution_setOutputFromMemory}, each operand in the shared + * memory object must be aligned on a boundary of a byte size that is a multiple + * of the element type byte size, e.g., a tensor with + * {@link ANEURALNETWORKS_TENSOR_FLOAT32} type must be aligned on 4-byte boundary. + * + * It is the application's responsibility to ensure that there are no uses of + * the memory after calling {@link ANeuralNetworksMemory_free}. This includes + * any model which references this memory because of a call to + * {@link ANeuralNetworksModel_setOperandValueFromMemory}, any compilation + * created using such a model, any execution object or burst object created + * using such a compilation, or any execution which references this memory + * because of a call to {@link ANeuralNetworksExecution_setInputFromMemory} or + * {@link ANeuralNetworksExecution_setOutputFromMemory}. + * + * Available since API level 27. + */ +typedef struct ANeuralNetworksMemory ANeuralNetworksMemory; + +/** + * ANeuralNetworksModel is an opaque type that contains a description of the + * mathematical operations that constitute the model. + * + *

Build the model by calling

    + *
  • {@link ANeuralNetworksModel_create}
    • + *
  • {@link ANeuralNetworksModel_addOperation}
    • + *
  • {@link ANeuralNetworksModel_addOperand}
    • + *
+ * + * This forms a graph in which each operation and operand is a node, a + * directed edge from an operand to an operation indicates that the + * operand is an input to the operation, and a directed edge from an + * operation to an operand indicates that the operand is an output + * from the operation. This graph must be acyclic. + * + * A model is completed by calling {@link ANeuralNetworksModel_finish}. + * A model is destroyed by calling {@link ANeuralNetworksModel_free}. + * + *

A model cannot be modified once {@link ANeuralNetworksModel_finish} + * has been called on it.

+ * + *

It is the application's responsibility to make sure that only one thread + * modifies a model at a given time. It is however safe for more than one + * thread to use the model once {@link ANeuralNetworksModel_finish} has returned.

+ * + *

It is also the application's responsibility to ensure that there are no + * other uses of the model after calling {@link ANeuralNetworksModel_free}. + * This includes any compilation, execution object or burst object created using + * the model.

+ * + * Available since API level 27. + */ +typedef struct ANeuralNetworksModel ANeuralNetworksModel; + +/** + * ANeuralNetworksCompilation is an opaque type that can be used to compile + * a machine learning model. + * + *

To use:

    + *
  • Create a new compilation instance by calling the + * {@link ANeuralNetworksCompilation_create} function or + * {@link ANeuralNetworksCompilation_createForDevices}.
    • + *
  • Set any desired properties on the compilation (for example, + * {@link ANeuralNetworksCompilation_setPreference}).
    • + *
  • Optionally, set the caching signature and the cache directory on the + * compilation by calling {@link ANeuralNetworksCompilation_setCaching}.
    • + *
  • Complete the compilation with {@link ANeuralNetworksCompilation_finish}.
    • + *
  • Use the compilation as many times as needed + * with {@link ANeuralNetworksExecution_create} and + * {@link ANeuralNetworksBurst_create}.
    • + *
  • Destroy the compilation with {@link ANeuralNetworksCompilation_free} + * once all executions using the compilation have completed.

+ * + * A compilation is completed by calling {@link ANeuralNetworksCompilation_finish}. + * A compilation is destroyed by calling {@link ANeuralNetworksCompilation_free}. + * + *

A compilation cannot be modified once {@link ANeuralNetworksCompilation_finish} + * has been called on it.

+ * + *

It is the application's responsibility to make sure that only + * one thread modifies a compilation at a given time. It is however + * safe for more than one thread to use the compilation once + * {@link ANeuralNetworksCompilation_finish} has returned.

+ * + *

It is also the application's responsibility to ensure that there are no other + * uses of the compilation after calling {@link ANeuralNetworksCompilation_free}. + * This includes any execution object or burst object created using the compilation.

+ * + * Available since API level 27. + */ +typedef struct ANeuralNetworksCompilation ANeuralNetworksCompilation; + +/** + * ANeuralNetworksExecution is an opaque type that can be used to apply a machine + * learning model to a set of inputs. + * + *

To use:

    + *
  • Create a new execution instance by calling the + * {@link ANeuralNetworksExecution_create} function.
    • + *
  • Associate input buffers or memory regions to the model inputs with + * {@link ANeuralNetworksExecution_setInput} or + * {@link ANeuralNetworksExecution_setInputFromMemory}.
    • + *
  • Associate output buffers or memory regions to the model outputs with + * {@link ANeuralNetworksExecution_setOutput} or + * {@link ANeuralNetworksExecution_setOutputFromMemory}.
    • + *
  • Apply the model with one of the following:
      • + *
    • Asynchronously with {@link ANeuralNetworksExecution_startCompute}, + * waiting for the execution to complete with + * {@link ANeuralNetworksEvent_wait}.
      • + *
    • Synchronously with {@link ANeuralNetworksExecution_compute}.
      • + *
    • Synchronously as part of an execution burst with + * {@link ANeuralNetworksExecution_burstCompute}.
    + *
  • Destroy the execution with + * {@link ANeuralNetworksExecution_free}.

+ * + *

An output buffer or memory region must not overlap with any + * other output buffer or memory region, with an input buffer or + * memory region, or with an operand value in a memory object + * ({@link ANeuralNetworksModel_setOperandValueFromMemory}).

+ * + *

An execution cannot be modified once + * {@link ANeuralNetworksExecution_burstCompute}, + * {@link ANeuralNetworksExecution_compute} or + * {@link ANeuralNetworksExecution_startCompute} has been called on it.

+ * + *

An execution can be applied to a model with + * {@link ANeuralNetworksExecution_burstCompute}, + * {@link ANeuralNetworksExecution_compute} or + * {@link ANeuralNetworksExecution_startCompute} only once. Create new + * executions to do new evaluations of the model.

+ * + *

It is the application's responsibility to make sure that only one thread + * modifies an execution at a given time. It is however safe for more than one + * thread to use {@link ANeuralNetworksEvent_wait} at the same time.

+ * + *

It is also the application's responsibility to ensure that the execution + * either has never been scheduled or has completed (i.e., that + * {@link ANeuralNetworksExecution_burstCompute}, + * {@link ANeuralNetworksExecution_compute}, or + * {@link ANeuralNetworksEvent_wait} has returned) before calling + * {@link ANeuralNetworksExecution_free}.

. + * + *

It is also the application's responsibility to ensure that there are no other + * uses of the execution after calling {@link ANeuralNetworksExecution_free}.

+ * + *

Multiple executions can be scheduled and evaluated concurrently, either by + * means of {@link ANeuralNetworksExecution_compute} or + * {@link ANeuralNetworksExecution_burstCompute} (which are synchronous) in + * different threads, or by means of + * {@link ANeuralNetworksExecution_startCompute} (which is asynchronous). + * (Concurrent uses of {@link ANeuralNetworksExecution_burstCompute} must be on + * different burst objects.) The runtime makes no guarantee on the ordering of + * completion of executions. If it's important to the application, the + * application should enforce the ordering by ensuring that one execution + * completes before the next is scheduled (for example, by scheduling all + * executions synchronously within a single thread, or by scheduling all + * executions asynchronously and using {@link ANeuralNetworksEvent_wait} between + * calls to {@link ANeuralNetworksExecution_startCompute}).

+ * + * Available since API level 27. + */ +typedef struct ANeuralNetworksExecution ANeuralNetworksExecution; + +// #if __ANDROID_API__ >= __ANDROID_API_Q__ +/** + * Parameters for ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL operand. + */ +typedef struct ANeuralNetworksSymmPerChannelQuantParams { + /* The index of the channel dimension. */ + uint32_t channelDim; + /** The size of the scale array. Should be equal to dimension[channelDim] of the Operand. */ + uint32_t scaleCount; + /** The array of scaling values for each channel. Each value must be greater than zero. */ + const float* scales; +} ANeuralNetworksSymmPerChannelQuantParams; + +/** + * ANeuralNetworksBurst is an opaque type that can be used to reduce the latency + * of a rapid sequence of executions. It will likely cause overhead if only used + * for a single execution. + * + * ANeuralNetworksBurst serves as a context object for any number of inferences + * using {@link ANeuralNetworksExecution} objects. An ANeuralNetworksBurst + * object and the {@link ANeuralNetworksExecution} objects used with it must all + * have been created from the same {@link ANeuralNetworksCompilation} object. + * + * This object is also used as a hint to drivers, providing insight to the + * lifetime of a rapid sequence of executions. For example, a driver may choose + * to increase the clock frequency of its accelerator for the lifetime of a + * burst object. + * + *

To use:

    + *
  • Create a new burst object by calling the + * {@link ANeuralNetworksBurst_create} function.
    • + *
  • For each execution:
      • + *
    • Create {@link ANeuralNetworksExecution} and configure its + * properties (see {@link ANeuralNetworksExecution} for details).
      • + *
    • Apply the model synchronously with + * {@link ANeuralNetworksExecution_burstCompute}, reusing the same + * {@link ANeuralNetworksBurst} with the new + * {@link ANeuralNetworksExecution}.
      • + *
    • Use and free the {@link ANeuralNetworksExecution}.
    + *
  • Destroy the burst with + * {@link ANeuralNetworksBurst_free}.

+ * + * Available since API level 29. + */ +typedef struct ANeuralNetworksBurst ANeuralNetworksBurst; +// #endif // __ANDROID_API__ >= __ANDROID_API_Q__ + +/** + * ANeuralNetworksOperandType describes the type of an operand. + * + * This structure is used to describe both scalars and tensors. + * + * A tensor operand type with all dimensions specified is "fully + * specified". Whenever possible (i.e., whenever the dimensions are + * known at model construction time), a tensor operand type should be + * (but is not required to be) fully specified, in order to enable the + * best possible performance. + * + * If a tensor operand's type is not fully specified, the dimensions + * of the operand are deduced from the operand types and values of the + * operation for which that operand is an output. + * + *

In the following situations, a tensor operand type must be fully + * specified:

    + *
  • The operand has a constant value, set by + * {@link ANeuralNetworksModel_setOperandValue} (with a + * non-nullptr buffer) or + * {@link ANeuralNetworksModel_setOperandValueFromMemory}.
    • + *
  • The operand is a model input (see + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}). A + * fully specified tensor operand type must either be provided + * to {@link ANeuralNetworksModel_addOperand}; or it must be + * provided to the corresponding + * {@link ANeuralNetworksExecution_setInput}, or + * {@link ANeuralNetworksExecution_setInputFromMemory}. + * EXCEPTION: If the input is optional and omitted + * (by passing nullptr for buffer to + * {@link ANeuralNetworksExecution_setInput}) then it need + * not have a fully specified tensor operand type.
+ * + * A tensor operand type of specified rank but some number of + * unspecified dimensions is represented by setting dimensionCount to + * the rank and each unspecified dimension to 0. + * + * Available since API level 27. + * + * Starting at API level 29, a tensor operand type of unspecified rank is + * represented by setting dimensionCount to 0 and dimensions to NULL (just as if + * it were a scalar operand type). + */ +typedef struct ANeuralNetworksOperandType { + /** + * The data type, e.g ANEURALNETWORKS_FLOAT32. + */ + int32_t type; + + /** + * The number of dimensions (rank). + * + * Must be 0 for scalars. + */ + uint32_t dimensionCount; + + /** + * The dimensions of the tensor. + * + * Must be nullptr for scalars. + */ + const uint32_t* dimensions; + + /** + * These two fields are only used for quantized tensors. + * They must be zero for all other types. + * The dequantized value of each entry is (value - zeroPoint) * scale. + */ + float scale; + int32_t zeroPoint; +} ANeuralNetworksOperandType; + +typedef int32_t ANeuralNetworksOperationType; + +/** + * ANeuralNetworksEvent is an opaque type that represents an event + * that will be signaled once an execution completes. + * + * Available since API level 27. + */ +typedef struct ANeuralNetworksEvent ANeuralNetworksEvent; + +// #if __ANDROID_API__ >= __ANDROID_API_Q__ + +/** + * ANeuralNetworksDevice is an opaque type that represents a device. + * + * This type is used to query basic properties and supported operations of the corresponding + * device, and control which device(s) a model is to be run on. + * + * Available since API level 29. + */ +typedef struct ANeuralNetworksDevice ANeuralNetworksDevice; + +/** + * Get the number of available devices. + * + * @param numDevices Used to return the number of devices. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworks_getDeviceCount(uint32_t* numDevices) __INTRODUCED_IN(29); + +/** + * Get the representation of the specified device. + * + * @param devIndex The index of the specified device. Must be less than the + number of available devices. + * @param device The representation of the specified device. + * The same representation will always be returned for the specified + * device. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworks_getDevice(uint32_t devIndex, ANeuralNetworksDevice** device) + __INTRODUCED_IN(29); + +/** + * Get the name of the specified device. + * + * @param device The representation of the specified device. + * @param name The returned name of the specified device. The name will be in UTF-8 + * and will be null-terminated. It will be recognizable as a known device name + * rather than a cryptic string. For devices with feature level 29 and above, the + * format of the name is {VENDOR}-{DEVICE}. For devices with feature level 28 + * or lower, the format of the name is undefined. + * The name will remain valid for the duration of the application. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworksDevice_getName(const ANeuralNetworksDevice* device, const char** name) + __INTRODUCED_IN(29); + +/** + * Get the type of a given device. + * + * The device type can be used to help application developers to distribute Machine Learning + * workloads and other workloads such as graphical rendering. + * E.g., for an app which renders AR scenes based on real time object detection results, + * the developer could choose an ACCELERATOR type device for ML workloads, and reserve GPU + * for graphical rendering. + * + * @param device The representation of the specified device. + * @param type The returned {@link DeviceTypeCode} of the specified device. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworksDevice_getType(const ANeuralNetworksDevice* device, int32_t* type) + __INTRODUCED_IN(29); + +/** + * Get the version of the driver implementation of the specified device. + * + * It’s the responsibility of the driver implementor to insure that this version string + * uniquely distinguishes this implementation from all previous implementations. + * + * This version string must not be confused with the feature level which is solely defined + * by {@link ANeuralNetworksDevice_getFeatureLevel}. There is no implicit ordering of the versions. + * For example, it is not possible to filter all drivers older than a certain version. + * + * Application developers may use this version string to avoid or prefer specific driver + * implementations. For example, an application may want to do so because: + * - A specific version of the driver does not provide the required performance, + * perhaps because of a performance regression. + * - A specific version of the driver has a bug or returns results that don’t match + * the minimum precision requirement for the application. + * + * @param device The representation of the specified device. + * @param version The returned version string of the driver for the specified device. The + * string will be in UTF-8 and will be null-terminated. For devices with feature + * level 28 or lower, "UNKNOWN" will be returned. The version string will remain + * valid for the duration of the application. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworksDevice_getVersion(const ANeuralNetworksDevice* device, const char** version) + __INTRODUCED_IN(29); + +/** + * Get the supported NNAPI version of the specified device. + * + * Each device has a supported feature level, which is the most advanced feature this driver + * implements. For example, if the driver implements the features introduced in Android P, + * but does not implement the features introduced after Android P, the value would be 28. + * Developers could decide whether or not the specified device should be used for a Model that + * has certain feature requirements. + * + * @param device The representation of the specified device. + * @param featureLevel The API level of the most advanced feature this driver implements. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworksDevice_getFeatureLevel(const ANeuralNetworksDevice* device, + int64_t* featureLevel) __INTRODUCED_IN(29); + +/** + * Get the supported operations for a specified set of devices. If multiple devices + * are selected, the supported operation list is a union of supported operations of all + * selected devices. + * + * @param model The model to be queried. + * @param devices The set of devices. Must not contain duplicates. + * @param numDevices The number of devices in the set. + * @param supportedOps The boolean array to be filled. True means supported. The size of the + * boolean array must be at least as large as the number of operations + * in the model. The order of elements in the supportedOps array matches + * the order in which the corresponding operations were added to the model. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworksModel_getSupportedOperationsForDevices( + const ANeuralNetworksModel* model, const ANeuralNetworksDevice* const* devices, + uint32_t numDevices, bool* supportedOps) __INTRODUCED_IN(29); + +/** + * Create a {@link ANeuralNetworksCompilation} to compile the given model for a specified set + * of devices. If more than one device is specified, the compilation will + * distribute the workload automatically across the devices. The model must be fully + * supported by the specified set of devices. This means that + * ANeuralNetworksModel_getSupportedOperationsForDevices() must have returned true for every + * operation for that model/devices pair. + * + * The user must handle all compilation and execution failures from the + * specified set of devices. This is in contrast to a use of {@link + * ANeuralNetworksCompilation_create}, where the runtime will attempt to recover + * from such failures. + * + * @param model The {@link ANeuralNetworksModel} to be compiled. + * @param devices The set of devices. Must not contain duplicates. + * @param numDevices The number of devices in the set. + * @param compilation The newly created object or NULL if unsuccessful. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA + * if the model is invalid. + * + * Available since API level 29. + */ +int ANeuralNetworksCompilation_createForDevices(ANeuralNetworksModel* model, + const ANeuralNetworksDevice* const* devices, + uint32_t numDevices, + ANeuralNetworksCompilation** compilation) + __INTRODUCED_IN(29); + +/** + * Sets the compilation caching signature and the cache directory. + * + * Provides optional caching information to the runtime for faster repeated + * compilation. + * + * See {@link ANeuralNetworksCompilation} for information on multithreaded usage. + * + * @param compilation The compilation to be modified. + * @param cacheDir The cache directory for the runtime to store and retrieve caching + * data. It is recommended to use the code cache directory provided + * by the Android runtime. If not using the code cache directory, the + * user should choose a directory local to the application, and is + * responsible for managing the cache entries. + * @param token The token provided by the user to specify a model must be of length + * ANEURALNETWORKS_BYTE_SIZE_OF_CACHE_TOKEN. The user should ensure that + * the token is unique to a model within the application. The NNAPI + * runtime cannot detect token collisions; a collision will result in a + * failed execution or in a successful execution that produces incorrect + * output values. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + * + * Available since API level 29. + */ +int ANeuralNetworksCompilation_setCaching(ANeuralNetworksCompilation* compilation, + const char* cacheDir, const uint8_t* token) + __INTRODUCED_IN(29); + +/** + * Schedule synchronous evaluation of the execution. + * + *

Schedules synchronous evaluation of the execution. Returns once the + * execution has completed and the outputs are ready to be consumed. + *

+ * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * See {@link ANeuralNetworksExecution_startCompute} for asynchronous execution. + * Synchronous execution incurs lower overhead than asynchronous execution. + * + * Available since API level 29. + * + * @param execution The execution to be scheduled and executed. + * + * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally. + * ANEURALNETWORKS_UNMAPPABLE if the execution input or output memory cannot + * be properly mapped. + */ +int ANeuralNetworksExecution_compute(ANeuralNetworksExecution* execution) __INTRODUCED_IN(29); + +/** + * Get the dimensional information of the specified output operand of the model of the + * {@link ANeuralNetworksExecution}. + * + * On asynchronous execution initiated by {@link ANeuralNetworksExecution_startCompute}, + * {@link ANeuralNetworksEvent_wait} must be called prior to this function to recuperate + * the resources used by the execution. + * + * @param execution The execution to be queried. + * @param index The index of the output argument we are querying. It is + * an index into the lists passed to + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not + * the index associated with {@link ANeuralNetworksModel_addOperand}. + * @param rank The rank of the output operand. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE + * if the target output is provided an insufficient buffer at execution time, + * ANEURALNETWORKS_BAD_DATA if the index is invalid. + * + * Available since API level 29. + */ +int ANeuralNetworksExecution_getOutputOperandRank(ANeuralNetworksExecution* execution, + int32_t index, uint32_t* rank) + __INTRODUCED_IN(29); + +/** + * Get the dimensional information of the specified output operand of the model of the + * {@link ANeuralNetworksExecution}. The target output operand cannot be a scalar. + * + * On asynchronous execution initiated by {@link ANeuralNetworksExecution_startCompute}, + * {@link ANeuralNetworksEvent_wait} must be called prior to this function to recuperate + * the resources used by the execution. + * + * @param execution The execution to be queried. + * @param index The index of the output argument we are querying. It is an index into the lists + * passed to {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not + * the index associated with {@link ANeuralNetworksModel_addOperand}. + * @param dimensions The dimension array to be filled. The size of the array must be exactly as + * large as the rank of the output operand to be queried in the model. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_OUTPUT_INSUFFICIENT_SIZE + * if the target output is provided an insufficient buffer at execution time, + * ANEURALNETWORKS_BAD_DATA if the index is invalid or if the target is a scalar. + * + * Available since API level 29. + */ +int ANeuralNetworksExecution_getOutputOperandDimensions(ANeuralNetworksExecution* execution, + int32_t index, uint32_t* dimensions) + __INTRODUCED_IN(29); + +/** + * Create a {@link ANeuralNetworksBurst} to apply the given compilation. + * This only creates the burst object. Computation is only performed once + * {@link ANeuralNetworksExecution_burstCompute} is invoked with a valid + * {@link ANeuralNetworksExecution} and {@link ANeuralNetworksBurst}. + * + *

The provided compilation must outlive the burst object.

+ * + * Available since API level 29. + * + * @param compilation The {@link ANeuralNetworksCompilation} to be evaluated. + * @param burst The newly created object or NULL if unsuccessful. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA + * if the compilation is invalid. + */ +int ANeuralNetworksBurst_create(ANeuralNetworksCompilation* compilation, + ANeuralNetworksBurst** burst) __INTRODUCED_IN(29); + +/** + * Destroys the burst object. + * + * Available since API level 29. + * + * @param burst The burst object to be destroyed. Passing NULL is acceptable and + * results in no operation. + */ +void ANeuralNetworksBurst_free(ANeuralNetworksBurst* burst) __INTRODUCED_IN(29); + +/** + * Schedule synchronous evaluation of the execution on a burst object. + * + *

Schedules synchronous evaluation of the execution. Returns once the + * execution has completed and the outputs are ready to be consumed.

+ * + *

There must be at most one {@link ANeuralNetworksExecution} processing at + * any given time for any given burst object. Any + * {@link ANeuralNetworksExecution} launched before the previous has finished + * will result in ANEURALNETWORKS_BAD_STATE.

+ * + * Available since API level 29. + * + * @param burst The burst object to execute on. + * @param execution The execution to be scheduled and executed. The execution + * must be created from the same {@link + * ANeuralNetworksCompilation} as the burst object. + * + * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally. + */ +int ANeuralNetworksExecution_burstCompute(ANeuralNetworksExecution* execution, + ANeuralNetworksBurst* burst) __INTRODUCED_IN(29); + +/** + * Creates a shared memory object from an AHardwareBuffer handle. + * + * If the shared memory is backed by an AHardwareBuffer of AHARDWAREBUFFER_FORMAT_BLOB + * format, it can be used the same way as shared memory created from a file handle. See + * {@link ANeuralNetworksMemory} for a description on how to use this shared memory. + * + * If the shared memory is backed by an AHardwareBuffer of a format other than + * AHARDWAREBUFFER_FORMAT_BLOB, it can only be used for Model inputs and outputs. + * When calling {@link ANeuralNetworksExecution_setInputFromMemory} or + * {@link ANeuralNetworksExecution_setOutputFromMemory} with the shared memory, both + * offset and length must be set to zero and the entire memory region will be + * associated with the specified input or output operand. There is no guarantee + * that an arbitrary AHardwareBuffer_Format and AHardwareBuffer_UsageFlags combination + * can be used by arbitrary devices. The execution will fail if the selected set of + * devices cannot consume the buffer. + * + * Calling {@link ANeuralNetworksModel_setOperandValueFromMemory} with shared memory + * backed by an AHardwareBuffer of a format other than AHARDWAREBUFFER_FORMAT_BLOB is + * disallowed. + * + * The provided AHardwareBuffer must outlive the ANeuralNetworksMemory object. + * + * Available since API level 29. + * + * @param ahwb The AHardwareBuffer handle. + * @param memory The memory object to be created. + * Set to NULL if unsuccessful. + * + * @return ANEURALNETWORKS_NO_ERROR if the request completed normally. + * + * @see AHardwareBuffer + */ +int ANeuralNetworksMemory_createFromAHardwareBuffer(const AHardwareBuffer* ahwb, + ANeuralNetworksMemory** memory) + __INTRODUCED_IN(29); + +/** + + * Specifies whether duration of the {@link ANeuralNetworksExecution} is to be + * measured. Evaluation of the execution must not have been scheduled. + * + * By default, duration is not measured. + * + * The {@link ANeuralNetworksExecution} must have been created with + * {@link ANeuralNetworksCompilation_createForDevices} with numDevices = 1. + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * Available since API level 29. + * + * @param execution The execution to be modified. + * @param measure 'true' if duration is to be measured, 'false' if not. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksExecution_setMeasureTiming(ANeuralNetworksExecution* execution, bool measure) + __INTRODUCED_IN(29); + +/** + * Different duration measurements. + * + * Durations are measured in nanoseconds. + * + * Available since API level 29. + */ +typedef enum { + // Execution time on hardware (not driver, which runs on host processor). + ANEURALNETWORKS_DURATION_ON_HARDWARE = 0, + // Execution time in driver (including time on hardware). Excludes overhead + // such as that of the runtime itself and the IPC needed for the runtime to + // communicate with the driver. + ANEURALNETWORKS_DURATION_IN_DRIVER = 1, +} DurationCode; + +/** + * Get the time spent in the specified {@link ANeuralNetworksExecution}, in nanoseconds. + * The execution must have completed. + * + * Available since API level 29. + * + * @param execution The execution to be queried. + * @param durationCode The measurement to be queried, specified by {@link DurationCode}. + * @param duration The returned duration. If no measurement was requested by + * {@link ANeuralNetworksExecution_setMeasureTiming}, or for some other + * reason the duration is not available, UINT64_MAX will be returned. + * A particular device need not support any given measurement. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksExecution_getDuration(const ANeuralNetworksExecution* execution, + int32_t durationCode, uint64_t* duration) + __INTRODUCED_IN(29); + +// #endif // __ANDROID_API__ >= __ANDROID_API_Q__ + +// #if __ANDROID_API__ >= 27 + +/** + * Creates a shared memory object from a file descriptor. + * + * The shared memory is backed by a file descriptor via mmap. + * See {@link ANeuralNetworksMemory} for a description on how to use + * this shared memory. + * + * Available since API level 27. + * + * @param size The requested size in bytes. + * Must not be larger than the file size. + * @param prot The desired memory protection for the mapping. + * It is either PROT_NONE or the bitwise OR of one or + * more of the following flags: PROT_READ, PROT_WRITE. + * @param fd The requested file descriptor. + * The file descriptor has to be mmap-able. The file + * descriptor will be duplicated. + * @param offset The offset to the beginning of the file of the area to map. + * The offset has to be aligned to a page size. + * @param memory The memory object to be created. + * Set to NULL if unsuccessful. + * + * @return ANEURALNETWORKS_NO_ERROR if the request completed normally. + */ +int ANeuralNetworksMemory_createFromFd(size_t size, int protect, int fd, size_t offset, + ANeuralNetworksMemory** memory) __INTRODUCED_IN(27); + +/** + * Delete a memory object. + * + * Destroys the object used by the run time to keep track of the memory. + * This will free the underlying actual memory if no other code has open + * handles to this memory. + * + * Available since API level 27. + * + * @param memory The memory object to be freed. Passing NULL is acceptable and + * results in no operation. + */ +void ANeuralNetworksMemory_free(ANeuralNetworksMemory* memory) __INTRODUCED_IN(27); + +/** + * Create an empty {@link ANeuralNetworksModel}. + * + *

This only creates the object. Computation is performed once + * {@link ANeuralNetworksExecution_compute} or + * {@link ANeuralNetworksExecution_startCompute} is invoked. + * + * The model should be constructed with calls to + * {@link ANeuralNetworksModel_addOperation} and + * {@link ANeuralNetworksModel_addOperand} + * + *

{@link ANeuralNetworksModel_finish} should be called once the model + * has been fully constructed.

+ * + *

{@link ANeuralNetworksModel_free} should be called once the model + * is no longer needed.

+ * + * Available since API level 27. + * + * @param model The {@link ANeuralNetworksModel} to be created. + * Set to NULL if unsuccessful. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksModel_create(ANeuralNetworksModel** model) __INTRODUCED_IN(27); + +/** + * Destroy a model. + * + * The model need not have been finished by a call to + * {@link ANeuralNetworksModel_finish}. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param model The model to be destroyed. Passing NULL is acceptable and + * results in no operation. + */ +void ANeuralNetworksModel_free(ANeuralNetworksModel* model) __INTRODUCED_IN(27); + +/** + * Indicate that we have finished modifying a model. Required before + * calling {@link ANeuralNetworksCompilation_create} and + * {@link ANeuralNetworksCompilation_createForDevices}. + * + * An application must ensure that no other thread uses the model at the same + * time. + * + * This function must only be called once for a given model. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param model The model to be finished. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksModel_finish(ANeuralNetworksModel* model) __INTRODUCED_IN(27); + +/** + * Add an operand to a model. + * + * The order in which the operands are added is important. The first one added + * to a model will have the index value 0, the second 1, etc. These indexes are + * used as operand identifiers in + * {@link ANeuralNetworksModel_addOperation}, + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}, + * {@link ANeuralNetworksModel_setOperandValue}, + * {@link ANeuralNetworksModel_setOperandValueFromMemory}, + * {@link ANeuralNetworksExecution_setInput}, + * {@link ANeuralNetworksExecution_setInputFromMemory}, + * {@link ANeuralNetworksExecution_setOutput}, + * {@link ANeuralNetworksExecution_setOutputFromMemory} and + * {@link ANeuralNetworksExecution_setOperandValue}. + * + *

Every operand must be referenced in exactly one of the following + * ways:

    + *
  • It is identified as a model input with + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}.
    • + *
  • It is identified as a constant with + * {@link ANeuralNetworksModel_setOperandValue} or + * {@link ANeuralNetworksModel_setOperandValueFromMemory}.
    • + *
  • It is identified as an output of exactly one operation with + * {@link ANeuralNetworksModel_addOperation}.

    • + *

    An operand that is identified as a model input or as a constant + * must not also be identified as a model output with + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}.

    + * + * To build a model that can accommodate inputs of various sizes, as + * you may want to do for a CNN, leave unspecified the dimensions that + * will vary at run time. If you do so, fully specify dimensions + * when calling {@link ANeuralNetworksExecution_setInput} or + * {@link ANeuralNetworksExecution_setInputFromMemory}. + * + * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been + * called will return an error. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param model The model to be modified. + * @param type The {@link ANeuralNetworksOperandType} that describes the shape + * of the operand. Neither the {@link ANeuralNetworksOperandType} + * nor the dimensions it points to need to outlive the call to + * {@link ANeuralNetworksModel_addOperand}. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksModel_addOperand(ANeuralNetworksModel* model, + const ANeuralNetworksOperandType* type) __INTRODUCED_IN(27); + +/** + * Sets an operand to a constant value. + * + * Values of length smaller or equal to + * {@link ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES} + * are immediately copied into the model. + * + * For values of length greater than + * {@link ANEURALNETWORKS_MAX_SIZE_OF_IMMEDIATELY_COPIED_VALUES}, a pointer to + * the buffer is stored within the model. The application must not change the + * content of this region until all executions using this model have + * completed. As the data may be copied during processing, modifying the data + * after this call yields undefined results. The provided buffer must outlive + * this model. + * + * For large tensors, using {@link ANeuralNetworksModel_setOperandValueFromMemory} + * is likely to be more efficient. + * + * To indicate that an optional operand should be considered missing, + * pass nullptr for buffer and 0 for length. + * + * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been + * called will return an error. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param model The model to be modified. + * @param index The index of the model operand we're setting. + * @param buffer A pointer to the data to use. + * @param length The size in bytes of the data value. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksModel_setOperandValue(ANeuralNetworksModel* model, int32_t index, + const void* buffer, size_t length) __INTRODUCED_IN(27); + +// #if __ANDROID_API__ >= __ANDROID_API_Q__ + +/** + * Sets an operand's per channel quantization parameters. + * + * Sets parameters required by a tensor of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL}. + * This function must be called for every tensor of type + * {@link ANEURALNETWORKS_TENSOR_QUANT8_SYMM_PER_CHANNEL} before + * calling {@link ANeuralNetworksModel_finish}. + * + * Available since API level 29. + * + * @param model The model to be modified. + * @param index The index of the model operand we're setting. + * @param channelQuant The per channel quantization parameters for the operand. + * No memory in this struct needs to outlive the call to + * this function. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksModel_setOperandSymmPerChannelQuantParams( + ANeuralNetworksModel* model, int32_t index, + const ANeuralNetworksSymmPerChannelQuantParams* channelQuant) __INTRODUCED_IN(29); + +// #endif // __ANDROID_API__ >= __ANDROID_API_Q__ + +/** + * Sets an operand to a value stored in a memory object. + * + * The content of the memory is not copied. A reference to that memory is stored + * inside the model. The application must not change the content of the memory + * region until all executions using this model have completed. As the data may + * be copied during processing, modifying the data after this call yields + * undefined results. + * + *

    The provided memory must outlive this model.

    + * + * To indicate that an optional operand should be considered missing, + * use {@link ANeuralNetworksModel_setOperandValue} instead, passing nullptr for buffer. + * + * Is disallowed to set an operand value with shared memory backed by an AHardwareBuffer + * of a format other than AHARDWAREBUFFER_FORMAT_BLOB. + * + * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been + * called will return an error. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + * See {@link ANeuralNetworksMemory_createFromAHardwareBuffer} for information on + * AHardwareBuffer usage. + * + * Available since API level 27. + * + * @param model The model to be modified. + * @param index The index of the model operand we're setting. + * @param buffer A pointer to the data to use. + * @param memory The memory containing the data. + * @param offset This specifies the location of the data within the memory. + * The offset is in bytes from the start of memory. + * @param length The size in bytes of the data value. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksModel_setOperandValueFromMemory(ANeuralNetworksModel* model, int32_t index, + const ANeuralNetworksMemory* memory, + size_t offset, size_t length) + __INTRODUCED_IN(27); + +/** + * Add an operation to a model. + * + * @param model The model to be modified. + * @param type The {@link ANeuralNetworksOperationType} of the operation. + * @param inputCount The number of entries in the inputs array. + * @param inputs An array of indexes identifying each operand. + * @param outputCount The number of entries in the outputs array. + * @param outputs An array of indexes identifying each operand. + * + * The operands specified by inputs and outputs must have been + * previously added by calls to {@link ANeuralNetworksModel_addOperand}. + * + * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been + * called will return an error. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + * + * Available since API level 27. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksModel_addOperation(ANeuralNetworksModel* model, + ANeuralNetworksOperationType type, uint32_t inputCount, + const uint32_t* inputs, uint32_t outputCount, + const uint32_t* outputs) __INTRODUCED_IN(27); + +/** + * Specifies which operands will be the model's inputs and + * outputs. Every model must have at least one input and one output. + * + * An operand cannot be used for both input and output. Doing so will + * return an error. + * + * @param model The model to be modified. + * @param inputCount The number of entries in the inputs array. + * @param inputs An array of indexes identifying the input operands. + * @param outputCount The number of entries in the outputs array. + * @param outputs An array of indexes identifying the output operands. + * + * The operands specified by inputs and outputs must have been + * previously added by calls to {@link ANeuralNetworksModel_addOperand}. + * + * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been + * called will return an error. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + * + * Available since API level 27. + * + */ +int ANeuralNetworksModel_identifyInputsAndOutputs(ANeuralNetworksModel* model, uint32_t inputCount, + const uint32_t* inputs, uint32_t outputCount, + const uint32_t* outputs) __INTRODUCED_IN(27); + +// #if __ANDROID_API__ >= 28 + +/** + * Specifies whether {@link ANEURALNETWORKS_TENSOR_FLOAT32} is allowed to be + * calculated with range and/or precision as low as that of the IEEE 754 16-bit + * floating-point format. By default, {@link ANEURALNETWORKS_TENSOR_FLOAT32} + * must be calculated using at least the range and precision of the IEEE 754 + * 32-bit floating-point format. + * + * @param model The model to be modified. + * @param allow 'true' indicates {@link ANEURALNETWORKS_TENSOR_FLOAT32} may be + * calculated with range and/or precision as low as that of the + * IEEE 754 16-bit floating point format. 'false' indicates + * {@link ANEURALNETWORKS_TENSOR_FLOAT32} must be calculated using + * at least the range and precision of the IEEE 754 32-bit floating + * point format. + * + * Attempting to modify a model once {@link ANeuralNetworksModel_finish} has been + * called will return an error. + * + * Available since API level 28. + * + * See {@link ANeuralNetworksModel} for information on multithreaded usage. + */ +int ANeuralNetworksModel_relaxComputationFloat32toFloat16(ANeuralNetworksModel* model, bool allow) + __INTRODUCED_IN(28); + +// #endif // __ANDROID_API__ >= 28 + +/** + * Create a {@link ANeuralNetworksCompilation} to compile the given model. + * + *

    This only creates the object. Compilation is only performed once + * {@link ANeuralNetworksCompilation_finish} is invoked.

    + * + *

    {@link ANeuralNetworksCompilation_finish} should be called once + * all desired properties have been set on the compilation.

    + * + *

    {@link ANeuralNetworksModel_free} should be called once the compilation + * is no longer needed.

    + * + *

    The provided model must outlive the compilation.

    + * + * The model must already have been finished by a call to + * {@link ANeuralNetworksModel_finish}. + * + * See {@link ANeuralNetworksCompilation} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param model The {@link ANeuralNetworksModel} to be compiled. + * @param compilation The newly created object or NULL if unsuccessful. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA + * if the model is invalid. + */ +int ANeuralNetworksCompilation_create(ANeuralNetworksModel* model, + ANeuralNetworksCompilation** compilation) __INTRODUCED_IN(27); + +/** + * Destroy a compilation. + * + * The compilation need not have been finished by a call to + * {@link ANeuralNetworksCompilation_finish}. + * + * See {@link ANeuralNetworksCompilation} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param compilation The compilation to be destroyed. Passing NULL is acceptable and + * results in no operation. + */ +void ANeuralNetworksCompilation_free(ANeuralNetworksCompilation* compilation) __INTRODUCED_IN(27); + +/** + * Sets the execution preference. + * + *

    Provides guidance to the runtime when trade-offs are possible. By default the runtime + * uses PREFER_SINGLE_FAST_ANSWER

    + * + * See {@link ANeuralNetworksCompilation} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param compilation The compilation to be modified. + * @param preference Either {@link PREFER_LOW_POWER}, + * {@link PREFER_SINGLE_FAST_ANSWER}, or + * {@link PREFER_SUSTAINED_SPEED}. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksCompilation_setPreference(ANeuralNetworksCompilation* compilation, + int32_t preference) __INTRODUCED_IN(27); + +/** + * Indicate that we have finished modifying a compilation. Required before + * calling {@link ANeuralNetworksExecution_create}. + * + * An application must ensure that no other thread uses the compilation at the + * same time. + * + * This function must only be called once for a given compilation. + * + * See {@link ANeuralNetworksCompilation} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param compilation The compilation to be finished. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksCompilation_finish(ANeuralNetworksCompilation* compilation) __INTRODUCED_IN(27); + +/** + * Create a {@link ANeuralNetworksExecution} to apply the given compilation. + * This only creates the object. Computation is only performed once + * {@link ANeuralNetworksExecution_compute} or + * {@link ANeuralNetworksExecution_startCompute} is invoked. + * + *

    The provided compilation must outlive the execution.

    + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param compilation The {@link ANeuralNetworksCompilation} to be evaluated. + * @param execution The newly created object or NULL if unsuccessful. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA + * if the compilation is invalid. + */ +int ANeuralNetworksExecution_create(ANeuralNetworksCompilation* compilation, + ANeuralNetworksExecution** execution) __INTRODUCED_IN(27); + +/** + * Destroy an execution. + * + *

    The execution need not have been scheduled by a call to + * {@link ANeuralNetworksExecution_burstCompute}, + * {@link ANeuralNetworksExecution_compute}, or + * {@link ANeuralNetworksExecution_startCompute}; but if it has been scheduled, + * then the application must not call {@link ANeuralNetworksExecution_free} + * until the execution has completed (i.e., + * {@link ANeuralNetworksExecution_burstCompute}, + * {@link ANeuralNetworksExecution_compute}, or + * {@link ANeuralNetworksEvent_wait} has returned). + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param execution The execution to be destroyed. Passing NULL is acceptable and + * results in no operation. + */ +void ANeuralNetworksExecution_free(ANeuralNetworksExecution* execution) __INTRODUCED_IN(27); + +/** + * Associate a user buffer with an input of the model of the + * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have + * been scheduled. Once evaluation of the execution has been scheduled, the + * application must not change the content of the buffer until the execution has + * completed. Evaluation of the execution will not change the content of the + * buffer. + * + *

    The provided buffer must outlive the execution.

    + * + * If the input is optional, you can indicate that it is omitted by + * passing nullptr for buffer and 0 for length. + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param execution The execution to be modified. + * @param index The index of the input argument we are setting. It is + * an index into the lists passed to + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not + * the index associated with + * {@link ANeuralNetworksModel_addOperand}. + * @param type The {@link ANeuralNetworksOperandType} of the + * operand. Unless the input is omitted, this should be + * used to specify the dimensions that were left + * unspecified when the operand was added to the + * model. All other properties of the type must be the + * same as specified in the model. If the type is the same + * as specified when the model was built, NULL can be + * passed. Neither the {@link ANeuralNetworksOperandType} + * nor the dimensions it points to need to outlive the call + * to {@link ANeuralNetworksExecution_setInput}. + * @param buffer The buffer containing the data. + * @param length The length in bytes of the buffer. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the + * name is not recognized or the buffer is too small for the input. + */ +int ANeuralNetworksExecution_setInput(ANeuralNetworksExecution* execution, int32_t index, + const ANeuralNetworksOperandType* type, const void* buffer, + size_t length) __INTRODUCED_IN(27); + +/** + * Associate a region of a memory object with an input of the model of the + * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have + * been scheduled. Once evaluation of the execution has been scheduled, the + * application must not change the content of the region until the execution has + * completed. Evaluation of the execution will not change the content of the + * region. + * + *

    The provided memory must outlive the execution.

    + * + * If the input is optional, you can indicate that it is omitted by + * using {@link ANeuralNetworksExecution_setInput} instead, passing nullptr for + * buffer and 0 for length. + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * See {@link ANeuralNetworksMemory_createFromAHardwareBuffer} for information on + * AHardwareBuffer usage. + * + * Available since API level 27. + * + * @param execution The execution to be modified. + * @param index The index of the input argument we are setting. It is + * an index into the lists passed to + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not + * the index associated with {@link ANeuralNetworksModel_addOperand}. + * @param type The {@link ANeuralNetworksOperandType} of the + * operand. This should be used to specify the dimensions + * that were left unspecified when the operand was added + * to the model. All other properties of the type must be + * the same as specified in the model. If the type is the + * same as specified when the model was built, NULL can be + * passed. Neither the {@link ANeuralNetworksOperandType} + * nor the dimensions it points to need to outlive the call + * to {@link ANeuralNetworksExecution_setInputFromMemory}. + * @param memory The memory containing the data. + * @param offset This specifies the location of the data within the memory. + * The offset is in bytes from the start of memory. + * @param length The size in bytes of the data value. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the + * name is not recognized or the buffer is too small for the input. + */ +int ANeuralNetworksExecution_setInputFromMemory(ANeuralNetworksExecution* execution, int32_t index, + const ANeuralNetworksOperandType* type, + const ANeuralNetworksMemory* memory, size_t offset, + size_t length) __INTRODUCED_IN(27); + +/** + * Associate a user buffer with an output of the model of the + * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have + * been scheduled. Once evaluation of the execution has been scheduled, the + * application must not change the content of the buffer until the execution has + * completed. + * + * If the output is optional, you can indicate that it is omitted by + * passing nullptr for buffer and 0 for length. + * + *

    The provided buffer must outlive the execution.

    + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param execution The execution to be modified. + * @param index The index of the output argument we are setting. It is + * an index into the lists passed to + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not + * the index associated with {@link ANeuralNetworksModel_addOperand}. + * @param type The {@link ANeuralNetworksOperandType} of the + * operand. Unless the output is omitted, this should be + * used to specify the dimensions that were left + * unspecified when the operand was added to the + * model. All other properties of the type must be the + * same as specified in the model. If the type is the same + * as specified when the model was built, NULL can be + * passed. Neither the {@link ANeuralNetworksOperandType} + * nor the dimensions it points to need to outlive the call + * to {@link ANeuralNetworksExecution_setOutput}. + * Since API level 29, the output operand can have unspecified + * dimensions or rank to be deduced dynamically during the execution. + * However, the user must provide a large enough buffer. The user + * can retrieve the output dimensional information after the execution + * by {@link ANeuralNetworksExecution_getOutputOperandRank} and + * {@link ANeuralNetworksExecution_getOutputOperandDimensions}. + * @param buffer The buffer where the data is to be written. + * @param length The length in bytes of the buffer. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the + * name is not recognized or the buffer is too small for the output. + */ +int ANeuralNetworksExecution_setOutput(ANeuralNetworksExecution* execution, int32_t index, + const ANeuralNetworksOperandType* type, void* buffer, + size_t length) __INTRODUCED_IN(27); + +/** + * Associate a region of a memory object with an output of the model of the + * {@link ANeuralNetworksExecution}. Evaluation of the execution must not have + * been scheduled. Once evaluation of the execution has been scheduled, the + * application must not change the content of the region until the execution has + * completed. + * + * If the output is optional, you can indicate that it is omitted by + * using {@link ANeuralNetworksExecution_setOutput} instead, passing nullptr for + * buffer and 0 for length. + * + *

    The provided memory must outlive the execution.

    + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * See {@link ANeuralNetworksMemory_createFromAHardwareBuffer} for information on + * AHardwareBuffer usage. + * + * Available since API level 27. + * + * @param execution The execution to be modified. + * @param index The index of the output argument we are setting. It is + * an index into the lists passed to + * {@link ANeuralNetworksModel_identifyInputsAndOutputs}. It is not + * the index associated with {@link ANeuralNetworksModel_addOperand}. + * @param type The {@link ANeuralNetworksOperandType} of the operand. This should be + * used to specify the dimensions that were left + * unspecified when the operand was added to the + * model. All other properties of the type must be the + * same as specified in the model. If the type is the same + * as specified when the model was built, NULL can be + * passed. Neither the {@link ANeuralNetworksOperandType} + * nor the dimensions it points to need to outlive the call + * to {@link ANeuralNetworksExecution_setOutputFromMemory}. + * Since API level 29, the output operand can have unspecified + * dimensions or rank to be deduced dynamically during the execution. + * However, the user must provide a large enough memory. The user + * can retrieve the output dimensional information after the execution + * by {@link ANeuralNetworksExecution_getOutputOperandRank} and + * {@link ANeuralNetworksExecution_getOutputOperandDimensions}. + * @param memory The memory where the data is to be stored. + * @param offset This specifies the location of the data within the memory. + * The offset is in bytes from the start of memory. + * @param length The length in bytes of the data value. + * + * @return ANEURALNETWORKS_NO_ERROR if successful, ANEURALNETWORKS_BAD_DATA if the + * name is not recognized or the buffer is too small for the output. + */ +int ANeuralNetworksExecution_setOutputFromMemory(ANeuralNetworksExecution* execution, int32_t index, + const ANeuralNetworksOperandType* type, + const ANeuralNetworksMemory* memory, size_t offset, + size_t length) __INTRODUCED_IN(27); + +/** + * Schedule asynchronous evaluation of the execution. + * + *

    Schedules asynchronous evaluation of the execution. Once the model has + * been applied and the outputs are ready to be consumed, the returned event + * will be signaled. Use {@link ANeuralNetworksEvent_wait} to wait for that + * event. + *

    + * + * ANeuralNetworksEvent_wait must be called to recuperate the resources used + * by the execution. + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * See {@link ANeuralNetworksExecution_compute} for synchronous execution. + * Synchronous execution incurs lower overhead than asynchronous execution. + * + * Available since API level 27. + * + * @param execution The execution to be scheduled and executed. + * @param event The event that will be signaled on completion. event is set to + * NULL if there's an error. + * + * @return ANEURALNETWORKS_NO_ERROR if successful. + */ +int ANeuralNetworksExecution_startCompute(ANeuralNetworksExecution* execution, + ANeuralNetworksEvent** event) __INTRODUCED_IN(27); + +/** + * Waits until the execution completes. + * + * More than one thread can wait on an event. When the execution completes, + * all threads will be released. + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * Available since API level 27. + * + * @return ANEURALNETWORKS_NO_ERROR if the execution completed normally. + * ANEURALNETWORKS_UNMAPPABLE if the execution input or output memory cannot + * be properly mapped. + */ +int ANeuralNetworksEvent_wait(ANeuralNetworksEvent* event) __INTRODUCED_IN(27); + +/** + * Destroys the event. + * + * See {@link ANeuralNetworksExecution} for information on multithreaded usage. + * + * Available since API level 27. + * + * @param event The event object to be destroyed. Passing NULL is acceptable and + * results in no operation. + */ +void ANeuralNetworksEvent_free(ANeuralNetworksEvent* event) __INTRODUCED_IN(27); + +// #endif // __ANDROID_API__ >= 27 + +__END_DECLS + +#endif // ANDROID_FRAMEWORKS_ML_NN_RUNTIME_NEURAL_NETWORKS_H + +/** @} */ diff --git a/source/backend/nnapi/backend/NNAPIOPRegister.cpp b/source/backend/nnapi/backend/NNAPIOPRegister.cpp new file mode 100644 index 000000000..c3ff92816 --- /dev/null +++ b/source/backend/nnapi/backend/NNAPIOPRegister.cpp @@ -0,0 +1,18 @@ +// This file is generated by Shell for ops register +namespace MNN { +extern void ___NNAPIUnary__OpType_UnaryOp__(); +extern void ___NNAPISoftmax__OpType_Softmax__(); +extern void ___NNAPIConvolution__OpType_Convolution__(); +extern void ___NNAPIConvolution__OpType_ConvolutionDepthwise__(); +extern void ___NNAPIBinary__OpType_BinaryOp__(); +extern void ___NNAPIPool__OpType_Pooling__(); + +void registerNNAPIOps() { +___NNAPIUnary__OpType_UnaryOp__(); +___NNAPISoftmax__OpType_Softmax__(); +___NNAPIConvolution__OpType_Convolution__(); +___NNAPIConvolution__OpType_ConvolutionDepthwise__(); +___NNAPIBinary__OpType_BinaryOp__(); +___NNAPIPool__OpType_Pooling__(); +} +} diff --git a/source/backend/nnapi/backend/NNAPISymbol.cpp b/source/backend/nnapi/backend/NNAPISymbol.cpp new file mode 100644 index 000000000..f35d7df11 --- /dev/null +++ b/source/backend/nnapi/backend/NNAPISymbol.cpp @@ -0,0 +1,103 @@ +// +// NNAPISymbol.cpp +// MNN +// +// Created by MNN on 2022/09/19. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPISymbol.hpp" +#include "NNAPIDefine.hpp" +#include +#include + +namespace MNN { + +#define LOAD_SYM(NAME, API_LEVEL) \ + NAME ## _ ## API_LEVEL = reinterpret_cast(dlsym(lib, #NAME)); \ + if (NAME ## _ ## API_LEVEL == nullptr) { \ + MNN_PRINT("[NNAPI] Load symbol %s failed.", #NAME); \ + return false; \ + } + +bool loadNNAPISymbol() { + if (ANDROID_API_LEVEL < 29) { + return false; + } + void *lib = dlopen("libneuralnetworks.so", RTLD_NOW | RTLD_LOCAL); + if (lib == nullptr) { + return false; + } + LOAD_SYM(ANeuralNetworksModel_getSupportedOperationsForDevices, 29); + LOAD_SYM(ANeuralNetworks_getDeviceCount, 29); + LOAD_SYM(ANeuralNetworks_getDevice, 29); + LOAD_SYM(ANeuralNetworksDevice_getName, 29); + LOAD_SYM(ANeuralNetworksDevice_getType, 29); + LOAD_SYM(ANeuralNetworksCompilation_createForDevices, 29); + LOAD_SYM(ANeuralNetworksExecution_compute, 29); + LOAD_SYM(ANeuralNetworksBurst_create, 29); + LOAD_SYM(ANeuralNetworksBurst_free, 29); + LOAD_SYM(ANeuralNetworksExecution_burstCompute, 29); + LOAD_SYM(ANeuralNetworksModel_create, 27); + LOAD_SYM(ANeuralNetworksModel_free, 27); + LOAD_SYM(ANeuralNetworksModel_finish, 27); + LOAD_SYM(ANeuralNetworksModel_addOperand, 27); + LOAD_SYM(ANeuralNetworksModel_setOperandValue, 27); + LOAD_SYM(ANeuralNetworksModel_setOperandSymmPerChannelQuantParams, 29); + LOAD_SYM(ANeuralNetworksModel_addOperation, 27); + LOAD_SYM(ANeuralNetworksModel_identifyInputsAndOutputs, 27); + LOAD_SYM(ANeuralNetworksCompilation_create, 27); + LOAD_SYM(ANeuralNetworksCompilation_free, 27); + LOAD_SYM(ANeuralNetworksCompilation_setPreference, 27); + LOAD_SYM(ANeuralNetworksCompilation_finish, 27); + LOAD_SYM(ANeuralNetworksExecution_create, 27); + LOAD_SYM(ANeuralNetworksExecution_free, 27); + LOAD_SYM(ANeuralNetworksExecution_setInput, 27); + LOAD_SYM(ANeuralNetworksExecution_setInputFromMemory, 27); + LOAD_SYM(ANeuralNetworksExecution_setOutput, 27); + LOAD_SYM(ANeuralNetworksExecution_setOutputFromMemory, 27); + LOAD_SYM(ANeuralNetworksExecution_startCompute, 27); + LOAD_SYM(ANeuralNetworksEvent_wait, 27); + LOAD_SYM(ANeuralNetworksEvent_free, 27); + LOAD_SYM(ANeuralNetworksDevice_getVersion, 29); + LOAD_SYM(ANeuralNetworksMemory_createFromAHardwareBuffer, 29); + LOAD_SYM(ANeuralNetworksMemory_createFromFd, 27); + LOAD_SYM(ANeuralNetworksMemory_free, 27); + return true; +} +MNN_ANeuralNetworksModel_getSupportedOperationsForDevices *ANeuralNetworksModel_getSupportedOperationsForDevices_29 = nullptr; +MNN_ANeuralNetworks_getDeviceCount *ANeuralNetworks_getDeviceCount_29 = nullptr; +MNN_ANeuralNetworks_getDevice *ANeuralNetworks_getDevice_29 = nullptr; +MNN_ANeuralNetworksDevice_getName *ANeuralNetworksDevice_getName_29 = nullptr; +MNN_ANeuralNetworksDevice_getType *ANeuralNetworksDevice_getType_29 = nullptr; +MNN_ANeuralNetworksCompilation_createForDevices *ANeuralNetworksCompilation_createForDevices_29 = nullptr; +MNN_ANeuralNetworksExecution_compute *ANeuralNetworksExecution_compute_29 = nullptr; +MNN_ANeuralNetworksBurst_create *ANeuralNetworksBurst_create_29 = nullptr; +MNN_ANeuralNetworksBurst_free *ANeuralNetworksBurst_free_29 = nullptr; +MNN_ANeuralNetworksExecution_burstCompute *ANeuralNetworksExecution_burstCompute_29 = nullptr; +MNN_ANeuralNetworksModel_create *ANeuralNetworksModel_create_27 = nullptr; +MNN_ANeuralNetworksModel_finish *ANeuralNetworksModel_finish_27 = nullptr; +MNN_ANeuralNetworksModel_free *ANeuralNetworksModel_free_27 = nullptr; +MNN_ANeuralNetworksModel_addOperand *ANeuralNetworksModel_addOperand_27 = nullptr; +MNN_ANeuralNetworksModel_setOperandValue *ANeuralNetworksModel_setOperandValue_27 = nullptr; +MNN_ANeuralNetworksModel_setOperandSymmPerChannelQuantParams *ANeuralNetworksModel_setOperandSymmPerChannelQuantParams_29; +MNN_ANeuralNetworksModel_addOperation *ANeuralNetworksModel_addOperation_27 = nullptr; +MNN_ANeuralNetworksModel_identifyInputsAndOutputs *ANeuralNetworksModel_identifyInputsAndOutputs_27 = nullptr; +MNN_ANeuralNetworksCompilation_create *ANeuralNetworksCompilation_create_27 = nullptr; +MNN_ANeuralNetworksCompilation_free *ANeuralNetworksCompilation_free_27 = nullptr; +MNN_ANeuralNetworksCompilation_setPreference *ANeuralNetworksCompilation_setPreference_27 = nullptr; +MNN_ANeuralNetworksCompilation_finish *ANeuralNetworksCompilation_finish_27 = nullptr; +MNN_ANeuralNetworksExecution_create *ANeuralNetworksExecution_create_27 = nullptr; +MNN_ANeuralNetworksExecution_free *ANeuralNetworksExecution_free_27 = nullptr; +MNN_ANeuralNetworksExecution_setInput *ANeuralNetworksExecution_setInput_27 = nullptr; +MNN_ANeuralNetworksExecution_setInputFromMemory *ANeuralNetworksExecution_setInputFromMemory_27 = nullptr; +MNN_ANeuralNetworksExecution_setOutput *ANeuralNetworksExecution_setOutput_27 = nullptr; +MNN_ANeuralNetworksExecution_setOutputFromMemory *ANeuralNetworksExecution_setOutputFromMemory_27 = nullptr; +MNN_ANeuralNetworksExecution_startCompute *ANeuralNetworksExecution_startCompute_27 = nullptr; +MNN_ANeuralNetworksEvent_wait *ANeuralNetworksEvent_wait_27 = nullptr; +MNN_ANeuralNetworksEvent_free *ANeuralNetworksEvent_free_27 = nullptr; +MNN_ANeuralNetworksDevice_getVersion *ANeuralNetworksDevice_getVersion_29 = nullptr; +MNN_ANeuralNetworksMemory_createFromAHardwareBuffer *ANeuralNetworksMemory_createFromAHardwareBuffer_29 = nullptr; +MNN_ANeuralNetworksMemory_createFromFd *ANeuralNetworksMemory_createFromFd_27 = nullptr; +MNN_ANeuralNetworksMemory_free *ANeuralNetworksMemory_free_27 = nullptr; +} \ No newline at end of file diff --git a/source/backend/nnapi/backend/NNAPISymbol.hpp b/source/backend/nnapi/backend/NNAPISymbol.hpp new file mode 100644 index 000000000..3784538b2 --- /dev/null +++ b/source/backend/nnapi/backend/NNAPISymbol.hpp @@ -0,0 +1,89 @@ +// +// NNAPISymbol.hpp +// MNN +// +// Created by MNN on 2022/09/19. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef NNAPISymbols_h +#define NNAPISymbols_h +#include "NNAPIDefine.hpp" + +namespace MNN { +// typedef the function in nnapi will be used +typedef int (MNN_ANeuralNetworksModel_getSupportedOperationsForDevices)(const ANeuralNetworksModel* model, const ANeuralNetworksDevice* const* devices, uint32_t numDevices, bool* supportedOps); +typedef int (MNN_ANeuralNetworks_getDeviceCount)(uint32_t* numDevices); +typedef int (MNN_ANeuralNetworks_getDevice)(uint32_t devIndex, ANeuralNetworksDevice** device); +typedef int (MNN_ANeuralNetworksDevice_getName)(const ANeuralNetworksDevice* device, const char** name); +typedef int (MNN_ANeuralNetworksDevice_getType)(const ANeuralNetworksDevice* device, int32_t* type); +typedef int (MNN_ANeuralNetworksCompilation_createForDevices)(ANeuralNetworksModel* model, const ANeuralNetworksDevice* const* devices, uint32_t numDevices, ANeuralNetworksCompilation** compilation); +typedef int (MNN_ANeuralNetworksExecution_compute)(ANeuralNetworksExecution* execution); +typedef int (MNN_ANeuralNetworksBurst_create)(ANeuralNetworksCompilation* compilation, ANeuralNetworksBurst** burst); +typedef void (MNN_ANeuralNetworksBurst_free)(ANeuralNetworksBurst* burst); +typedef int (MNN_ANeuralNetworksExecution_burstCompute)(ANeuralNetworksExecution* execution, ANeuralNetworksBurst* burst); +typedef int (MNN_ANeuralNetworksModel_create)(ANeuralNetworksModel** model); +typedef void (MNN_ANeuralNetworksModel_free)(ANeuralNetworksModel* model); +typedef int (MNN_ANeuralNetworksModel_finish)(ANeuralNetworksModel* model); +typedef int (MNN_ANeuralNetworksModel_addOperand)(ANeuralNetworksModel* model, const ANeuralNetworksOperandType* type); +typedef int (MNN_ANeuralNetworksModel_setOperandValue)(ANeuralNetworksModel* model, int32_t index, const void* buffer, size_t length); +typedef int (MNN_ANeuralNetworksModel_setOperandSymmPerChannelQuantParams)(ANeuralNetworksModel* model, int32_t index, const ANeuralNetworksSymmPerChannelQuantParams* channelQuant); +typedef int (MNN_ANeuralNetworksModel_addOperation)(ANeuralNetworksModel* model, ANeuralNetworksOperationType type, uint32_t inputCount, const uint32_t* inputs, uint32_t outputCount, const uint32_t* outputs); +typedef int (MNN_ANeuralNetworksModel_identifyInputsAndOutputs)(ANeuralNetworksModel* model, uint32_t inputCount, const uint32_t* inputs, uint32_t outputCount, const uint32_t* outputs); +typedef int (MNN_ANeuralNetworksCompilation_create)(ANeuralNetworksModel* model, ANeuralNetworksCompilation** compilation); +typedef void (MNN_ANeuralNetworksCompilation_free)(ANeuralNetworksCompilation* compilation); +typedef int (MNN_ANeuralNetworksCompilation_setPreference)(ANeuralNetworksCompilation* compilation, int32_t preference); +typedef int (MNN_ANeuralNetworksCompilation_finish)(ANeuralNetworksCompilation* compilation); +typedef int (MNN_ANeuralNetworksExecution_create)(ANeuralNetworksCompilation* compilation, ANeuralNetworksExecution** execution); +typedef void (MNN_ANeuralNetworksExecution_free)(ANeuralNetworksExecution* execution); +typedef int (MNN_ANeuralNetworksExecution_setInput)(ANeuralNetworksExecution* execution, int32_t index, const ANeuralNetworksOperandType* type, const void* buffer, size_t length); +typedef int (MNN_ANeuralNetworksExecution_setInputFromMemory)(ANeuralNetworksExecution* execution, int32_t index, const ANeuralNetworksOperandType* type, const ANeuralNetworksMemory* memory, size_t offset, size_t length); +typedef int (MNN_ANeuralNetworksExecution_setOutput)(ANeuralNetworksExecution* execution, int32_t index, const ANeuralNetworksOperandType* type, void* buffer, size_t length); +typedef int (MNN_ANeuralNetworksExecution_setOutputFromMemory)(ANeuralNetworksExecution* execution, int32_t index, const ANeuralNetworksOperandType* type, const ANeuralNetworksMemory* memory, size_t offset, size_t length); +typedef int (MNN_ANeuralNetworksExecution_startCompute)(ANeuralNetworksExecution* execution, ANeuralNetworksEvent** event); +typedef int (MNN_ANeuralNetworksEvent_wait)(ANeuralNetworksEvent* event); +typedef void (MNN_ANeuralNetworksEvent_free)(ANeuralNetworksEvent* event); +typedef int (MNN_ANeuralNetworksDevice_getVersion)(const ANeuralNetworksDevice* device, const char** version); +typedef int (MNN_ANeuralNetworksMemory_createFromAHardwareBuffer)(const AHardwareBuffer* ahwb, ANeuralNetworksMemory** memory); +typedef int (MNN_ANeuralNetworksMemory_createFromFd)(size_t size, int protect, int fd, size_t offset, ANeuralNetworksMemory **memory); +typedef void (MNN_ANeuralNetworksMemory_free)(ANeuralNetworksMemory* memory); + +// symbols +bool loadNNAPISymbol(); +extern MNN_ANeuralNetworksModel_getSupportedOperationsForDevices *ANeuralNetworksModel_getSupportedOperationsForDevices_29; +extern MNN_ANeuralNetworks_getDeviceCount *ANeuralNetworks_getDeviceCount_29; +extern MNN_ANeuralNetworks_getDevice *ANeuralNetworks_getDevice_29; +extern MNN_ANeuralNetworksDevice_getName *ANeuralNetworksDevice_getName_29; +extern MNN_ANeuralNetworksDevice_getType *ANeuralNetworksDevice_getType_29; +extern MNN_ANeuralNetworksCompilation_createForDevices *ANeuralNetworksCompilation_createForDevices_29; +extern MNN_ANeuralNetworksExecution_compute *ANeuralNetworksExecution_compute_29; +extern MNN_ANeuralNetworksBurst_create *ANeuralNetworksBurst_create_29; +extern MNN_ANeuralNetworksBurst_free *ANeuralNetworksBurst_free_29; +extern MNN_ANeuralNetworksExecution_burstCompute *ANeuralNetworksExecution_burstCompute_29; +extern MNN_ANeuralNetworksModel_create *ANeuralNetworksModel_create_27; +extern MNN_ANeuralNetworksModel_free *ANeuralNetworksModel_free_27; +extern MNN_ANeuralNetworksModel_finish *ANeuralNetworksModel_finish_27; +extern MNN_ANeuralNetworksModel_addOperand *ANeuralNetworksModel_addOperand_27; +extern MNN_ANeuralNetworksModel_setOperandValue *ANeuralNetworksModel_setOperandValue_27; +extern MNN_ANeuralNetworksModel_setOperandSymmPerChannelQuantParams *ANeuralNetworksModel_setOperandSymmPerChannelQuantParams_29; +extern MNN_ANeuralNetworksModel_addOperation *ANeuralNetworksModel_addOperation_27; +extern MNN_ANeuralNetworksModel_identifyInputsAndOutputs *ANeuralNetworksModel_identifyInputsAndOutputs_27; +extern MNN_ANeuralNetworksCompilation_create *ANeuralNetworksCompilation_create_27; +extern MNN_ANeuralNetworksCompilation_free *ANeuralNetworksCompilation_free_27; +extern MNN_ANeuralNetworksCompilation_setPreference *ANeuralNetworksCompilation_setPreference_27; +extern MNN_ANeuralNetworksCompilation_finish *ANeuralNetworksCompilation_finish_27; +extern MNN_ANeuralNetworksExecution_create *ANeuralNetworksExecution_create_27; +extern MNN_ANeuralNetworksExecution_free *ANeuralNetworksExecution_free_27; +extern MNN_ANeuralNetworksExecution_setInput *ANeuralNetworksExecution_setInput_27; +extern MNN_ANeuralNetworksExecution_setInputFromMemory *ANeuralNetworksExecution_setInputFromMemory_27; +extern MNN_ANeuralNetworksExecution_setOutput *ANeuralNetworksExecution_setOutput_27; +extern MNN_ANeuralNetworksExecution_setOutputFromMemory *ANeuralNetworksExecution_setOutputFromMemory_27; +extern MNN_ANeuralNetworksExecution_startCompute *ANeuralNetworksExecution_startCompute_27; +extern MNN_ANeuralNetworksEvent_wait *ANeuralNetworksEvent_wait_27; +extern MNN_ANeuralNetworksEvent_free *ANeuralNetworksEvent_free_27; +extern MNN_ANeuralNetworksDevice_getVersion *ANeuralNetworksDevice_getVersion_29; +extern MNN_ANeuralNetworksMemory_createFromAHardwareBuffer *ANeuralNetworksMemory_createFromAHardwareBuffer_29; +extern MNN_ANeuralNetworksMemory_createFromFd *ANeuralNetworksMemory_createFromFd_27; +extern MNN_ANeuralNetworksMemory_free *ANeuralNetworksMemory_free_27; +} +#endif /* NNAPISymbols_h */ \ No newline at end of file diff --git a/source/backend/nnapi/execution/NNAPIBinary.cpp b/source/backend/nnapi/execution/NNAPIBinary.cpp new file mode 100644 index 000000000..c558c8745 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIBinary.cpp @@ -0,0 +1,37 @@ +// +// NNAPIBinary.cpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPIBinary.hpp" + +namespace MNN { + + +NNAPIBinary::NNAPIBinary(MNN::Backend *b, const MNN::Op *op, const std::vector &inputs, const std::vector &outputs) : NNAPICommonExecution(b, op) { +} + +ErrorCode NNAPIBinary::onResize(const std::vector &inputs, const std::vector &outputs) { + MNN_ASSERT(inputs.size() == 2 && outputs.size() == 1); + std::map binary_map { + {BinaryOpOperation_ADD, ANEURALNETWORKS_ADD}, + {BinaryOpOperation_SUB, ANEURALNETWORKS_SUB}, + {BinaryOpOperation_MUL, ANEURALNETWORKS_MUL}, + {BinaryOpOperation_DIV, ANEURALNETWORKS_DIV} + }; + auto opType = static_cast(mOp->main_as_BinaryOp()->opType()); + auto iter = binary_map.find(opType); + if (iter == binary_map.end() || iter->second < 0) { + MNN_ERROR("[NNAPI] Binary not support %s\n", MNN::EnumNameBinaryOpOperation(opType)); + return NOT_SUPPORT; + } + auto inputIdxs = getTensorIdxs(inputs); + inputIdxs.push_back(buildScalar(ANEURALNETWORKS_FUSED_NONE)); + return buildOperation(iter->second, inputIdxs, getTensorIdxs(outputs)); +} + +REGISTER_NNAPI_OP_CREATOR(NNAPIBinary, OpType_BinaryOp) +} // namespace MNN diff --git a/source/backend/nnapi/execution/NNAPIBinary.hpp b/source/backend/nnapi/execution/NNAPIBinary.hpp new file mode 100644 index 000000000..850851e3e --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIBinary.hpp @@ -0,0 +1,25 @@ +// +// NNAPIBinary.hpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef MNN_NNAPIBINARY_HPP +#define MNN_NNAPIBINARY_HPP + +#include "NNAPIBackend.hpp" +#include "NNAPICommonExecution.hpp" + +namespace MNN { + +class NNAPIBinary : public NNAPICommonExecution { +public: + NNAPIBinary(Backend *b, const Op *op, const std::vector &inputs, const std::vector &outputs); + ErrorCode onResize(const std::vector &inputs, const std::vector &outputs); + virtual ~NNAPIBinary() = default; +}; +} // namespace MNN + +#endif // MNN_NNAPIBINARY_HPP diff --git a/source/backend/nnapi/execution/NNAPICommonExecution.cpp b/source/backend/nnapi/execution/NNAPICommonExecution.cpp new file mode 100644 index 000000000..147b7ebb6 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPICommonExecution.cpp @@ -0,0 +1,53 @@ +// +// NNAPICommonExecution.cpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPICommonExecution.hpp" +namespace MNN { + +NNAPICommonExecution::NNAPICommonExecution(Backend *backend, const Op *op) : Execution(backend), mOp(op) { + mNNAPIBackend = (NNAPIBackend*)backend; + mNCHW = mNNAPIBackend->NCHW(); +} + +ErrorCode NNAPICommonExecution::onResize(const std::vector &inputs, const std::vector &outputs) { + return NO_ERROR; +} + +ErrorCode NNAPICommonExecution::onExecute(const std::vector &inputs, const std::vector &outputs) { + return NO_ERROR; +} + +std::vector NNAPICommonExecution::getTensorIdxs(const std::vector& tensors) { + std::vector idxs(tensors.size()); + for (int i = 0; i < tensors.size(); i++) { + idxs[i] = mNNAPIBackend->getTensorIdx(tensors[i]); + } + return idxs; +} + +uint32_t NNAPICommonExecution::buildConstant(const void* data, size_t size, OperandCode dtype, std::vector dims) { + return mNNAPIBackend->buildOperand(data, size, dtype, dims); +} + +uint32_t NNAPICommonExecution::buildTensor(OperandCode dtype, std::vector dims) { + std::vector udims(dims.begin(), dims.end()); + if (!mNCHW) { + // NCHW -> NHWC + udims[0] = dims[0]; + udims[1] = dims[2]; + udims[2] = dims[3]; + udims[3] = dims[1]; + } + return mNNAPIBackend->buildOperand(nullptr, 0, dtype, udims); +} + +ErrorCode NNAPICommonExecution::buildOperation(int op, const std::vector &inputs, const std::vector &outputs) { + auto name = mOp->name() ? mOp->name()->c_str() : EnumNameOpType(mOp->type()); + return mNNAPIBackend->buildOperation(op, inputs, outputs, name); +} +}; // namespace MNN diff --git a/source/backend/nnapi/execution/NNAPICommonExecution.hpp b/source/backend/nnapi/execution/NNAPICommonExecution.hpp new file mode 100644 index 000000000..a473e6348 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPICommonExecution.hpp @@ -0,0 +1,36 @@ +// +// NNAPICommonExecution.hpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef MNN_NNAPICOMMONEXECUTION_HPP +#define MNN_NNAPICOMMONEXECUTION_HPP +#include "core/Execution.hpp" +#include "NNAPIBackend.hpp" +#include + +namespace MNN { + +class NNAPICommonExecution : public Execution { +public: + NNAPICommonExecution(Backend *backend, const Op *op); + virtual ~NNAPICommonExecution() = default; + + virtual ErrorCode onResize(const std::vector &inputs, const std::vector &outputs) override; + virtual ErrorCode onExecute(const std::vector &inputs, const std::vector &outputs) override; +protected: + bool mNCHW; + std::vector getTensorIdxs(const std::vector& tensors); + template inline uint32_t buildScalar(T scalar) { return mNNAPIBackend->buildScalar(scalar); } + uint32_t buildConstant(const void* data, size_t size, OperandCode dtype, std::vector dims = {}); + uint32_t buildTensor(OperandCode dtype, std::vector dims); + ErrorCode buildOperation(int op, const std::vector &inputs, const std::vector &outputs); + NNAPIBackend* mNNAPIBackend; + const Op* mOp; +}; + +} // namespace MNN +#endif // MNN_NNAPICOMMONEXECUTION_HPP diff --git a/source/backend/nnapi/execution/NNAPIConvolution.cpp b/source/backend/nnapi/execution/NNAPIConvolution.cpp new file mode 100644 index 000000000..a27ee2ad1 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIConvolution.cpp @@ -0,0 +1,138 @@ +// +// NNAPIConvolution.cpp +// MNN +// +// Created by MNN on 2022/09/06. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPIConvolution.hpp" + +namespace MNN { + + +NNAPIConvolution::NNAPIConvolution(MNN::Backend *b, const MNN::Op *op, const std::vector &inputs, const std::vector &outputs) : NNAPICommonExecution(b, op) { + isDepthwise = mOp->type() == OpType_ConvolutionDepthwise; + isDeconv = mOp->type() == OpType_Deconvolution; +} +template +static void NCHW2NHWC(const T* source, T* dest, int b, int c, int area) { + int sourceBatchsize = c * area; + int destBatchSize = sourceBatchsize; + for (int bi = 0; bi < b; ++bi) { + auto srcBatch = source + bi * sourceBatchsize; + auto dstBatch = dest + bi * destBatchSize; + for (int i = 0; i < area; ++i) { + auto srcArea = srcBatch + i; + auto dstArea = dstBatch + i * c; + for (int ci = 0; ci < c; ++ci) { + dstArea[ci] = srcArea[ci * area]; + } + } + } +} +ErrorCode NNAPIConvolution::onResize(const std::vector &inputs, const std::vector &outputs) { + auto conv2D = mOp->main_as_Convolution2D(); + auto common = conv2D->common(); + int kernelX = common->kernelX(); + int kernelY = common->kernelY(); + int strideX = common->strideX(); + int strideY = common->strideY(); + int dilateX = common->dilateX(); + int dilateY = common->dilateY(); + int group = common->group(); + uint32_t outputCount = common->outputCount(); + auto padMod = common->padMode(); + bool relu = common->relu(); + bool relu6 = common->relu6(); + int top, left, bottom, right; + if (nullptr != common->pads()) { + MNN_ASSERT(common->pads()->size() >= 4); + top = common->pads()->Get(0); + left = common->pads()->Get(1); + bottom = common->pads()->Get(2); + right = common->pads()->Get(3); + } else { + top = common->padY(); + left = common->padX(); + bottom = common->padY(); + right = common->padX(); + } + // NNAPI inputs: + // conv2d: [input, weight, bias, pad_left, pad_right, pad_top, pad_bottom, stride_w, stride_h, fusecode, NCHW/NHWC, dilate_w, dilate_h] + // depthwise_conv2d: [input, weight, bias, pad_left, pad_right, pad_top, pad_bottom, stride_w, stride_h, multiplier, fusecode, NCHW/NHWC, dilate_w, dilate_h] + auto inputIdxs = getTensorIdxs(inputs); + // inputs not contain weight and bias, read from param + if (inputs.size() < 3) { + const void *weightPtr, *biasPtr; + int weightSize, biasSize; + if (nullptr != conv2D->quanParameter()) { + quanCommon = ConvolutionCommon::load(conv2D->quanParameter(), true); + if (nullptr == quanCommon) { + MNN_ERROR("Memory not Enough, can't extract IDST Convolution: %s \n", mOp->name()->c_str()); + } + if (quanCommon->weightFloat.get() == nullptr) { + MNN_PRINT("quanCommon->weightFloat.get() == nullptr \n"); + } + // Back to float + weightPtr = quanCommon->weightFloat.get(); + weightSize = quanCommon->weightFloat.size(); + } else { + weightPtr = conv2D->weight()->data(); + weightSize = conv2D->weight()->size(); + } + biasSize = conv2D->bias()->size(); + biasPtr = conv2D->bias()->data(); + uint32_t inputCount = weightSize / (kernelX * kernelY * outputCount); + uint32_t n = outputCount; + uint32_t c = inputCount; + uint32_t h = kernelY; + uint32_t w = kernelX; + if (isDepthwise) { + n = 1; + c = outputCount; + } + nhwcWeight.reset(new float[weightSize]); + std::vector weightDims {n, h, w, c}; + // [outputCount, inputChannel, h, w] -> [outputCount, h, w, inputChannel] + NCHW2NHWC(reinterpret_cast(weightPtr), nhwcWeight.get(), n, c, h * w); + std::vector biasDims {outputCount}; + inputIdxs.push_back(buildConstant(nhwcWeight.get(), weightSize * sizeof(float), ANEURALNETWORKS_TENSOR_FLOAT32, weightDims)); + inputIdxs.push_back(buildConstant(biasPtr, biasSize * sizeof(float), ANEURALNETWORKS_TENSOR_FLOAT32, biasDims)); + } + // pad + inputIdxs.push_back(buildScalar(left)); + inputIdxs.push_back(buildScalar(right)); + inputIdxs.push_back(buildScalar(top)); + inputIdxs.push_back(buildScalar(bottom)); + // stride + inputIdxs.push_back(buildScalar(strideX)); + inputIdxs.push_back(buildScalar(strideY)); + if (isDepthwise) { + int multiplier = outputCount / group; + inputIdxs.push_back(buildScalar(multiplier)); + } + // fusecode + FuseCode code = ANEURALNETWORKS_FUSED_NONE; + if (relu) code = ANEURALNETWORKS_FUSED_RELU; + if (relu6) code = ANEURALNETWORKS_FUSED_RELU6; + inputIdxs.push_back(buildScalar(code)); + // NCHW/NHWC + inputIdxs.push_back(buildScalar(mNCHW)); + // dilate + if (dilateX > 1 || dilateY > 1) { + inputIdxs.push_back(buildScalar(dilateX)); + inputIdxs.push_back(buildScalar(dilateY)); + } + auto op = ANEURALNETWORKS_CONV_2D; + if (mOp->type() == OpType_ConvolutionDepthwise) { + op = ANEURALNETWORKS_DEPTHWISE_CONV_2D; + } else { + // TODO: deconv + } + return buildOperation(op, inputIdxs, getTensorIdxs(outputs)); +} + +REGISTER_NNAPI_OP_CREATOR(NNAPIConvolution, OpType_Convolution) +REGISTER_NNAPI_OP_CREATOR(NNAPIConvolution, OpType_ConvolutionDepthwise) +} // namespace MNN diff --git a/source/backend/nnapi/execution/NNAPIConvolution.hpp b/source/backend/nnapi/execution/NNAPIConvolution.hpp new file mode 100644 index 000000000..86a7e3f40 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIConvolution.hpp @@ -0,0 +1,30 @@ +// +// NNAPIConvolution.hpp +// MNN +// +// Created by MNN on 2022/09/06. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef MNN_NNAPICONVOLUTION_HPP +#define MNN_NNAPICONVOLUTION_HPP + +#include "NNAPIBackend.hpp" +#include "NNAPICommonExecution.hpp" +#include "core/ConvolutionCommon.hpp" + +namespace MNN { + +class NNAPIConvolution : public NNAPICommonExecution { +public: + NNAPIConvolution(Backend *b, const Op *op, const std::vector &inputs, const std::vector &outputs); + ErrorCode onResize(const std::vector &inputs, const std::vector &outputs); + virtual ~NNAPIConvolution() = default; +private: + std::shared_ptr quanCommon; + std::unique_ptr nhwcWeight; + bool isDepthwise = false, isDeconv = false; +}; +} // namespace MNN + +#endif // MNN_NNAPICONVOLUTION_HPP diff --git a/source/backend/nnapi/execution/NNAPIPool.cpp b/source/backend/nnapi/execution/NNAPIPool.cpp new file mode 100644 index 000000000..148187813 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIPool.cpp @@ -0,0 +1,67 @@ +// +// NNAPIPool.cpp +// MNN +// +// Created by MNN on 2022/09/06. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPIPool.hpp" + +namespace MNN { + + +NNAPIPool::NNAPIPool(MNN::Backend *b, const MNN::Op *op, const std::vector &inputs, const std::vector &outputs) : NNAPICommonExecution(b, op) { +} + +ErrorCode NNAPIPool::onResize(const std::vector &inputs, const std::vector &outputs) { + auto pool = mOp->main_as_Pool(); + auto strideX = pool->strideX(); + auto strideY = pool->strideY(); + auto kernelX = pool->kernelX(); + auto kernelY = pool->kernelY(); + auto padMod = pool->padType(); + auto global = pool->isGlobal(); + int top, left, bottom, right; + if (nullptr != pool->pads()) { + MNN_ASSERT(pool->pads()->size() >= 4); + top = pool->pads()->Get(0); + left = pool->pads()->Get(1); + bottom = pool->pads()->Get(2); + right = pool->pads()->Get(3); + } else { + top = pool->padY(); + left = pool->padX(); + bottom = pool->padY(); + right = pool->padX(); + } + if (global) { + kernelX = inputs[0]->width(); + kernelY = inputs[0]->height(); + } + // NNAPI Pool inputs: [input, pad_left, pad_right, pad_top, pad_bottom, stride_w, stride_h, kernel_w, kernel_h, fusecode, NCHW/NHWC] + auto inputIdxs = getTensorIdxs(inputs); + // pad + inputIdxs.push_back(buildScalar(left)); + inputIdxs.push_back(buildScalar(right)); + inputIdxs.push_back(buildScalar(top)); + inputIdxs.push_back(buildScalar(bottom)); + // stride + inputIdxs.push_back(buildScalar(strideX)); + inputIdxs.push_back(buildScalar(strideY)); + // kernel + inputIdxs.push_back(buildScalar(kernelX)); + inputIdxs.push_back(buildScalar(kernelY)); + // fusecode + inputIdxs.push_back(buildScalar(ANEURALNETWORKS_FUSED_NONE)); + // NCHW/NHWC + inputIdxs.push_back(buildScalar(mNCHW)); + auto op = ANEURALNETWORKS_MAX_POOL_2D; + if (pool->type() == PoolType_AVEPOOL) { + op = ANEURALNETWORKS_AVERAGE_POOL_2D; + } + return buildOperation(op, inputIdxs, getTensorIdxs(outputs)); +} + +REGISTER_NNAPI_OP_CREATOR(NNAPIPool, OpType_Pooling) +} // namespace MNN diff --git a/source/backend/nnapi/execution/NNAPIPool.hpp b/source/backend/nnapi/execution/NNAPIPool.hpp new file mode 100644 index 000000000..7ef7b4577 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIPool.hpp @@ -0,0 +1,26 @@ +// +// NNAPIPool.hpp +// MNN +// +// Created by MNN on 2022/09/06. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef MNN_NNAPIPOOL_HPP +#define MNN_NNAPIPOOL_HPP + +#include "NNAPIBackend.hpp" +#include "NNAPICommonExecution.hpp" +#include "core/ConvolutionCommon.hpp" + +namespace MNN { + +class NNAPIPool : public NNAPICommonExecution { +public: + NNAPIPool(Backend *b, const Op *op, const std::vector &inputs, const std::vector &outputs); + ErrorCode onResize(const std::vector &inputs, const std::vector &outputs); + virtual ~NNAPIPool() = default; +}; +} // namespace MNN + +#endif // MNN_NNAPIPOOL_HPP diff --git a/source/backend/nnapi/execution/NNAPISoftmax.cpp b/source/backend/nnapi/execution/NNAPISoftmax.cpp new file mode 100644 index 000000000..9ada20f18 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPISoftmax.cpp @@ -0,0 +1,38 @@ +// +// NNAPISoftmax.cpp +// MNN +// +// Created by MNN on 2022/09/06. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPISoftmax.hpp" + +namespace MNN { + + +NNAPISoftmax::NNAPISoftmax(MNN::Backend *b, const MNN::Op *op, const std::vector &inputs, const std::vector &outputs) : NNAPICommonExecution(b, op) { +} + +ErrorCode NNAPISoftmax::onResize(const std::vector &inputs, const std::vector &outputs) { + int axis = mOp->main_as_Axis()->axis(); + auto inputIdxs = getTensorIdxs(inputs); + // NNAPI Softmax inputs: [input, beta, axis] + float beta = 1.0; + inputIdxs.push_back(buildScalar(beta)); + bool needAxis = false; + auto dims = inputs[0]->shape(); + for (int i = 0; i < dims.size(); i++) { + if (i != axis && dims[i] > 1) { + needAxis = true; + break; + } + } + if (needAxis) { + inputIdxs.push_back(buildScalar(axis)); + } + return buildOperation(ANEURALNETWORKS_SOFTMAX, inputIdxs, getTensorIdxs(outputs)); +} + +REGISTER_NNAPI_OP_CREATOR(NNAPISoftmax, OpType_Softmax) +} // namespace MNN diff --git a/source/backend/nnapi/execution/NNAPISoftmax.hpp b/source/backend/nnapi/execution/NNAPISoftmax.hpp new file mode 100644 index 000000000..83052a7a0 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPISoftmax.hpp @@ -0,0 +1,26 @@ +// +// NNAPISoftmax.hpp +// MNN +// +// Created by MNN on 2022/09/06. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef MNN_NNAPISOFTMAX_HPP +#define MNN_NNAPISOFTMAX_HPP + +#include "NNAPIBackend.hpp" +#include "NNAPICommonExecution.hpp" +#include "core/ConvolutionCommon.hpp" + +namespace MNN { + +class NNAPISoftmax : public NNAPICommonExecution { +public: + NNAPISoftmax(Backend *b, const Op *op, const std::vector &inputs, const std::vector &outputs); + ErrorCode onResize(const std::vector &inputs, const std::vector &outputs); + virtual ~NNAPISoftmax() = default; +}; +} // namespace MNN + +#endif // MNN_NNAPISOFTMAX_HPP diff --git a/source/backend/nnapi/execution/NNAPIUnary.cpp b/source/backend/nnapi/execution/NNAPIUnary.cpp new file mode 100644 index 000000000..1c8b1b060 --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIUnary.cpp @@ -0,0 +1,65 @@ +// +// NNAPIUnary.cpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "NNAPIUnary.hpp" + +namespace MNN { + + +NNAPIUnary::NNAPIUnary(MNN::Backend *b, const MNN::Op *op, const std::vector &inputs, const std::vector &outputs) : NNAPICommonExecution(b, op) { +} + +ErrorCode NNAPIUnary::onResize(const std::vector &inputs, const std::vector &outputs) { + MNN_ASSERT(inputs.size() == 1 && outputs.size() == 1); + std::map unary_map { + {UnaryOpOperation_ABS, ANEURALNETWORKS_ABS}, + {UnaryOpOperation_EXP, ANEURALNETWORKS_EXP}, + {UnaryOpOperation_SQRT, ANEURALNETWORKS_SQRT}, + {UnaryOpOperation_RSQRT, ANEURALNETWORKS_RSQRT}, + {UnaryOpOperation_LOG, ANEURALNETWORKS_LOG}, + {UnaryOpOperation_RECIPROCAL, -1}, + {UnaryOpOperation_SIN, ANEURALNETWORKS_SIN}, + {UnaryOpOperation_ASIN, -1}, + {UnaryOpOperation_SINH, -1}, + {UnaryOpOperation_ASINH, -1}, + {UnaryOpOperation_COS, -1}, + {UnaryOpOperation_ACOS, -1}, + {UnaryOpOperation_COSH, -1}, + {UnaryOpOperation_ACOSH, -1}, + {UnaryOpOperation_TAN, -1}, + {UnaryOpOperation_ATAN, -1}, + {UnaryOpOperation_TANH, ANEURALNETWORKS_TANH}, + {UnaryOpOperation_ATANH, -1}, + {UnaryOpOperation_ERF, -1}, + {UnaryOpOperation_CEIL, -1}, + {UnaryOpOperation_FLOOR, ANEURALNETWORKS_FLOOR}, + {UnaryOpOperation_ROUND, -1}, + {UnaryOpOperation_SIGN, -1}, + {UnaryOpOperation_SIGMOID, -1}, + {UnaryOpOperation_LOG1P, -1}, + {UnaryOpOperation_SQUARE, -1}, + {UnaryOpOperation_NEG, ANEURALNETWORKS_NEG}, + {UnaryOpOperation_HARDSWISH, -1}, + {UnaryOpOperation_GELU, -1}, + {UnaryOpOperation_GELU_STANDARD, -1}, + {UnaryOpOperation_EXPM1, -1}, + {UnaryOpOperation_ERFC, -1}, + {UnaryOpOperation_BNLL, -1}, + {UnaryOpOperation_ERFINV, -1} + }; + auto opType = mOp->main_as_UnaryOp()->opType(); + auto iter = unary_map.find(opType); + if (iter == unary_map.end() || iter->second < 0) { + MNN_ERROR("NNAPI Unary not support %s\n", MNN::EnumNameUnaryOpOperation(opType)); + return NOT_SUPPORT; + } + return buildOperation(iter->second, getTensorIdxs(inputs), getTensorIdxs(outputs)); +} + +REGISTER_NNAPI_OP_CREATOR(NNAPIUnary, OpType_UnaryOp) +} // namespace MNN diff --git a/source/backend/nnapi/execution/NNAPIUnary.hpp b/source/backend/nnapi/execution/NNAPIUnary.hpp new file mode 100644 index 000000000..b175aa3bb --- /dev/null +++ b/source/backend/nnapi/execution/NNAPIUnary.hpp @@ -0,0 +1,25 @@ +// +// NNAPIUnary.hpp +// MNN +// +// Created by MNN on 2022/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#ifndef MNN_NNAPIUNARY_HPP +#define MNN_NNAPIUNARY_HPP + +#include "NNAPIBackend.hpp" +#include "NNAPICommonExecution.hpp" + +namespace MNN { + +class NNAPIUnary : public NNAPICommonExecution { +public: + NNAPIUnary(Backend *b, const Op *op, const std::vector &inputs, const std::vector &outputs); + ErrorCode onResize(const std::vector &inputs, const std::vector &outputs); + virtual ~NNAPIUnary() = default; +}; +} // namespace MNN + +#endif // MNN_NNAPIUNARY_HPP diff --git a/source/backend/opencl/execution/buffer/BinaryBufExecution.cpp b/source/backend/opencl/execution/buffer/BinaryBufExecution.cpp index 02685c843..47a99818a 100644 --- a/source/backend/opencl/execution/buffer/BinaryBufExecution.cpp +++ b/source/backend/opencl/execution/buffer/BinaryBufExecution.cpp @@ -43,6 +43,10 @@ ErrorCode BinaryBufExecution::onResize(const std::vector &inputs, cons int shape[4] = {outputShape[0], outputShape[1], outputShape[2], UP_DIV(outputShape[3], 4)}; int fullCount[2] = {1, 1}; + int activationType = 0; + if(mOp->type() == OpType_BinaryOp) { + activationType = mOp->main_as_BinaryOp()->activationType(); + } auto &unit = mUnits[0]; unit.kernel = runTime->buildKernel("binary_buf", "binary_buf", mBuildOptions); mMaxWorkGroupSize = static_cast(runTime->getMaxWorkGroupSize(unit.kernel)); @@ -60,6 +64,7 @@ ErrorCode BinaryBufExecution::onResize(const std::vector &inputs, cons unit.kernel.setArg(index++, openCLBuffer(output)); unit.kernel.setArg(index++, shape); unit.kernel.setArg(index++, fullCount); + unit.kernel.setArg(index++, activationType); std::string name = "binary_buf"; mLocalWorkSize = localWS2DDefault(mGlobalWorkSize, mMaxWorkGroupSize, openCLBackend->getOpenCLRuntime(), name, unit.kernel).first; @@ -80,6 +85,7 @@ ErrorCode BinaryBufExecution::onResize(const std::vector &inputs, cons unit.kernel.setArg(index++, openCLBuffer(output)); unit.kernel.setArg(index++, shape); unit.kernel.setArg(index++, fullCount); + unit.kernel.setArg(index++, activationType); unit.globalWorkSize = {mGlobalWorkSize[0], mGlobalWorkSize[1]}; unit.localWorkSize = {mLocalWorkSize[0], mLocalWorkSize[1]}; diff --git a/source/backend/opencl/execution/cl/binary.cl b/source/backend/opencl/execution/cl/binary.cl index de267fbc1..2a62b4ca4 100644 --- a/source/backend/opencl/execution/cl/binary.cl +++ b/source/backend/opencl/execution/cl/binary.cl @@ -7,7 +7,8 @@ __kernel void binary(__private int global_dim0, __private int global_dim1, __read_only image2d_t input0, __read_only image2d_t input1, __write_only image2d_t output, __private const int4 shape,//[N,H,W,C4] - __private const int2 isFull) { + __private const int2 isFull, + __private const int activationType) { int2 pos = (int2)(get_global_id(0), get_global_id(1));//WC4, NH FLOAT4 in0, in1; @@ -27,6 +28,9 @@ __kernel void binary(__private int global_dim0, __private int global_dim1, } FLOAT4 out = CONVERT_FLOAT4(OPERATOR); + if(activationType == 1) { + out = fmax(out, (FLOAT4)0); + } WI_F(output, pos, out); } } diff --git a/source/backend/opencl/execution/cl/binary_buf.cl b/source/backend/opencl/execution/cl/binary_buf.cl index 1bfec6c9c..f3fcb2cc2 100644 --- a/source/backend/opencl/execution/cl/binary_buf.cl +++ b/source/backend/opencl/execution/cl/binary_buf.cl @@ -5,7 +5,8 @@ __kernel void binary_buf(__private int global_dim0, __private int global_dim1, __global FLOAT* input0, __global FLOAT* input1, __global FLOAT* output, __private const int4 shape,//[N,H,W,C4] - __private const int2 isFull) { + __private const int2 isFull, + __private const int activationType) { int2 pos = (int2)(get_global_id(0), get_global_id(1));//NC4, HW if (pos.x < global_dim0 && pos.y < global_dim1) { @@ -19,6 +20,9 @@ __kernel void binary_buf(__private int global_dim0, __private int global_dim1, in1 = (FLOAT4)(in1.x, in1.x, in1.x, in1.x); } FLOAT4 out = CONVERT_FLOAT4(OPERATOR); + if(activationType == 1) { + out = fmax(out, (FLOAT4)0); + } vstore4(out, offset, output); } } diff --git a/source/backend/opencl/execution/cl/opencl_program.cc b/source/backend/opencl/execution/cl/opencl_program.cc index 4e62c5efb..987fd71a2 100644 --- a/source/backend/opencl/execution/cl/opencl_program.cc +++ b/source/backend/opencl/execution/cl/opencl_program.cc @@ -5,136 +5,76 @@ namespace MNN { extern const std::map> OpenCLProgramMap = { { - "binary_buf", - { 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} }, { "buffer_to_image", @@ -145,32 +85,32 @@ extern const std::map> OpenCLProgramMap { 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} }, }; } diff --git a/source/backend/opencl/execution/image/EltwiseExecution.cpp b/source/backend/opencl/execution/image/EltwiseExecution.cpp index 50df95073..a266036e1 100644 --- a/source/backend/opencl/execution/image/EltwiseExecution.cpp +++ b/source/backend/opencl/execution/image/EltwiseExecution.cpp @@ -27,9 +27,8 @@ static string swapComputeIn0In1(const string& computeOrigin) { return compute; } -EltwiseExecution::EltwiseExecution(const std::vector &inputs, const std::string &compute, const MNN::Op *op, Backend *backend, - float operatorData, bool broadCast) - : CommonExecution(backend), mCompute(compute), mBroadCast(broadCast), mOperatorData(operatorData) { +EltwiseExecution::EltwiseExecution(const std::vector &inputs, const std::string &compute, const MNN::Op *op, Backend *backend) + : CommonExecution(backend), mCompute(compute) { mBuildOptions.emplace("-DOPERATOR=" + compute); mOp = op; @@ -56,6 +55,10 @@ ErrorCode EltwiseExecution::onResize(const std::vector &inputs, const auto runTime = ((OpenCLBackend *)backend())->getOpenCLRuntime(); int shape[4] = {outputShape[0], outputShape[1], outputShape[2], UP_DIV(outputShape[3], 4)}; int fullCount[2] = {1, 1}; + int activationType = 0; + if(mOp->type() == OpType_BinaryOp) { + activationType = mOp->main_as_BinaryOp()->activationType(); + } auto &unit = mUnits[0]; unit.kernel = runTime->buildKernel("binary", "binary", mBuildOptions); @@ -76,6 +79,7 @@ ErrorCode EltwiseExecution::onResize(const std::vector &inputs, const unit.kernel.setArg(index++, openCLImage(output)); unit.kernel.setArg(index++, shape); unit.kernel.setArg(index++, fullCount); + unit.kernel.setArg(index++, activationType); std::string name = "binary"; mLocalWorkSize = localWS2DDefault(mGlobalWorkSize, mMaxWorkGroupSize, openCLBackend->getOpenCLRuntime(), name, unit.kernel).first; @@ -127,6 +131,7 @@ ErrorCode EltwiseExecution::onResize(const std::vector &inputs, const unit.kernel.setArg(index++, openCLImage(output)); unit.kernel.setArg(index++, shape); unit.kernel.setArg(index++, fullCount); + unit.kernel.setArg(index++, activationType); if(i == 0) { std::string name = "binary"; diff --git a/source/backend/opencl/execution/image/EltwiseExecution.hpp b/source/backend/opencl/execution/image/EltwiseExecution.hpp index 0dd059d0a..f0125c514 100644 --- a/source/backend/opencl/execution/image/EltwiseExecution.hpp +++ b/source/backend/opencl/execution/image/EltwiseExecution.hpp @@ -16,7 +16,7 @@ namespace OpenCL { class EltwiseExecution : public CommonExecution { public: - EltwiseExecution(const std::vector &inputs, const std::string &compute, const MNN::Op *op, Backend *backend, float operatorData = 0.0001f, bool broadCast = false); + EltwiseExecution(const std::vector &inputs, const std::string &compute, const MNN::Op *op, Backend *backend); virtual ~EltwiseExecution() = default; uint32_t realSize(const Tensor* tensor); diff --git a/source/backend/opengl/AllShader.cpp b/source/backend/opengl/AllShader.cpp index 2fa253ec8..e3a43ee32 100644 --- a/source/backend/opengl/AllShader.cpp +++ b/source/backend/opengl/AllShader.cpp @@ -884,6 +884,7 @@ const char* glsl_binary_glsl = "layout(location=1) uniform mediump sampler3D uInput0;\n" "layout(location=2) uniform mediump sampler3D uInput1;\n" "layout(location=3) uniform ivec4 imgSize;\n" +"layout(location=4) uniform int activationType;\n" "layout (local_size_x = XLOCAL, local_size_y = YLOCAL, local_size_z = ZLOCAL) in;\n" "void main()\n" "{\n" @@ -903,6 +904,9 @@ const char* glsl_binary_glsl = "#ifdef REALDIV\n" " vec4 sum = texelFetch(uInput0, pos, 0) / texelFetch(uInput1, pos, 0);\n" "#endif\n" +" if(activationType == 1) {\n" +" sum = max(sum, vec4(0));\n" +" }\n" " imageStore(uOutput, pos, sum);\n" " }\n" "}\n" diff --git a/source/backend/opengl/GLBinary.cpp b/source/backend/opengl/GLBinary.cpp index 048ca7aef..99bcad200 100644 --- a/source/backend/opengl/GLBinary.cpp +++ b/source/backend/opengl/GLBinary.cpp @@ -17,6 +17,7 @@ namespace MNN { namespace OpenGL { GLBinary::GLBinary(const std::vector &inputs, const Op *op, Backend *bn) : Execution(bn) { mType = op->main_as_BinaryOp()->opType(); + mActivationType = op->main_as_BinaryOp()->activationType(); } GLBinary::~GLBinary() { @@ -89,6 +90,7 @@ ErrorCode GLBinary::onExecute(const std::vector &inputs, const std::ve OPENGL_CHECK_ERROR; } glUniform4i(3, iw, ih, ic_4, 1); + glUniform1i(4, mActivationType); OPENGL_CHECK_ERROR; ((GLBackend *)backend())->compute(UP_DIV(iw, mLocalSize[0]), UP_DIV(ih, mLocalSize[1]), UP_DIV(ic_4, mLocalSize[2])); diff --git a/source/backend/opengl/GLBinary.hpp b/source/backend/opengl/GLBinary.hpp index 5a96e1a4d..f9d7afc83 100644 --- a/source/backend/opengl/GLBinary.hpp +++ b/source/backend/opengl/GLBinary.hpp @@ -25,6 +25,7 @@ private: std::shared_ptr mProgram; int32_t mType; int mLocalSize[3]; + int mActivationType = 0; }; } // namespace OpenGL } // namespace MNN diff --git a/source/backend/opengl/glsl/binary.glsl b/source/backend/opengl/glsl/binary.glsl index d5b211368..0f84cfa5c 100644 --- a/source/backend/opengl/glsl/binary.glsl +++ b/source/backend/opengl/glsl/binary.glsl @@ -3,6 +3,7 @@ layout(FORMAT, binding=0) writeonly uniform PRECISION image3D uOutput; layout(location=1) uniform mediump sampler3D uInput0; layout(location=2) uniform mediump sampler3D uInput1; layout(location=3) uniform ivec4 imgSize; +layout(location=4) uniform int activationType; layout (local_size_x = XLOCAL, local_size_y = YLOCAL, local_size_z = ZLOCAL) in; @@ -25,6 +26,9 @@ void main() #ifdef REALDIV vec4 sum = texelFetch(uInput0, pos, 0) / texelFetch(uInput1, pos, 0); #endif + if(activationType == 1) { + sum = max(sum, vec4(0)); + } imageStore(uOutput, pos, sum); } } diff --git a/source/backend/tensorrt/execution/TRTBinary.cpp b/source/backend/tensorrt/execution/TRTBinary.cpp index 041d254c7..f77ad671e 100644 --- a/source/backend/tensorrt/execution/TRTBinary.cpp +++ b/source/backend/tensorrt/execution/TRTBinary.cpp @@ -15,7 +15,7 @@ namespace MNN { TRTBinary::TRTBinary(Backend *b, const Op *op, const std::vector &inputs, const std::vector &outputs) : MNN::TRTCommonExecution(b, op) { - // Do nothing + mActivationType = op->main_as_BinaryOp()->activationType(); } std::vector TRTBinary::onEncode(const std::vector &xOp) { @@ -34,7 +34,13 @@ std::vector TRTBinary::onEncode(const std::vector &xOp) { MNN_PRINT("binary plugin == nullptr !!!\n"); } mTrtBackend->pushReleaseLayer(binaryPlugin); - return {plugin->getOutput(0)}; + + auto output = plugin->getOutput(0); + if (mActivationType == 1) { + mActivationLayer = mTrtBackend->getNetwork()->addActivation(*output, ActivationType::kRELU); + return {mActivationLayer->getOutput(0)}; + } + return {output}; } TRTCreatorRegister> __binary_op(OpType_BinaryOp); diff --git a/source/backend/tensorrt/execution/TRTBinary.hpp b/source/backend/tensorrt/execution/TRTBinary.hpp index 58d222a5e..d12d222eb 100644 --- a/source/backend/tensorrt/execution/TRTBinary.hpp +++ b/source/backend/tensorrt/execution/TRTBinary.hpp @@ -22,6 +22,8 @@ public: private: IConstantLayer *const_layer; + int mActivationType = 0; + IActivationLayer *mActivationLayer{nullptr}; }; } // namespace MNN diff --git a/source/backend/vulkan/compiler/AllShader.cpp b/source/backend/vulkan/compiler/AllShader.cpp index a137d4a99..10d6802a6 100644 --- a/source/backend/vulkan/compiler/AllShader.cpp +++ b/source/backend/vulkan/compiler/AllShader.cpp @@ -1,6 +1,6 @@ #include "../shaders/AllShader.h" const unsigned char glsl_dwweightcopy_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x9e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -179,7 +179,7 @@ const unsigned char glsl_dwweightcopy_comp[] = { unsigned int glsl_dwweightcopy_comp_len = 2092; const unsigned char glsl_deconvCol2Im_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x9b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -380,7 +380,7 @@ const unsigned char glsl_deconvCol2Im_comp[] = { unsigned int glsl_deconvCol2Im_comp_len = 2364; const unsigned char glsl_convolutionDepthwiseMali_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -710,7 +710,7 @@ const unsigned char glsl_convolutionDepthwiseMali_comp[] = { unsigned int glsl_convolutionDepthwiseMali_comp_len = 3912; const unsigned char glsl_convolutionDepthwiseMali_RELU_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -1046,7 +1046,7 @@ const unsigned char glsl_convolutionDepthwiseMali_RELU_comp[] = { unsigned int glsl_convolutionDepthwiseMali_RELU_comp_len = 3984; const unsigned char glsl_convolutionDepthwiseMali_RELU6_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xf2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -1386,7 +1386,7 @@ const unsigned char glsl_convolutionDepthwiseMali_RELU6_comp[] = { unsigned int glsl_convolutionDepthwiseMali_RELU6_comp_len = 4032; const unsigned char glsl_relu_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x5a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -1423,7 +1423,6 @@ const unsigned char glsl_relu_comp[] = { 0x34, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x34, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x35, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x50, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, @@ -1528,10 +1527,10 @@ const unsigned char glsl_relu_comp[] = { 0xf9, 0x00, 0x02, 0x00, 0x2e, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x2e, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_relu_comp_len = 1692; +unsigned int glsl_relu_comp_len = 1680; const unsigned char glsl_unaryImage_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -1651,7 +1650,7 @@ const unsigned char glsl_unaryImage_comp[] = { unsigned int glsl_unaryImage_comp_len = 1384; const unsigned char glsl_unaryImage_SIGMOID_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x56, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -1781,7 +1780,7 @@ const unsigned char glsl_unaryImage_SIGMOID_comp[] = { unsigned int glsl_unaryImage_SIGMOID_comp_len = 1508; const unsigned char glsl_unaryImage_TANH_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -1903,7 +1902,7 @@ const unsigned char glsl_unaryImage_TANH_comp[] = { unsigned int glsl_unaryImage_TANH_comp_len = 1408; const unsigned char glsl_unaryImage_ABS_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2025,7 +2024,7 @@ const unsigned char glsl_unaryImage_ABS_comp[] = { unsigned int glsl_unaryImage_ABS_comp_len = 1408; const unsigned char glsl_unaryImage_SQRT_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2147,7 +2146,7 @@ const unsigned char glsl_unaryImage_SQRT_comp[] = { unsigned int glsl_unaryImage_SQRT_comp_len = 1408; const unsigned char glsl_unaryImage_RSQRT_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2269,7 +2268,7 @@ const unsigned char glsl_unaryImage_RSQRT_comp[] = { unsigned int glsl_unaryImage_RSQRT_comp_len = 1408; const unsigned char glsl_unaryImage_NEG_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2390,7 +2389,7 @@ const unsigned char glsl_unaryImage_NEG_comp[] = { unsigned int glsl_unaryImage_NEG_comp_len = 1400; const unsigned char glsl_unaryImage_SQUARE_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x50, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2511,7 +2510,7 @@ const unsigned char glsl_unaryImage_SQUARE_comp[] = { unsigned int glsl_unaryImage_SQUARE_comp_len = 1404; const unsigned char glsl_unaryImage_EXP_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2633,7 +2632,7 @@ const unsigned char glsl_unaryImage_EXP_comp[] = { unsigned int glsl_unaryImage_EXP_comp_len = 1408; const unsigned char glsl_unaryImage_SIGN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2755,7 +2754,7 @@ const unsigned char glsl_unaryImage_SIGN_comp[] = { unsigned int glsl_unaryImage_SIGN_comp_len = 1408; const unsigned char glsl_unaryImage_LOG_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -2883,7 +2882,7 @@ const unsigned char glsl_unaryImage_LOG_comp[] = { unsigned int glsl_unaryImage_LOG_comp_len = 1480; const unsigned char glsl_unaryImage_TAN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3005,7 +3004,7 @@ const unsigned char glsl_unaryImage_TAN_comp[] = { unsigned int glsl_unaryImage_TAN_comp_len = 1408; const unsigned char glsl_unaryImage_COS_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3127,7 +3126,7 @@ const unsigned char glsl_unaryImage_COS_comp[] = { unsigned int glsl_unaryImage_COS_comp_len = 1408; const unsigned char glsl_unaryImage_SIN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3249,7 +3248,7 @@ const unsigned char glsl_unaryImage_SIN_comp[] = { unsigned int glsl_unaryImage_SIN_comp_len = 1408; const unsigned char glsl_unaryImage_CEIL_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3371,7 +3370,7 @@ const unsigned char glsl_unaryImage_CEIL_comp[] = { unsigned int glsl_unaryImage_CEIL_comp_len = 1408; const unsigned char glsl_unaryImage_FLOOR_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3493,7 +3492,7 @@ const unsigned char glsl_unaryImage_FLOOR_comp[] = { unsigned int glsl_unaryImage_FLOOR_comp_len = 1408; const unsigned char glsl_unaryImage_EXPM1_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3620,7 +3619,7 @@ const unsigned char glsl_unaryImage_EXPM1_comp[] = { unsigned int glsl_unaryImage_EXPM1_comp_len = 1472; const unsigned char glsl_unaryImage_RECIPROCAL_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x51, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3745,7 +3744,7 @@ const unsigned char glsl_unaryImage_RECIPROCAL_comp[] = { unsigned int glsl_unaryImage_RECIPROCAL_comp_len = 1448; const unsigned char glsl_unaryImage_SINH_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3867,7 +3866,7 @@ const unsigned char glsl_unaryImage_SINH_comp[] = { unsigned int glsl_unaryImage_SINH_comp_len = 1408; const unsigned char glsl_unaryImage_ASINH_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -3989,7 +3988,7 @@ const unsigned char glsl_unaryImage_ASINH_comp[] = { unsigned int glsl_unaryImage_ASINH_comp_len = 1408; const unsigned char glsl_unaryImage_ASIN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4111,7 +4110,7 @@ const unsigned char glsl_unaryImage_ASIN_comp[] = { unsigned int glsl_unaryImage_ASIN_comp_len = 1408; const unsigned char glsl_unaryImage_COSH_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4233,7 +4232,7 @@ const unsigned char glsl_unaryImage_COSH_comp[] = { unsigned int glsl_unaryImage_COSH_comp_len = 1408; const unsigned char glsl_unaryImage_ACOS_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4355,7 +4354,7 @@ const unsigned char glsl_unaryImage_ACOS_comp[] = { unsigned int glsl_unaryImage_ACOS_comp_len = 1408; const unsigned char glsl_unaryImage_ACOSH_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4477,7 +4476,7 @@ const unsigned char glsl_unaryImage_ACOSH_comp[] = { unsigned int glsl_unaryImage_ACOSH_comp_len = 1408; const unsigned char glsl_unaryImage_ATAN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4599,7 +4598,7 @@ const unsigned char glsl_unaryImage_ATAN_comp[] = { unsigned int glsl_unaryImage_ATAN_comp_len = 1408; const unsigned char glsl_unaryImage_ATANH_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4721,7 +4720,7 @@ const unsigned char glsl_unaryImage_ATANH_comp[] = { unsigned int glsl_unaryImage_ATANH_comp_len = 1408; const unsigned char glsl_unaryImage_LOG1P_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x52, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4848,7 +4847,7 @@ const unsigned char glsl_unaryImage_LOG1P_comp[] = { unsigned int glsl_unaryImage_LOG1P_comp_len = 1472; const unsigned char glsl_unaryImage_ROUND_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -4970,7 +4969,7 @@ const unsigned char glsl_unaryImage_ROUND_comp[] = { unsigned int glsl_unaryImage_ROUND_comp_len = 1408; const unsigned char glsl_unaryImage_HARDSWISH_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x71, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -5128,7 +5127,7 @@ const unsigned char glsl_unaryImage_HARDSWISH_comp[] = { unsigned int glsl_unaryImage_HARDSWISH_comp_len = 1848; const unsigned char glsl_im2col_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x54, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -5508,7 +5507,7 @@ const unsigned char glsl_im2col_comp[] = { unsigned int glsl_im2col_comp_len = 4512; const unsigned char glsl_convolutionDepthwise_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xec, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -5838,7 +5837,7 @@ const unsigned char glsl_convolutionDepthwise_comp[] = { unsigned int glsl_convolutionDepthwise_comp_len = 3912; const unsigned char glsl_convolutionDepthwise_RELU_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -6174,7 +6173,7 @@ const unsigned char glsl_convolutionDepthwise_RELU_comp[] = { unsigned int glsl_convolutionDepthwise_RELU_comp_len = 3984; const unsigned char glsl_convolutionDepthwise_RELU6_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xf2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -6514,8 +6513,8 @@ const unsigned char glsl_convolutionDepthwise_RELU6_comp[] = { unsigned int glsl_convolutionDepthwise_RELU6_comp_len = 4032; const unsigned char glsl_gridSampleBilinear_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0xb4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0xb0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -6580,15 +6579,15 @@ const unsigned char glsl_gridSampleBilinear_comp[] = { 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x47, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x4c, 0x01, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x58, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x63, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x65, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x57, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x62, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x7b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x7d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x7f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x97, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x99, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0xb1, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0xb3, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, + 0x94, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x96, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0xad, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0xaf, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x15, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x16, 0x00, 0x03, 0x00, @@ -6757,52 +6756,52 @@ const unsigned char glsl_gridSampleBilinear_comp[] = { 0x06, 0x00, 0x00, 0x00, 0xd2, 0x00, 0x00, 0x00, 0xcb, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xd5, 0x00, 0x00, 0x00, 0xcf, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, - 0x82, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x52, 0x01, 0x00, 0x00, + 0x82, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x51, 0x01, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x08, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x53, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0x52, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x2d, 0x00, 0x00, 0x00, 0xcf, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0x52, 0x01, 0x00, 0x00, 0x82, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x56, 0x01, 0x00, 0x00, 0xb3, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, - 0x0c, 0x00, 0x08, 0x00, 0x06, 0x00, 0x00, 0x00, 0x57, 0x01, 0x00, 0x00, + 0x51, 0x01, 0x00, 0x00, 0x82, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x55, 0x01, 0x00, 0x00, 0xb3, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, + 0x0c, 0x00, 0x08, 0x00, 0x06, 0x00, 0x00, 0x00, 0x56, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x2d, 0x00, 0x00, 0x00, 0xcb, 0x00, 0x00, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x56, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, - 0x20, 0x00, 0x00, 0x00, 0x58, 0x01, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x5b, 0x01, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x55, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, + 0x20, 0x00, 0x00, 0x00, 0x57, 0x01, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x5a, 0x01, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x5d, 0x01, 0x00, 0x00, 0x5b, 0x01, 0x00, 0x00, - 0x53, 0x01, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, - 0x60, 0x01, 0x00, 0x00, 0x67, 0x00, 0x00, 0x00, 0xb3, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x62, 0x01, 0x00, 0x00, - 0x60, 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0x00, 0x00, 0x5f, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x00, - 0xb3, 0x01, 0x00, 0x00, 0xb2, 0x01, 0x00, 0x00, 0xb1, 0x01, 0x00, 0x00, + 0xad, 0x01, 0x00, 0x00, 0x75, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, + 0x64, 0x00, 0x04, 0x00, 0x1f, 0x00, 0x00, 0x00, 0xae, 0x01, 0x00, 0x00, + 0x57, 0x01, 0x00, 0x00, 0x5f, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x00, + 0xaf, 0x01, 0x00, 0x00, 0xae, 0x01, 0x00, 0x00, 0xad, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x6f, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x1a, 0x01, 0x00, 0x00, 0xd5, 0x00, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, 0x08, 0x00, 0x00, 0x00, 0x1c, 0x01, 0x00, 0x00, @@ -6818,14 +6817,14 @@ const unsigned char glsl_gridSampleBilinear_comp[] = { 0x26, 0x01, 0x00, 0x00, 0x26, 0x01, 0x00, 0x00, 0x26, 0x01, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, 0x09, 0x00, 0x00, 0x00, 0x2b, 0x01, 0x00, 0x00, 0xd7, 0x00, 0x00, 0x00, 0x27, 0x01, 0x00, 0x00, 0x85, 0x00, 0x05, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x2f, 0x01, 0x00, 0x00, 0x65, 0x01, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x2f, 0x01, 0x00, 0x00, 0x64, 0x01, 0x00, 0x00, 0x1d, 0x01, 0x00, 0x00, 0x85, 0x00, 0x05, 0x00, 0x09, 0x00, 0x00, 0x00, - 0x32, 0x01, 0x00, 0x00, 0x7f, 0x01, 0x00, 0x00, 0x21, 0x01, 0x00, 0x00, + 0x32, 0x01, 0x00, 0x00, 0x7d, 0x01, 0x00, 0x00, 0x21, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x09, 0x00, 0x00, 0x00, 0x33, 0x01, 0x00, 0x00, 0x2f, 0x01, 0x00, 0x00, 0x32, 0x01, 0x00, 0x00, 0x85, 0x00, 0x05, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x37, 0x01, 0x00, 0x00, 0x99, 0x01, 0x00, 0x00, + 0x09, 0x00, 0x00, 0x00, 0x37, 0x01, 0x00, 0x00, 0x96, 0x01, 0x00, 0x00, 0x1d, 0x01, 0x00, 0x00, 0x85, 0x00, 0x05, 0x00, 0x09, 0x00, 0x00, 0x00, - 0x3a, 0x01, 0x00, 0x00, 0xb3, 0x01, 0x00, 0x00, 0x21, 0x01, 0x00, 0x00, + 0x3a, 0x01, 0x00, 0x00, 0xaf, 0x01, 0x00, 0x00, 0x21, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x09, 0x00, 0x00, 0x00, 0x3b, 0x01, 0x00, 0x00, 0x37, 0x01, 0x00, 0x00, 0x3a, 0x01, 0x00, 0x00, 0x85, 0x00, 0x05, 0x00, 0x09, 0x00, 0x00, 0x00, 0x3f, 0x01, 0x00, 0x00, 0x33, 0x01, 0x00, 0x00, @@ -6844,8 +6843,8 @@ const unsigned char glsl_gridSampleBilinear_comp[] = { unsigned int glsl_gridSampleBilinear_comp_len = 3908; const unsigned char glsl_gridSampleBilinear_PAD_MODE_ZEROS_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0xfa, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0xf6, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -6913,15 +6912,15 @@ const unsigned char glsl_gridSampleBilinear_PAD_MODE_ZEROS_comp[] = { 0x68, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x73, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x75, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x8a, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x95, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x97, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0xac, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x89, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x94, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x96, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0xaa, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0xb5, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0xb7, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0xb9, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0xce, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0xd9, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0xdb, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, + 0xcb, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0xd6, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0xd8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x15, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x16, 0x00, 0x03, 0x00, @@ -7093,21 +7092,21 @@ const unsigned char glsl_gridSampleBilinear_PAD_MODE_ZEROS_comp[] = { 0xd4, 0x00, 0x00, 0x00, 0x53, 0x00, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xde, 0x00, 0x00, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x53, 0x00, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, - 0x5a, 0x01, 0x00, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0xaf, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, 0x5d, 0x01, 0x00, 0x00, + 0x59, 0x01, 0x00, 0x00, 0xd8, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0xaf, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, 0x5c, 0x01, 0x00, 0x00, 0xd8, 0x00, 0x00, 0x00, 0xc9, 0x00, 0x00, 0x00, 0xa6, 0x00, 0x05, 0x00, - 0x15, 0x00, 0x00, 0x00, 0x5e, 0x01, 0x00, 0x00, 0x5a, 0x01, 0x00, 0x00, - 0x5d, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, - 0x60, 0x01, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0xa6, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, 0x61, 0x01, 0x00, 0x00, - 0x5e, 0x01, 0x00, 0x00, 0x60, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, - 0x15, 0x00, 0x00, 0x00, 0x64, 0x01, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00, + 0x15, 0x00, 0x00, 0x00, 0x5d, 0x01, 0x00, 0x00, 0x59, 0x01, 0x00, 0x00, + 0x5c, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, + 0x5f, 0x01, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0xa6, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, 0x60, 0x01, 0x00, 0x00, + 0x5d, 0x01, 0x00, 0x00, 0x5f, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, + 0x15, 0x00, 0x00, 0x00, 0x63, 0x01, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00, 0xbc, 0x00, 0x00, 0x00, 0xa6, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, - 0x65, 0x01, 0x00, 0x00, 0x61, 0x01, 0x00, 0x00, 0x64, 0x01, 0x00, 0x00, - 0xf7, 0x00, 0x03, 0x00, 0x76, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xfa, 0x00, 0x04, 0x00, 0x65, 0x01, 0x00, 0x00, 0x66, 0x01, 0x00, 0x00, + 0x64, 0x01, 0x00, 0x00, 0x60, 0x01, 0x00, 0x00, 0x63, 0x01, 0x00, 0x00, + 0xf7, 0x00, 0x03, 0x00, 0x65, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xfa, 0x00, 0x04, 0x00, 0x64, 0x01, 0x00, 0x00, 0x66, 0x01, 0x00, 0x00, 0x67, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x66, 0x01, 0x00, 0x00, - 0xf9, 0x00, 0x02, 0x00, 0x76, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0xf9, 0x00, 0x02, 0x00, 0x65, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x67, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x2a, 0x00, 0x00, 0x00, 0x68, 0x01, 0x00, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x6b, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, @@ -7122,92 +7121,92 @@ const unsigned char glsl_gridSampleBilinear_PAD_MODE_ZEROS_comp[] = { 0x68, 0x01, 0x00, 0x00, 0x5f, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x00, 0x75, 0x01, 0x00, 0x00, 0x74, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, - 0x76, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x76, 0x01, 0x00, 0x00, - 0xf5, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x00, 0xf6, 0x01, 0x00, 0x00, + 0x65, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x65, 0x01, 0x00, 0x00, + 0xf5, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x00, 0xf2, 0x01, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0x66, 0x01, 0x00, 0x00, 0x75, 0x01, 0x00, 0x00, 0x67, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, - 0x7c, 0x01, 0x00, 0x00, 0xde, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, - 0xaf, 0x00, 0x05, 0x00, 0x15, 0x00, 0x00, 0x00, 0x7f, 0x01, 0x00, 0x00, + 0x7a, 0x01, 0x00, 0x00, 0xde, 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0x00, + 0xd6, 0x01, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, + 0xf9, 0x00, 0x02, 0x00, 0xc8, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0xc8, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x09, 0x00, 0x00, 0x00, + 0xf5, 0x01, 0x00, 0x00, 0x27, 0x00, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, + 0xd8, 0x01, 0x00, 0x00, 0xca, 0x01, 0x00, 0x00, 0x6f, 0x00, 0x04, 0x00, 0x08, 0x00, 0x00, 0x00, 0x23, 0x01, 0x00, 0x00, 0xde, 0x00, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, 0x08, 0x00, 0x00, 0x00, 0x25, 0x01, 0x00, 0x00, 0x23, 0x01, 0x00, 0x00, 0xd0, 0x00, 0x00, 0x00, 0x50, 0x00, 0x07, 0x00, @@ -7222,14 +7221,14 @@ const unsigned char glsl_gridSampleBilinear_PAD_MODE_ZEROS_comp[] = { 0x2f, 0x01, 0x00, 0x00, 0x2f, 0x01, 0x00, 0x00, 0x2f, 0x01, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, 0x09, 0x00, 0x00, 0x00, 0x34, 0x01, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, 0x30, 0x01, 0x00, 0x00, 0x85, 0x00, 0x05, 0x00, - 0x09, 0x00, 0x00, 0x00, 0x38, 0x01, 0x00, 0x00, 0xf6, 0x01, 0x00, 0x00, + 0x09, 0x00, 0x00, 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0x00, @@ -7248,7 +7247,7 @@ const unsigned char glsl_gridSampleBilinear_PAD_MODE_ZEROS_comp[] = { unsigned int glsl_gridSampleBilinear_PAD_MODE_ZEROS_comp_len = 4796; const unsigned char glsl_gridSampleNearest_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xcf, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -7516,7 +7515,7 @@ const unsigned char glsl_gridSampleNearest_comp[] = { unsigned int glsl_gridSampleNearest_comp_len = 3164; const unsigned char glsl_gridSampleNearest_PAD_MODE_ZEROS_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xf3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -7810,7 +7809,7 @@ const unsigned char glsl_gridSampleNearest_PAD_MODE_ZEROS_comp[] = { unsigned int glsl_gridSampleNearest_PAD_MODE_ZEROS_comp_len = 3476; const unsigned char glsl_relu6_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x4d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -7847,7 +7846,6 @@ const unsigned char glsl_relu6_comp[] = { 0x34, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x34, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x35, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x3d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x3d, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, @@ -7954,11 +7952,11 @@ const unsigned char glsl_relu6_comp[] = { 0xf9, 0x00, 0x02, 0x00, 0x2e, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x2e, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_relu6_comp_len = 1716; +unsigned int glsl_relu6_comp_len = 1704; const unsigned char glsl_binaryImage_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 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0x37, 0x00, 0x00, 0x00, - 0x66, 0x00, 0x00, 0x00, 0x7c, 0x00, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, - 0x3d, 0x00, 0x04, 0x00, 0x67, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x00, - 0x69, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x6a, 0x00, 0x00, 0x00, - 0x77, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, - 0x25, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, - 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 -}; -unsigned int glsl_binaryImage_MUL_comp_len = 2084; - -const unsigned char glsl_binaryImage_DIV_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, - 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, - 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, - 0x0e, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 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0x47, 0x00, 0x04, 0x00, + 0x14, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, + 0x03, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x3d, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, - 0x51, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x3d, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x70, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x70, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, @@ -8695,141 +8012,937 @@ const unsigned char glsl_binaryImage_DIV_comp[] = { 0x0b, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x17, 0x00, 0x04, 0x00, 0x11, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x1e, 0x00, 0x04, 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0x01, 0x00, 0x00, 0x00, + 0x28, 0x00, 0x00, 0x00, 0x6d, 0x00, 0x00, 0x00, 0x76, 0x00, 0x00, 0x00, + 0xf9, 0x00, 0x02, 0x00, 0x73, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0x73, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x37, 0x00, 0x00, 0x00, + 0x90, 0x00, 0x00, 0x00, 0x6d, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00, + 0x77, 0x00, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x7b, 0x00, 0x00, 0x00, 0x7a, 0x00, 0x00, 0x00, + 0x63, 0x00, 0x04, 0x00, 0x7b, 0x00, 0x00, 0x00, 0x88, 0x00, 0x00, 0x00, + 0x90, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_binaryImage_DIV_comp_len = 2224; +unsigned int glsl_binaryImage_DIV_comp_len = 2500; const unsigned char glsl_binaryImage_POW_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -8848,17 +8961,21 @@ const unsigned char glsl_binaryImage_POW_comp[] = { 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x74, 0x72, 0x69, 0x64, 0x65, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x70, 0x6f, 0x73, 0x4c, - 0x69, 0x6d, 0x69, 0x74, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x75, 0x43, 0x6f, 0x6e, 0x73, 0x74, 0x61, 0x6e, - 0x74, 0x00, 0x00, 0x00, 0x05, 0x00, 0x04, 0x00, 0x3d, 0x00, 0x00, 0x00, - 0x75, 0x49, 0x6e, 0x70, 0x75, 0x74, 0x30, 0x00, 0x05, 0x00, 0x04, 0x00, - 0x51, 0x00, 0x00, 0x00, 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0x6e, 0x70, + 0x75, 0x74, 0x31, 0x00, 0x05, 0x00, 0x04, 0x00, 0x73, 0x00, 0x00, 0x00, + 0x75, 0x4f, 0x75, 0x74, 0x70, 0x75, 0x74, 0x00, 0x47, 0x00, 0x04, 0x00, + 0x0d, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, + 0x10, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x12, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, @@ -8868,12 +8985,12 @@ const unsigned char glsl_binaryImage_POW_comp[] = { 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x47, 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, + 0x47, 0x00, 0x04, 0x00, 0x73, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x73, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x69, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x69, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, - 0x6e, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, + 0x73, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x73, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x03, 0x00, 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glsl_binaryImage_POW_comp_len = 2092; +unsigned int glsl_binaryImage_POW_comp_len = 2368; const unsigned char glsl_binaryImage_VMAX_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -9027,17 +9163,21 @@ const unsigned char glsl_binaryImage_VMAX_comp[] = { 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x74, 0x72, 0x69, 0x64, 0x65, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x70, 0x6f, 0x73, 0x4c, - 0x69, 0x6d, 0x69, 0x74, 0x00, 0x00, 0x00, 0x00, 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0x05, 0x00, 0x14, 0x00, 0x00, 0x00, 0x75, 0x43, 0x6f, 0x6e, + 0x73, 0x74, 0x61, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x05, 0x00, 0x04, 0x00, + 0x3d, 0x00, 0x00, 0x00, 0x75, 0x49, 0x6e, 0x70, 0x75, 0x74, 0x30, 0x00, + 0x05, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x75, 0x49, 0x6e, 0x70, + 0x75, 0x74, 0x31, 0x00, 0x05, 0x00, 0x04, 0x00, 0x73, 0x00, 0x00, 0x00, + 0x75, 0x4f, 0x75, 0x74, 0x70, 0x75, 0x74, 0x00, 0x47, 0x00, 0x04, 0x00, + 0x0d, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, + 0x10, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x12, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, @@ -9047,12 +9187,12 @@ const unsigned char glsl_binaryImage_VMAX_comp[] = { 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x47, 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x69, 0x00, 0x00, 0x00, + 0x47, 0x00, 0x04, 0x00, 0x73, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x73, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x69, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x69, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, - 0x6e, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, + 0x73, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x73, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x15, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, @@ -9064,130 +9204,149 @@ const unsigned char glsl_binaryImage_VMAX_comp[] = { 0x0b, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x17, 0x00, 0x04, 0x00, 0x11, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - 0x1e, 0x00, 0x04, 0x00, 0x12, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, - 0x11, 0x00, 0x00, 0x00, 0x20, 0x00, 0x04, 0x00, 0x13, 0x00, 0x00, 0x00, - 0x02, 0x00, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, - 0x13, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 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0x00, + 0x63, 0x00, 0x04, 0x00, 0x74, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, + 0x88, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_binaryImage_VMAX_comp_len = 2092; +unsigned int glsl_binaryImage_VMAX_comp_len = 2368; const unsigned char glsl_binaryImage_SQUDIFF_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x82, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -9206,17 +9365,21 @@ const unsigned char glsl_binaryImage_SQUDIFF_comp[] = { 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x74, 0x72, 0x69, 0x64, 0x65, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x70, 0x6f, 0x73, 0x4c, - 0x69, 0x6d, 0x69, 0x74, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x75, 0x43, 0x6f, 0x6e, 0x73, 0x74, 0x61, 0x6e, - 0x74, 0x00, 0x00, 0x00, 0x05, 0x00, 0x04, 0x00, 0x3d, 0x00, 0x00, 0x00, - 0x75, 0x49, 0x6e, 0x70, 0x75, 0x74, 0x30, 0x00, 0x05, 0x00, 0x04, 0x00, - 0x51, 0x00, 0x00, 0x00, 0x75, 0x49, 0x6e, 0x70, 0x75, 0x74, 0x31, 0x00, - 0x05, 0x00, 0x04, 0x00, 0x6d, 0x00, 0x00, 0x00, 0x75, 0x4f, 0x75, 0x74, - 0x70, 0x75, 0x74, 0x00, 0x47, 0x00, 0x04, 0x00, 0x0d, 0x00, 0x00, 0x00, - 0x0b, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, - 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x69, 0x6d, 0x69, 0x74, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x07, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x61, 0x63, 0x74, 0x69, + 0x76, 0x61, 0x74, 0x69, 0x6f, 0x6e, 0x54, 0x79, 0x70, 0x65, 0x00, 0x00, + 0x05, 0x00, 0x05, 0x00, 0x14, 0x00, 0x00, 0x00, 0x75, 0x43, 0x6f, 0x6e, + 0x73, 0x74, 0x61, 0x6e, 0x74, 0x00, 0x00, 0x00, 0x05, 0x00, 0x04, 0x00, + 0x3d, 0x00, 0x00, 0x00, 0x75, 0x49, 0x6e, 0x70, 0x75, 0x74, 0x30, 0x00, + 0x05, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x75, 0x49, 0x6e, 0x70, + 0x75, 0x74, 0x31, 0x00, 0x05, 0x00, 0x04, 0x00, 0x77, 0x00, 0x00, 0x00, + 0x75, 0x4f, 0x75, 0x74, 0x70, 0x75, 0x74, 0x00, 0x47, 0x00, 0x04, 0x00, + 0x0d, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, + 0x10, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x12, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, @@ -9226,12 +9389,12 @@ const unsigned char glsl_binaryImage_SQUDIFF_comp[] = { 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x47, 0x00, 0x04, 0x00, 0x6d, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x6d, 0x00, 0x00, 0x00, + 0x47, 0x00, 0x04, 0x00, 0x77, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x77, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x6d, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, - 0x6d, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, - 0x72, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, + 0x77, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, + 0x77, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, + 0x7c, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x13, 0x00, 0x02, 0x00, 0x02, 0x00, 0x00, 0x00, 0x21, 0x00, 0x03, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x15, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, @@ -9243,131 +9406,150 @@ const unsigned char glsl_binaryImage_SQUDIFF_comp[] = { 0x0b, 0x00, 0x00, 0x00, 0x3b, 0x00, 0x04, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x17, 0x00, 0x04, 0x00, 0x11, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x04, 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0x00, 0x00, 0x00, + 0x28, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, + 0xf9, 0x00, 0x02, 0x00, 0x70, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0x70, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x37, 0x00, 0x00, 0x00, + 0x8c, 0x00, 0x00, 0x00, 0x6a, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00, + 0x74, 0x00, 0x00, 0x00, 0x6f, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, + 0x75, 0x00, 0x00, 0x00, 0x78, 0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, + 0x63, 0x00, 0x04, 0x00, 0x78, 0x00, 0x00, 0x00, 0x85, 0x00, 0x00, 0x00, + 0x8c, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_binaryImage_SQUDIFF_comp_len = 2104; +unsigned int glsl_binaryImage_SQUDIFF_comp_len = 2380; const unsigned char glsl_binaryImage_VMIN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x7e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x89, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -9386,17 +9568,21 @@ const unsigned char glsl_binaryImage_VMIN_comp[] = { 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x73, 0x74, 0x72, 0x69, 0x64, 0x65, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x06, 0x00, 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x70, 0x6f, 0x73, 0x4c, - 0x69, 0x6d, 0x69, 0x74, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x05, 0x00, - 0x14, 0x00, 0x00, 0x00, 0x75, 0x43, 0x6f, 0x6e, 0x73, 0x74, 0x61, 0x6e, - 0x74, 0x00, 0x00, 0x00, 0x05, 0x00, 0x04, 0x00, 0x3d, 0x00, 0x00, 0x00, - 0x75, 0x49, 0x6e, 0x70, 0x75, 0x74, 0x30, 0x00, 0x05, 0x00, 0x04, 0x00, - 0x51, 0x00, 0x00, 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0x49, 0x6e, 0x70, + 0x75, 0x74, 0x31, 0x00, 0x05, 0x00, 0x04, 0x00, 0x73, 0x00, 0x00, 0x00, + 0x75, 0x4f, 0x75, 0x74, 0x70, 0x75, 0x74, 0x00, 0x47, 0x00, 0x04, 0x00, + 0x0d, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, + 0x10, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x12, 0x00, 0x00, 0x00, + 0x02, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x12, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x14, 0x00, 0x00, 0x00, @@ -9406,12 +9592,12 @@ const unsigned char glsl_binaryImage_VMIN_comp[] = { 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x51, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 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0x6c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0x6a, 0x00, 0x00, 0x00, 0x6b, 0x00, 0x00, 0x00, 0x6c, 0x00, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0x6b, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x07, 0x00, + 0x37, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x28, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x6f, 0x00, 0x00, 0x00, + 0xf9, 0x00, 0x02, 0x00, 0x6c, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0x6c, 0x00, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x37, 0x00, 0x00, 0x00, + 0x88, 0x00, 0x00, 0x00, 0x66, 0x00, 0x00, 0x00, 0x5e, 0x00, 0x00, 0x00, + 0x70, 0x00, 0x00, 0x00, 0x6b, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, + 0x71, 0x00, 0x00, 0x00, 0x74, 0x00, 0x00, 0x00, 0x73, 0x00, 0x00, 0x00, + 0x63, 0x00, 0x04, 0x00, 0x74, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, + 0x88, 0x00, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x25, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_binaryImage_VMIN_comp_len = 2092; +unsigned int glsl_binaryImage_VMIN_comp_len = 2368; const unsigned char glsl_matmul_input_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xc9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -9778,7 +9983,7 @@ const unsigned char glsl_matmul_input_comp[] = { unsigned int glsl_matmul_input_comp_len = 2744; const unsigned char glsl_matmul_input_TRANSPOSE_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xfa, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -10047,7 +10252,7 @@ const unsigned char glsl_matmul_input_TRANSPOSE_comp[] = { unsigned int glsl_matmul_input_TRANSPOSE_comp_len = 3176; const unsigned char glsl_nchwToimage_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -10319,7 +10524,7 @@ const unsigned char glsl_nchwToimage_comp[] = { unsigned int glsl_nchwToimage_comp_len = 3208; const unsigned char glsl_packAsImage4x4_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x13, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x32, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, @@ -10587,7 +10792,7 @@ const unsigned char glsl_packAsImage4x4_comp[] = { unsigned int glsl_packAsImage4x4_comp_len = 3160; const unsigned char glsl_packAsImage4x4_TRANSPOSE_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x44, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x32, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, @@ -10891,7 +11096,7 @@ const unsigned char glsl_packAsImage4x4_TRANSPOSE_comp[] = { unsigned int glsl_packAsImage4x4_TRANSPOSE_comp_len = 3592; const unsigned char glsl_roipooling_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x3d, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -11240,7 +11445,7 @@ const unsigned char glsl_roipooling_comp[] = { unsigned int glsl_roipooling_comp_len = 4140; const unsigned char glsl_blit_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -11430,7 +11635,7 @@ const unsigned char glsl_blit_comp[] = { unsigned int glsl_blit_comp_len = 2232; const unsigned char glsl_blit_image_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xdb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -11685,7 +11890,7 @@ const unsigned char glsl_blit_image_comp[] = { unsigned int glsl_blit_image_comp_len = 3004; const unsigned char glsl_fill_image_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -11795,7 +12000,7 @@ const unsigned char glsl_fill_image_comp[] = { unsigned int glsl_fill_image_comp_len = 1272; const unsigned char glsl_imageTonchw_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -11842,7 +12047,6 @@ const unsigned char glsl_imageTonchw_comp[] = { 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x35, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x47, 0x00, 0x03, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x44, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, @@ -12052,10 +12256,10 @@ const unsigned char glsl_imageTonchw_comp[] = { 0xf8, 0x00, 0x02, 0x00, 0x1f, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_imageTonchw_comp_len = 3064; +unsigned int glsl_imageTonchw_comp_len = 3052; const unsigned char glsl_softmaxHeight_NHWC_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xb9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -12278,7 +12482,7 @@ const unsigned char glsl_softmaxHeight_NHWC_comp[] = { unsigned int glsl_softmaxHeight_NHWC_comp_len = 2628; const unsigned char glsl_resizeNearest_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x9a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -12490,7 +12694,7 @@ const unsigned char glsl_resizeNearest_comp[] = { unsigned int glsl_resizeNearest_comp_len = 2488; const unsigned char glsl_reduce_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x7b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -12638,7 +12842,7 @@ const unsigned char glsl_reduce_comp[] = { unsigned int glsl_reduce_comp_len = 1720; const unsigned char glsl_reduce_VMAX_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -12809,7 +13013,7 @@ const unsigned char glsl_reduce_VMAX_comp[] = { unsigned int glsl_reduce_VMAX_comp_len = 1996; const unsigned char glsl_reduce_VMIN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -12980,7 +13184,7 @@ const unsigned char glsl_reduce_VMIN_comp[] = { unsigned int glsl_reduce_VMIN_comp_len = 1996; const unsigned char glsl_reduce_MEAN_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -13156,7 +13360,7 @@ const unsigned char glsl_reduce_MEAN_comp[] = { unsigned int glsl_reduce_MEAN_comp_len = 2060; const unsigned char glsl_reduce_PROD_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -13326,7 +13530,7 @@ const unsigned char glsl_reduce_PROD_comp[] = { unsigned int glsl_reduce_PROD_comp_len = 1988; const unsigned char glsl_reduce_SUM_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -13496,7 +13700,7 @@ const unsigned char glsl_reduce_SUM_comp[] = { unsigned int glsl_reduce_SUM_comp_len = 1988; const unsigned char glsl_resizeBilinear_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -13774,7 +13978,7 @@ const unsigned char glsl_resizeBilinear_comp[] = { unsigned int glsl_resizeBilinear_comp_len = 3288; const unsigned char glsl_nchwTonc4hw4_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x37, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -14088,7 +14292,7 @@ const unsigned char glsl_nchwTonc4hw4_comp[] = { unsigned int glsl_nchwTonc4hw4_comp_len = 3716; const unsigned char glsl_nc4hw4Tonchw_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x0b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -14372,7 +14576,7 @@ const unsigned char glsl_nc4hw4Tonchw_comp[] = { unsigned int glsl_nc4hw4Tonchw_comp_len = 3360; const unsigned char glsl_buffer2Image2D_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x49, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -14505,7 +14709,7 @@ const unsigned char glsl_buffer2Image2D_comp[] = { unsigned int glsl_buffer2Image2D_comp_len = 1544; const unsigned char glsl_im2col1x1_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xe3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -14773,7 +14977,7 @@ const unsigned char glsl_im2col1x1_comp[] = { unsigned int glsl_im2col1x1_comp_len = 3160; const unsigned char glsl_avgpool_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -15043,7 +15247,7 @@ const unsigned char glsl_avgpool_comp[] = { unsigned int glsl_avgpool_comp_len = 3184; const unsigned char glsl_unPackImage4x4_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xc5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -15273,7 +15477,7 @@ const unsigned char glsl_unPackImage4x4_comp[] = { unsigned int glsl_unPackImage4x4_comp_len = 2712; const unsigned char glsl_unPackImage4x4_TRANSPOSE_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xe6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -15539,7 +15743,7 @@ const unsigned char glsl_unPackImage4x4_TRANSPOSE_comp[] = { unsigned int glsl_unPackImage4x4_TRANSPOSE_comp_len = 3144; const unsigned char glsl_maxpool_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -15793,8 +15997,8 @@ const unsigned char glsl_maxpool_comp[] = { unsigned int glsl_maxpool_comp_len = 2996; const unsigned char glsl_winogradTransformDest2_3_1_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -16179,32 +16383,32 @@ const unsigned char glsl_winogradTransformDest2_3_1_comp[] = { 0x71, 0x00, 0x00, 0x00, 0x70, 0x01, 0x00, 0x00, 0x6e, 0x01, 0x00, 0x00, 0x4a, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x71, 0x01, 0x00, 0x00, 0x74, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x41, 0x00, 0x06, 0x00, - 0x14, 0x00, 0x00, 0x00, 0xb5, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0xb4, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, - 0x06, 0x00, 0x00, 0x00, 0xb6, 0x01, 0x00, 0x00, 0xb5, 0x01, 0x00, 0x00, - 0x41, 0x00, 0x05, 0x00, 0x1b, 0x00, 0x00, 0x00, 0xb7, 0x01, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0xb5, 0x01, 0x00, 0x00, 0xb4, 0x01, 0x00, 0x00, + 0x41, 0x00, 0x05, 0x00, 0x1b, 0x00, 0x00, 0x00, 0xb6, 0x01, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, - 0x12, 0x00, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, 0xb7, 0x01, 0x00, 0x00, - 0x7c, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0xb9, 0x01, 0x00, 0x00, - 0xb8, 0x01, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, - 0xba, 0x01, 0x00, 0x00, 0xb6, 0x01, 0x00, 0x00, 0xb9, 0x01, 0x00, 0x00, - 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xbb, 0x01, 0x00, 0x00, - 0x8a, 0x00, 0x00, 0x00, 0xba, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xbd, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, 0xb7, 0x01, 0x00, 0x00, 0xb6, 0x01, 0x00, 0x00, + 0x7c, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, + 0xb7, 0x01, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, + 0xb9, 0x01, 0x00, 0x00, 0xb5, 0x01, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, + 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xba, 0x01, 0x00, 0x00, + 0x8a, 0x00, 0x00, 0x00, 0xb9, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xbc, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x04, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xbe, 0x01, 0x00, 0x00, 0xbd, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0xc4, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xbe, 0x01, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, + 0xbd, 0x01, 0x00, 0x00, 0xbc, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, + 0xbe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xbd, 0x01, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, 0xbe, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xbf, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, - 0xb6, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xc4, 0x01, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xc4, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xc5, 0x01, 0x00, 0x00, 0xbd, 0x01, 0x00, 0x00, + 0xb5, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xbe, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xbe, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, 0xbc, 0x01, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, - 0xc5, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xbb, 0x01, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc5, 0x01, 0x00, 0x00, + 0xc4, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xba, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0x7b, 0x01, 0x00, 0x00, - 0xc6, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0xc5, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x74, 0x01, 0x00, 0x00, 0x7b, 0x01, 0x00, 0x00, 0x70, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x44, 0x01, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, @@ -16214,23 +16418,23 @@ const unsigned char glsl_winogradTransformDest2_3_1_comp[] = { 0x3d, 0x00, 0x04, 0x00, 0x71, 0x01, 0x00, 0x00, 0x85, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, - 0x87, 0x01, 0x00, 0x00, 0xba, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xd2, 0x01, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, + 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xce, 0x01, 0x00, 0x00, + 0x87, 0x01, 0x00, 0x00, 0xb9, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x04, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xd3, 0x01, 0x00, 0x00, 0xd2, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0xd9, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xd3, 0x01, 0x00, 0x00, 0xd4, 0x01, 0x00, 0x00, 0xd9, 0x01, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xd4, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xd8, 0x01, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, - 0xb6, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xd9, 0x01, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xd9, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, 0xd2, 0x01, 0x00, 0x00, - 0xc4, 0x01, 0x00, 0x00, 0xd8, 0x01, 0x00, 0x00, 0xd4, 0x01, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xdb, 0x01, 0x00, 0x00, - 0xda, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, + 0xd1, 0x01, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, + 0xd2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xd1, 0x01, 0x00, 0x00, 0xd3, 0x01, 0x00, 0x00, 0xd2, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xd3, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xd7, 0x01, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, + 0xb5, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xd2, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xd2, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xd8, 0x01, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, + 0xbe, 0x01, 0x00, 0x00, 0xd7, 0x01, 0x00, 0x00, 0xd3, 0x01, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xd9, 0x01, 0x00, 0x00, + 0xd8, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xce, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0x8c, 0x01, 0x00, 0x00, - 0xdb, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0xd9, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x85, 0x01, 0x00, 0x00, 0x8c, 0x01, 0x00, 0x00, 0x84, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0x91, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x56, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, @@ -16238,20 +16442,20 @@ const unsigned char glsl_winogradTransformDest2_3_1_comp[] = { 0x5c, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0x95, 0x01, 0x00, 0x00, 0x93, 0x01, 0x00, 0x00, 0x62, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x71, 0x01, 0x00, 0x00, 0x96, 0x01, 0x00, 0x00, - 0x73, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, 0xee, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, 0xbe, 0x01, 0x00, 0x00, - 0xe9, 0x01, 0x00, 0x00, 0xee, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, - 0xe9, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xed, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0xb6, 0x01, 0x00, 0x00, - 0xf9, 0x00, 0x02, 0x00, 0xee, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, - 0xee, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xef, 0x01, 0x00, 0x00, 0xbd, 0x01, 0x00, 0x00, 0xd9, 0x01, 0x00, 0x00, - 0xed, 0x01, 0x00, 0x00, 0xe9, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, - 0x06, 0x00, 0x00, 0x00, 0xf0, 0x01, 0x00, 0x00, 0xef, 0x01, 0x00, 0x00, - 0x21, 0x00, 0x00, 0x00, 0xbb, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, + 0x73, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, 0xe6, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, 0xbd, 0x01, 0x00, 0x00, + 0xe7, 0x01, 0x00, 0x00, 0xe6, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0xe7, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, + 0xeb, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0xb5, 0x01, 0x00, 0x00, + 0xf9, 0x00, 0x02, 0x00, 0xe6, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0xe6, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, + 0xec, 0x01, 0x00, 0x00, 0xbc, 0x01, 0x00, 0x00, 0xd2, 0x01, 0x00, 0x00, + 0xeb, 0x01, 0x00, 0x00, 0xe7, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x00, 0x00, 0xed, 0x01, 0x00, 0x00, 0xec, 0x01, 0x00, 0x00, + 0x21, 0x00, 0x00, 0x00, 0xba, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x9c, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, - 0x9d, 0x01, 0x00, 0x00, 0xf0, 0x01, 0x00, 0x00, 0x9c, 0x01, 0x00, 0x00, + 0x9d, 0x01, 0x00, 0x00, 0xed, 0x01, 0x00, 0x00, 0x9c, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x96, 0x01, 0x00, 0x00, 0x9d, 0x01, 0x00, 0x00, 0x95, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0xa2, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x5c, 0x01, 0x00, 0x00, @@ -16260,18 +16464,18 @@ const unsigned char glsl_winogradTransformDest2_3_1_comp[] = { 0x71, 0x00, 0x00, 0x00, 0xa6, 0x01, 0x00, 0x00, 0xa4, 0x01, 0x00, 0x00, 0x68, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x71, 0x01, 0x00, 0x00, 0xa7, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xd3, 0x01, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x03, 0x02, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xfe, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, - 0xb6, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x03, 0x02, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0x03, 0x02, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, 0xd2, 0x01, 0x00, 0x00, - 0xee, 0x01, 0x00, 0x00, 0x02, 0x02, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x05, 0x02, 0x00, 0x00, - 0x04, 0x02, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, + 0xfa, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xd1, 0x01, 0x00, 0x00, 0xfb, 0x01, 0x00, 0x00, 0xfa, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xfb, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0x87, 0x01, 0x00, 0x00, + 0xb5, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xfa, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xfa, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, + 0xe6, 0x01, 0x00, 0x00, 0xff, 0x01, 0x00, 0x00, 0xfb, 0x01, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x00, + 0x00, 0x02, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xce, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0xae, 0x01, 0x00, 0x00, - 0x05, 0x02, 0x00, 0x00, 0x9c, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0x01, 0x02, 0x00, 0x00, 0x9c, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0xa7, 0x01, 0x00, 0x00, 0xae, 0x01, 0x00, 0x00, 0xa6, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x53, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x53, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 @@ -16279,8 +16483,8 @@ const unsigned char glsl_winogradTransformDest2_3_1_comp[] = { unsigned int glsl_winogradTransformDest2_3_1_comp_len = 5784; const unsigned char glsl_winogradTransformDest2_3_1_RELU_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x10, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x0c, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -16671,32 +16875,32 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU_comp[] = { 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x70, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x75, 0x01, 0x00, 0x00, 0x78, 0x01, 0x00, 0x00, 0x77, 0x01, 0x00, 0x00, 0x41, 0x00, 0x06, 0x00, - 0x14, 0x00, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0xbe, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, - 0x06, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, - 0x41, 0x00, 0x05, 0x00, 0x1b, 0x00, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, 0xbe, 0x01, 0x00, 0x00, + 0x41, 0x00, 0x05, 0x00, 0x1b, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, - 0x12, 0x00, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, - 0x7c, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, - 0xc2, 0x01, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, - 0xc4, 0x01, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, - 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc5, 0x01, 0x00, 0x00, - 0x8a, 0x00, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, + 0x7c, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, + 0xc1, 0x01, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, + 0xc3, 0x01, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, + 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, + 0x8a, 0x00, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x04, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xc8, 0x01, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0xce, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xc8, 0x01, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, 0xce, 0x01, 0x00, 0x00, + 0xc7, 0x01, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, + 0xc8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xc7, 0x01, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, 0xc8, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xc9, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xcd, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, - 0xc0, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xce, 0x01, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xce, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xcf, 0x01, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, + 0xbf, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xc8, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xc8, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xce, 0x01, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0xcd, 0x01, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, - 0xcf, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xc5, 0x01, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xcf, 0x01, 0x00, 0x00, + 0xce, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0x7f, 0x01, 0x00, 0x00, - 0xd0, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0xcf, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x78, 0x01, 0x00, 0x00, 0x7f, 0x01, 0x00, 0x00, 0x74, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0x84, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x44, 0x01, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, @@ -16709,22 +16913,22 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU_comp[] = { 0x8b, 0x01, 0x00, 0x00, 0x77, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x8d, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, - 0xda, 0x01, 0x00, 0x00, 0x8d, 0x01, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, - 0xb1, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, + 0xd8, 0x01, 0x00, 0x00, 0x8d, 0x01, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, + 0xb1, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, 0x8d, 0x01, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x04, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xdd, 0x01, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, - 0xf7, 0x00, 0x03, 0x00, 0xe3, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xfa, 0x00, 0x04, 0x00, 0xdd, 0x01, 0x00, 0x00, 0xde, 0x01, 0x00, 0x00, - 0xe3, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xde, 0x01, 0x00, 0x00, - 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xe2, 0x01, 0x00, 0x00, - 0x8d, 0x01, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, - 0xe3, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xe3, 0x01, 0x00, 0x00, - 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, 0xe4, 0x01, 0x00, 0x00, - 0xdc, 0x01, 0x00, 0x00, 0xce, 0x01, 0x00, 0x00, 0xe2, 0x01, 0x00, 0x00, - 0xde, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, - 0xe5, 0x01, 0x00, 0x00, 0xe4, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, - 0xda, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, - 0x92, 0x01, 0x00, 0x00, 0xe5, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xdb, 0x01, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, + 0xf7, 0x00, 0x03, 0x00, 0xdc, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xfa, 0x00, 0x04, 0x00, 0xdb, 0x01, 0x00, 0x00, 0xdd, 0x01, 0x00, 0x00, + 0xdc, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xdd, 0x01, 0x00, 0x00, + 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xe1, 0x01, 0x00, 0x00, + 0x8d, 0x01, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, + 0xdc, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xdc, 0x01, 0x00, 0x00, + 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, 0xe2, 0x01, 0x00, 0x00, + 0xda, 0x01, 0x00, 0x00, 0xc8, 0x01, 0x00, 0x00, 0xe1, 0x01, 0x00, 0x00, + 0xdd, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, + 0xe3, 0x01, 0x00, 0x00, 0xe2, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, + 0xd8, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, + 0x92, 0x01, 0x00, 0x00, 0xe3, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x8b, 0x01, 0x00, 0x00, 0x92, 0x01, 0x00, 0x00, 0x8a, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0x97, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x56, 0x01, 0x00, 0x00, @@ -16735,20 +16939,20 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU_comp[] = { 0x9d, 0x01, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x9b, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x75, 0x01, 0x00, 0x00, 0x9e, 0x01, 0x00, 0x00, 0x77, 0x01, 0x00, 0x00, - 0xf7, 0x00, 0x03, 0x00, 0xf8, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xfa, 0x00, 0x04, 0x00, 0xc8, 0x01, 0x00, 0x00, 0xf3, 0x01, 0x00, 0x00, - 0xf8, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xf3, 0x01, 0x00, 0x00, - 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xf7, 0x01, 0x00, 0x00, - 0x8a, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, - 0xf8, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xf8, 0x01, 0x00, 0x00, - 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00, - 0xc7, 0x01, 0x00, 0x00, 0xe3, 0x01, 0x00, 0x00, 0xf7, 0x01, 0x00, 0x00, - 0xf3, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, - 0xfa, 0x01, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, - 0xc5, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, + 0xf7, 0x00, 0x03, 0x00, 0xf0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0xfa, 0x00, 0x04, 0x00, 0xc7, 0x01, 0x00, 0x00, 0xf1, 0x01, 0x00, 0x00, + 0xf0, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xf1, 0x01, 0x00, 0x00, + 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xf5, 0x01, 0x00, 0x00, + 0x8a, 0x00, 0x00, 0x00, 0xbf, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, + 0xf0, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xf0, 0x01, 0x00, 0x00, + 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, 0xf6, 0x01, 0x00, 0x00, + 0xc6, 0x01, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, 0xf5, 0x01, 0x00, 0x00, + 0xf1, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, + 0xf7, 0x01, 0x00, 0x00, 0xf6, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, + 0xc4, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xa4, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0xa5, 0x01, 0x00, 0x00, - 0xfa, 0x01, 0x00, 0x00, 0xa4, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0xf7, 0x01, 0x00, 0x00, 0xa4, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x9e, 0x01, 0x00, 0x00, 0xa5, 0x01, 0x00, 0x00, 0x9d, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0xaa, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x5c, 0x01, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, @@ -16759,18 +16963,18 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU_comp[] = { 0x01, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0xae, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x75, 0x01, 0x00, 0x00, 0xb1, 0x01, 0x00, 0x00, 0x77, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0x0d, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xdd, 0x01, 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, 0x0d, 0x02, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0x08, 0x02, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, 0x8d, 0x01, 0x00, 0x00, - 0xc0, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x0d, 0x02, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0x0d, 0x02, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0x0e, 0x02, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, - 0xf8, 0x01, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, 0x08, 0x02, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0f, 0x02, 0x00, 0x00, - 0x0e, 0x02, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, + 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xdb, 0x01, 0x00, 0x00, 0x05, 0x02, 0x00, 0x00, 0x04, 0x02, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0x05, 0x02, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0x09, 0x02, 0x00, 0x00, 0x8d, 0x01, 0x00, 0x00, + 0xbf, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x04, 0x02, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0x04, 0x02, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0x0a, 0x02, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, + 0xf0, 0x01, 0x00, 0x00, 0x09, 0x02, 0x00, 0x00, 0x05, 0x02, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0b, 0x02, 0x00, 0x00, + 0x0a, 0x02, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xd8, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, - 0x0f, 0x02, 0x00, 0x00, 0xa4, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0x0b, 0x02, 0x00, 0x00, 0xa4, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0xb1, 0x01, 0x00, 0x00, 0xb8, 0x01, 0x00, 0x00, 0xb0, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x53, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x53, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 @@ -16778,8 +16982,8 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU_comp[] = { unsigned int glsl_winogradTransformDest2_3_1_RELU_comp_len = 5940; const unsigned char glsl_winogradTransformDest2_3_1_RELU6_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0x12, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x0e, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -17174,32 +17378,32 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU6_comp[] = { 0x2b, 0x00, 0x00, 0x00, 0x70, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x75, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x77, 0x01, 0x00, 0x00, 0x7a, 0x01, 0x00, 0x00, 0x79, 0x01, 0x00, 0x00, 0x41, 0x00, 0x06, 0x00, - 0x14, 0x00, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, + 0x14, 0x00, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, - 0x06, 0x00, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, - 0x41, 0x00, 0x05, 0x00, 0x1b, 0x00, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, 0xc0, 0x01, 0x00, 0x00, + 0x41, 0x00, 0x05, 0x00, 0x1b, 0x00, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, - 0x12, 0x00, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, - 0x7c, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc5, 0x01, 0x00, 0x00, - 0xc4, 0x01, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, - 0xc6, 0x01, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, 0xc5, 0x01, 0x00, 0x00, - 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, - 0x8a, 0x00, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, 0xc3, 0x01, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, + 0x7c, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, + 0xc3, 0x01, 0x00, 0x00, 0x84, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, + 0xc5, 0x01, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, 0xc4, 0x01, 0x00, 0x00, + 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, + 0x8a, 0x00, 0x00, 0x00, 0xc5, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xc8, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x04, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xca, 0x01, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0xd0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xca, 0x01, 0x00, 0x00, 0xcb, 0x01, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, + 0xc9, 0x01, 0x00, 0x00, 0xc8, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, + 0xca, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xc9, 0x01, 0x00, 0x00, 0xcb, 0x01, 0x00, 0x00, 0xca, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0xcb, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0xcf, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, - 0xc2, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xd0, 0x01, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xd0, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xd1, 0x01, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, + 0xc1, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xca, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xca, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, 0xc8, 0x01, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0xcf, 0x01, 0x00, 0x00, 0xcb, 0x01, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xd2, 0x01, 0x00, 0x00, - 0xd1, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xd1, 0x01, 0x00, 0x00, + 0xd0, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0x81, 0x01, 0x00, 0x00, - 0xd2, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0xd1, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x7a, 0x01, 0x00, 0x00, 0x81, 0x01, 0x00, 0x00, 0x76, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0x86, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, 0x44, 0x01, 0x00, 0x00, 0x83, 0x00, 0x05, 0x00, @@ -17212,22 +17416,22 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU6_comp[] = { 0x77, 0x01, 0x00, 0x00, 0x8d, 0x01, 0x00, 0x00, 0x79, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, - 0x06, 0x00, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, - 0xc6, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xde, 0x01, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, - 0xa8, 0x00, 0x04, 0x00, 0x22, 0x00, 0x00, 0x00, 0xdf, 0x01, 0x00, 0x00, - 0xde, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, 0xe5, 0x01, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, 0xdf, 0x01, 0x00, 0x00, - 0xe0, 0x01, 0x00, 0x00, 0xe5, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, - 0xe0, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xe4, 0x01, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, 0xc2, 0x01, 0x00, 0x00, - 0xf9, 0x00, 0x02, 0x00, 0xe5, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, - 0xe5, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, - 0xe6, 0x01, 0x00, 0x00, 0xde, 0x01, 0x00, 0x00, 0xd0, 0x01, 0x00, 0x00, - 0xe4, 0x01, 0x00, 0x00, 0xe0, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, - 0x06, 0x00, 0x00, 0x00, 0xe7, 0x01, 0x00, 0x00, 0xe6, 0x01, 0x00, 0x00, - 0x21, 0x00, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, - 0x36, 0x00, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0xe7, 0x01, 0x00, 0x00, + 0x06, 0x00, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, + 0xc5, 0x01, 0x00, 0x00, 0xb1, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, + 0xdc, 0x01, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, + 0xa8, 0x00, 0x04, 0x00, 0x22, 0x00, 0x00, 0x00, 0xdd, 0x01, 0x00, 0x00, + 0xdc, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, 0xde, 0x01, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, 0xdd, 0x01, 0x00, 0x00, + 0xdf, 0x01, 0x00, 0x00, 0xde, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0xdf, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, + 0xe3, 0x01, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, 0xc1, 0x01, 0x00, 0x00, + 0xf9, 0x00, 0x02, 0x00, 0xde, 0x01, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, + 0xde, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, + 0xe4, 0x01, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, 0xca, 0x01, 0x00, 0x00, + 0xe3, 0x01, 0x00, 0x00, 0xdf, 0x01, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, + 0x06, 0x00, 0x00, 0x00, 0xe5, 0x01, 0x00, 0x00, 0xe4, 0x01, 0x00, 0x00, + 0x21, 0x00, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, + 0x36, 0x00, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0xe5, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0x8d, 0x01, 0x00, 0x00, 0x94, 0x01, 0x00, 0x00, 0x8c, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0x99, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, @@ -17239,19 +17443,19 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU6_comp[] = { 0x2b, 0x00, 0x00, 0x00, 0x9d, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x75, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x77, 0x01, 0x00, 0x00, 0xa0, 0x01, 0x00, 0x00, 0x79, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0xfa, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xca, 0x01, 0x00, 0x00, 0xf5, 0x01, 0x00, 0x00, 0xfa, 0x01, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xf5, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, - 0xc2, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xfa, 0x01, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0xfa, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0xfb, 0x01, 0x00, 0x00, 0xc9, 0x01, 0x00, 0x00, - 0xe5, 0x01, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00, 0xf5, 0x01, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, - 0xfb, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xc7, 0x01, 0x00, 0x00, + 0xf2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xc9, 0x01, 0x00, 0x00, 0xf3, 0x01, 0x00, 0x00, 0xf2, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xf3, 0x01, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xf7, 0x01, 0x00, 0x00, 0x8a, 0x00, 0x00, 0x00, + 0xc1, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0xf2, 0x01, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0xf2, 0x01, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0xf8, 0x01, 0x00, 0x00, 0xc8, 0x01, 0x00, 0x00, + 0xde, 0x01, 0x00, 0x00, 0xf7, 0x01, 0x00, 0x00, 0xf3, 0x01, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00, + 0xf8, 0x01, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xc6, 0x01, 0x00, 0x00, 0x80, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0xa6, 0x01, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, - 0x36, 0x00, 0x00, 0x00, 0xa7, 0x01, 0x00, 0x00, 0xfc, 0x01, 0x00, 0x00, + 0x36, 0x00, 0x00, 0x00, 0xa7, 0x01, 0x00, 0x00, 0xf9, 0x01, 0x00, 0x00, 0xa6, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0xa0, 0x01, 0x00, 0x00, 0xa7, 0x01, 0x00, 0x00, 0x9f, 0x01, 0x00, 0x00, 0x81, 0x00, 0x05, 0x00, 0x71, 0x00, 0x00, 0x00, 0xac, 0x01, 0x00, 0x00, 0x7d, 0x00, 0x00, 0x00, @@ -17263,18 +17467,18 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU6_comp[] = { 0x2b, 0x00, 0x00, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x73, 0x01, 0x00, 0x00, 0x75, 0x01, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x77, 0x01, 0x00, 0x00, 0xb3, 0x01, 0x00, 0x00, 0x79, 0x01, 0x00, 0x00, 0xf7, 0x00, 0x03, 0x00, - 0x0f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, - 0xdf, 0x01, 0x00, 0x00, 0x0a, 0x02, 0x00, 0x00, 0x0f, 0x02, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0x0a, 0x02, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, - 0x22, 0x00, 0x00, 0x00, 0x0e, 0x02, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, - 0xc2, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x0f, 0x02, 0x00, 0x00, - 0xf8, 0x00, 0x02, 0x00, 0x0f, 0x02, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, - 0x22, 0x00, 0x00, 0x00, 0x10, 0x02, 0x00, 0x00, 0xde, 0x01, 0x00, 0x00, - 0xfa, 0x01, 0x00, 0x00, 0x0e, 0x02, 0x00, 0x00, 0x0a, 0x02, 0x00, 0x00, - 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x11, 0x02, 0x00, 0x00, - 0x10, 0x02, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, + 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x04, 0x00, + 0xdd, 0x01, 0x00, 0x00, 0x07, 0x02, 0x00, 0x00, 0x06, 0x02, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0x07, 0x02, 0x00, 0x00, 0xaf, 0x00, 0x05, 0x00, + 0x22, 0x00, 0x00, 0x00, 0x0b, 0x02, 0x00, 0x00, 0x8f, 0x01, 0x00, 0x00, + 0xc1, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x06, 0x02, 0x00, 0x00, + 0xf8, 0x00, 0x02, 0x00, 0x06, 0x02, 0x00, 0x00, 0xf5, 0x00, 0x07, 0x00, + 0x22, 0x00, 0x00, 0x00, 0x0c, 0x02, 0x00, 0x00, 0xdc, 0x01, 0x00, 0x00, + 0xf2, 0x01, 0x00, 0x00, 0x0b, 0x02, 0x00, 0x00, 0x07, 0x02, 0x00, 0x00, + 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, 0x0d, 0x02, 0x00, 0x00, + 0x0c, 0x02, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0xda, 0x01, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x36, 0x00, 0x00, 0x00, 0xba, 0x01, 0x00, 0x00, - 0x11, 0x02, 0x00, 0x00, 0xa6, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, + 0x0d, 0x02, 0x00, 0x00, 0xa6, 0x01, 0x00, 0x00, 0x63, 0x00, 0x04, 0x00, 0xb3, 0x01, 0x00, 0x00, 0xba, 0x01, 0x00, 0x00, 0xb2, 0x01, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, 0x53, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x53, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 @@ -17282,8 +17486,8 @@ const unsigned char glsl_winogradTransformDest2_3_1_RELU6_comp[] = { unsigned int glsl_winogradTransformDest2_3_1_RELU6_comp_len = 6000; const unsigned char glsl_winogradTransformSource2_3_1_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, - 0xa5, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, + 0x95, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, @@ -17501,291 +17705,291 @@ const unsigned char glsl_winogradTransformSource2_3_1_comp[] = { 0x82, 0x00, 0x05, 0x00, 0x06, 0x00, 0x00, 0x00, 0x84, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x83, 0x00, 0x00, 0x00, 0x3d, 0x00, 0x04, 0x00, 0x8a, 0x00, 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x8c, 0x00, 0x00, 0x00, - 0x41, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x58, 0x02, 0x00, 0x00, + 0x41, 0x00, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x57, 0x02, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, - 0x3d, 0x00, 0x04, 0x00, 0x06, 0x00, 0x00, 0x00, 0x59, 0x02, 0x00, 0x00, - 0x58, 0x02, 0x00, 0x00, 0x41, 0x00, 0x05, 0x00, 0x1b, 0x00, 0x00, 0x00, - 0x5a, 0x02, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x1a, 0x00, 0x00, 0x00, - 0x3d, 0x00, 0x04, 0x00, 0x12, 0x00, 0x00, 0x00, 0x5b, 0x02, 0x00, 0x00, - 0x5a, 0x02, 0x00, 0x00, 0x7c, 0x00, 0x04, 0x00, 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0x00, + 0x8d, 0x03, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x8e, 0x03, 0x00, 0x00, + 0xaf, 0x00, 0x05, 0x00, 0x22, 0x00, 0x00, 0x00, 0x92, 0x03, 0x00, 0x00, + 0xb1, 0x00, 0x00, 0x00, 0x58, 0x02, 0x00, 0x00, 0xf9, 0x00, 0x02, 0x00, + 0x8d, 0x03, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x8d, 0x03, 0x00, 0x00, + 0xf5, 0x00, 0x07, 0x00, 0x22, 0x00, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, + 0x9b, 0x02, 0x00, 0x00, 0x79, 0x03, 0x00, 0x00, 0x92, 0x03, 0x00, 0x00, + 0x8e, 0x03, 0x00, 0x00, 0xa9, 0x00, 0x06, 0x00, 0x06, 0x00, 0x00, 0x00, + 0x94, 0x03, 0x00, 0x00, 0x93, 0x03, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, + 0x99, 0x02, 0x00, 0x00, 0x50, 0x00, 0x05, 0x00, 0x35, 0x00, 0x00, 0x00, + 0x3a, 0x01, 0x00, 0x00, 0x94, 0x03, 0x00, 0x00, 0x18, 0x01, 0x00, 0x00, 0x64, 0x00, 0x04, 0x00, 0x89, 0x00, 0x00, 0x00, 0x3b, 0x01, 0x00, 0x00, 0x8d, 0x00, 0x00, 0x00, 0x5f, 0x00, 0x07, 0x00, 0x86, 0x00, 0x00, 0x00, 0x3c, 0x01, 0x00, 0x00, 0x3b, 0x01, 0x00, 0x00, 0x3a, 0x01, 0x00, 0x00, @@ -18018,7 +18222,7 @@ const unsigned char glsl_winogradTransformSource2_3_1_comp[] = { unsigned int glsl_winogradTransformSource2_3_1_comp_len = 8776; const unsigned char glsl_col2Im_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xbb, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -18254,7 +18458,7 @@ const unsigned char glsl_col2Im_comp[] = { unsigned int glsl_col2Im_comp_len = 2784; const unsigned char glsl_col2Im_RELU_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xbf, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -18496,7 +18700,7 @@ const unsigned char glsl_col2Im_RELU_comp[] = { unsigned int glsl_col2Im_RELU_comp_len = 2856; const unsigned char glsl_col2Im_RELU6_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -18742,7 +18946,7 @@ const unsigned char glsl_col2Im_RELU6_comp[] = { unsigned int glsl_col2Im_RELU6_comp_len = 2904; const unsigned char glsl_nc4hw4toimage_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x86, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -18936,7 +19140,7 @@ const unsigned char glsl_nc4hw4toimage_comp[] = { unsigned int glsl_nc4hw4toimage_comp_len = 2280; const unsigned char glsl_imageTonc4hw4_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x8b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, 0x2e, 0x73, 0x74, 0x64, 0x2e, 0x34, 0x35, 0x30, @@ -18983,7 +19187,6 @@ const unsigned char glsl_imageTonc4hw4_comp[] = { 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x35, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x47, 0x00, 0x03, 0x00, 0x3a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x48, 0x00, 0x05, 0x00, 0x45, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, @@ -19129,10 +19332,10 @@ const unsigned char glsl_imageTonc4hw4_comp[] = { 0xf8, 0x00, 0x02, 0x00, 0x1f, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_imageTonc4hw4_comp_len = 2296; +unsigned int glsl_imageTonc4hw4_comp_len = 2284; const unsigned char glsl_matmul_output_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -19356,7 +19559,7 @@ const unsigned char glsl_matmul_output_comp[] = { unsigned int glsl_matmul_output_comp_len = 2632; const unsigned char glsl_matmul_output_BIAS_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xc8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -19598,7 +19801,7 @@ const unsigned char glsl_matmul_output_BIAS_comp[] = { unsigned int glsl_matmul_output_BIAS_comp_len = 2856; const unsigned char glsl_matmul_output_TRANSPOSE_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xd2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -19858,7 +20061,7 @@ const unsigned char glsl_matmul_output_TRANSPOSE_comp[] = { unsigned int glsl_matmul_output_TRANSPOSE_comp_len = 3064; const unsigned char glsl_matmul_output_TRANSPOSE_BIAS_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0xe9, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -20136,7 +20339,7 @@ const unsigned char glsl_matmul_output_TRANSPOSE_BIAS_comp[] = { unsigned int glsl_matmul_output_TRANSPOSE_BIAS_comp_len = 3288; const unsigned char glsl_gemm16x16_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x73, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -20483,7 +20686,7 @@ const unsigned char glsl_gemm16x16_comp[] = { unsigned int glsl_gemm16x16_comp_len = 4108; const unsigned char glsl_gemm16x16_FP16_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x59, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x09, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, @@ -20852,7 +21055,7 @@ const unsigned char glsl_gemm16x16_FP16_comp[] = { unsigned int glsl_gemm16x16_FP16_comp_len = 4372; const unsigned char glsl_deconvolutionDepthwise_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -21211,7 +21414,7 @@ const unsigned char glsl_deconvolutionDepthwise_comp[] = { unsigned int glsl_deconvolutionDepthwise_comp_len = 4260; const unsigned char glsl_deconvolutionDepthwise_RELU_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x09, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -21576,7 +21779,7 @@ const unsigned char glsl_deconvolutionDepthwise_RELU_comp[] = { unsigned int glsl_deconvolutionDepthwise_RELU_comp_len = 4332; const unsigned char glsl_deconvolutionDepthwise_RELU6_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x0b, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -21945,7 +22148,7 @@ const unsigned char glsl_deconvolutionDepthwise_RELU6_comp[] = { unsigned int glsl_deconvolutionDepthwise_RELU6_comp_len = 4380; const unsigned char glsl_preluWithChannel_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x7b, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -21990,7 +22193,6 @@ const unsigned char glsl_preluWithChannel_comp[] = { 0x5b, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x5b, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x5c, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x5f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x03, 0x00, 0x72, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, 0x72, 0x00, 0x00, 0x00, 0x22, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x47, 0x00, 0x04, 0x00, @@ -22121,10 +22323,10 @@ const unsigned char glsl_preluWithChannel_comp[] = { 0xf9, 0x00, 0x02, 0x00, 0x3a, 0x00, 0x00, 0x00, 0xf8, 0x00, 0x02, 0x00, 0x3a, 0x00, 0x00, 0x00, 0xfd, 0x00, 0x01, 0x00, 0x38, 0x00, 0x01, 0x00 }; -unsigned int glsl_preluWithChannel_comp_len = 2100; +unsigned int glsl_preluWithChannel_comp_len = 2088; const unsigned char glsl_deconvIm2Col_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x3a, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -22489,7 +22691,7 @@ const unsigned char glsl_deconvIm2Col_comp[] = { unsigned int glsl_deconvIm2Col_comp_len = 4328; const unsigned char glsl_deconvIm2Col_RELU_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x3e, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -22860,7 +23062,7 @@ const unsigned char glsl_deconvIm2Col_RELU_comp[] = { unsigned int glsl_deconvIm2Col_RELU_comp_len = 4400; const unsigned char glsl_deconvIm2Col_RELU6_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -23235,7 +23437,7 @@ const unsigned char glsl_deconvIm2Col_RELU6_comp[] = { unsigned int glsl_deconvIm2Col_RELU6_comp_len = 4448; const unsigned char glsl_buffer2Image1D_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x2c, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, @@ -23343,7 +23545,7 @@ const unsigned char glsl_buffer2Image1D_comp[] = { unsigned int glsl_buffer2Image1D_comp_len = 1244; const unsigned char glsl_scale_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, @@ -23531,7 +23733,7 @@ const unsigned char glsl_scale_comp[] = { unsigned int glsl_scale_comp_len = 2204; const unsigned char glsl_buffer2Image3D_comp[] = { - 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x0a, 0x00, 0x08, 0x00, + 0x03, 0x02, 0x23, 0x07, 0x00, 0x00, 0x01, 0x00, 0x08, 0x00, 0x08, 0x00, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x01, 0x00, 0x00, 0x00, 0x11, 0x00, 0x02, 0x00, 0x38, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x06, 0x00, 0x01, 0x00, 0x00, 0x00, 0x47, 0x4c, 0x53, 0x4c, diff --git a/source/backend/vulkan/execution/VulkanBinary.cpp b/source/backend/vulkan/execution/VulkanBinary.cpp index fe97cc017..a84751327 100644 --- a/source/backend/vulkan/execution/VulkanBinary.cpp +++ b/source/backend/vulkan/execution/VulkanBinary.cpp @@ -16,6 +16,7 @@ namespace MNN { struct ConstBuffer { ivec4 stride00; ivec4 posLimit; + int activationType; }; static std::string _getShaderName(const Op* op, bool image) { std::string prefix = "glsl_binaryImage_"; @@ -79,7 +80,7 @@ static std::string _getShaderName(const Op* op, bool image) { return prefix + mid + posfix; } -VulkanBinary::VulkanBinary(const std::string& shaderName, Backend* bn, bool image) : VulkanBasicExecution(bn) { +VulkanBinary::VulkanBinary(const std::string& shaderName, Backend* bn, bool image, int activationType) : VulkanBasicExecution(bn) { auto vkBn = static_cast(bn); mBinaryPipeline = vkBn->getPipeline(shaderName, { VK_DESCRIPTOR_TYPE_STORAGE_IMAGE, @@ -87,6 +88,7 @@ VulkanBinary::VulkanBinary(const std::string& shaderName, Backend* bn, bool imag VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER, VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER }); + mActivationType = activationType; } VulkanBinary::~VulkanBinary() { @@ -118,6 +120,7 @@ ErrorCode VulkanBinary::onEncode(const std::vector& inputs, const std:: binaryOpParam->stride00[2] = 0; binaryOpParam->posLimit[0] = 1; binaryOpParam->posLimit[1] = 1; + binaryOpParam->activationType = mActivationType; if (input0Scalar) { binaryOpParam->posLimit[0] = 0; } @@ -165,7 +168,11 @@ public: if (shader.empty()) { return nullptr; } - return new VulkanBinary(shader, backend, image); + int activationType = 0; + if(op->type() == OpType_BinaryOp) { + activationType = op->main_as_BinaryOp()->activationType(); + } + return new VulkanBinary(shader, backend, image, activationType); } }; diff --git a/source/backend/vulkan/execution/VulkanBinary.hpp b/source/backend/vulkan/execution/VulkanBinary.hpp index 21f6d1d53..3aa78a821 100644 --- a/source/backend/vulkan/execution/VulkanBinary.hpp +++ b/source/backend/vulkan/execution/VulkanBinary.hpp @@ -15,7 +15,7 @@ namespace MNN { class VulkanBinary : public VulkanBasicExecution { public: - VulkanBinary(const std::string& shaderName, Backend* bn, bool image); + VulkanBinary(const std::string& shaderName, Backend* bn, bool image, int activationType = 0); virtual ~VulkanBinary(); ErrorCode onEncode(const std::vector& inputs, const std::vector& outputs, @@ -25,6 +25,7 @@ private: std::vector> mConstBuffer; const VulkanPipeline* mBinaryPipeline; std::vector> mDescriptorSet; + int mActivationType = 0; }; } // namespace MNN diff --git a/source/backend/vulkan/execution/glsl/binaryImage.comp b/source/backend/vulkan/execution/glsl/binaryImage.comp index d0ce988a4..5e79b2256 100644 --- a/source/backend/vulkan/execution/glsl/binaryImage.comp +++ b/source/backend/vulkan/execution/glsl/binaryImage.comp @@ -6,6 +6,7 @@ layout(set=0, binding=2) uniform sampler2D uInput1; layout(set=0, binding=3) uniform constBuffer{ ivec4 stride00;//WHC, LIMIT ivec4 posLimit; + int activationType; } uConstant; layout(local_size_x = 256, local_size_y = 1, local_size_z = 1) in; @@ -53,6 +54,9 @@ void main() #ifdef SQUDIFF value = (x0 - x1) * (x0 - x1); #endif + if(uConstant.activationType == 1) { + value = max(value, vec4(0)); + } imageStore(uOutput, pos.xy, value); } diff --git a/source/common/WinogradInt8Attr.hpp b/source/common/WinogradInt8Attr.hpp index a5b6bd083..01180d842 100644 --- a/source/common/WinogradInt8Attr.hpp +++ b/source/common/WinogradInt8Attr.hpp @@ -15,7 +15,7 @@ #include "core/Macro.h" namespace MNN { -class MNN_PUBLIC WinogradInt8Attr { +class WinogradInt8Attr { public: struct Attr { int kyStart, kxStart, kernelY, kernelX, unitY, unitX; diff --git a/source/core/Backend.hpp b/source/core/Backend.hpp index edababf14..fc403f853 100644 --- a/source/core/Backend.hpp +++ b/source/core/Backend.hpp @@ -22,8 +22,11 @@ struct Op; class Execution; class Runtime; +class Backend; +using ReuseCopyTensorMap = std::map, std::tuple>; /** abstract backend */ class Backend : public NonCopyable { + public: /** info used to create backend */ struct Info { @@ -119,6 +122,10 @@ public: */ virtual void onExecuteEnd() const = 0; + virtual const Runtime* getRuntime() { + return nullptr; + } + public: /** * @brief allocate buffer of tensor for given storage type. @@ -258,7 +265,7 @@ public: const MNN::Op* op, OpInfo& dstInfo) const { return true; } - + // FIXME: Temply use to mask cache valid, in future will delete virtual void onMaskOpReady(const std::vector& inputs, const std::vector& outputs, const MNN::Op* op) { @@ -268,6 +275,7 @@ public: bool hasAsyncWork() const; void setAsyncWork(std::future&& future); MNN_PUBLIC void waitAsyncWork(); + private: std::future mFuture; }; diff --git a/source/core/BackendRegister.cpp b/source/core/BackendRegister.cpp index 5cde31e4e..d0c2c3324 100644 --- a/source/core/BackendRegister.cpp +++ b/source/core/BackendRegister.cpp @@ -22,6 +22,9 @@ extern void registerMetalRuntimeCreator(); #if MNN_COREML_ENABLED extern void registerCoreMLRuntimeCreator(); #endif +#if MNN_NNAPI_ENABLED +extern void registerNNAPIRuntimeCreator(); +#endif static std::once_flag s_flag; void registerBackend() { @@ -37,6 +40,9 @@ void registerBackend() { #if MNN_COREML_ENABLED registerCoreMLRuntimeCreator(); #endif +#ifdef MNN_NNAPI_ENABLED + registerNNAPIRuntimeCreator(); +#endif #if MNN_METAL_ENABLED registerMetalRuntimeCreator(); #endif diff --git a/source/core/Interpreter.cpp b/source/core/Interpreter.cpp index c257793e0..255a2d54b 100644 --- a/source/core/Interpreter.cpp +++ b/source/core/Interpreter.cpp @@ -19,6 +19,7 @@ #include "core/RuntimeFactory.hpp" #include "core/Session.hpp" #include +#include "backend/cpu/CPUBackend.hpp" #ifdef MNN_INTERNAL_ENABLED #include "internal/logging/Log.hpp" @@ -447,6 +448,10 @@ void Interpreter::resizeSession(Session* session, int needRelloc) { if (1 == needRelloc) { session->setNeedMalloc(true); } + + CPURuntime* runtime = static_cast(session->getCPURuntime()); + runtime->clearReuseCopyTensorMap(); + session->resize(); } diff --git a/source/core/OpCommonUtils.cpp b/source/core/OpCommonUtils.cpp index e8c0e5fe0..07389c756 100644 --- a/source/core/OpCommonUtils.cpp +++ b/source/core/OpCommonUtils.cpp @@ -102,7 +102,7 @@ static std::tuple _computeStride(const std::tuple& return std::make_tuple(inside, axis, outside); } bool OpCommonUtils::canBlitFast(const Tensor::InsideDescribe::Region& region, const SPLITS& srcSplits, - const SPLITS& dstSplits, int pack, bool swapnc) { + const SPLITS& dstSplits, int pack, bool swapnc, bool swapcw) { int srcCOffset = (region.src.offset / std::get<0>(srcSplits)) % std::get<1>(srcSplits); if (srcCOffset % pack != 0) { return false; @@ -129,6 +129,11 @@ bool OpCommonUtils::canBlitFast(const Tensor::InsideDescribe::Region& region, co if (std::get<1>(srcFused)) { return false; } + } else if (swapcw) { + // nc can't be fused + if (std::get<0>(srcFused)) { + return false; + } } else { // nw can't be fused if (std::get<2>(srcFused)) { @@ -143,6 +148,11 @@ bool OpCommonUtils::canBlitFast(const Tensor::InsideDescribe::Region& region, co if (std::get<1>(dstFused)) { return false; } + } else if (swapcw) { + // nc can't be fused + if (std::get<0>(dstFused)) { + return false; + } } else { // nw can't be fused if (std::get<2>(dstFused)) { @@ -249,7 +259,7 @@ void OpCommonUtils::turnToPackRegion(const Tensor::InsideDescribe::Region& regio // c4Region.dst.stride[0], c4Region.dst .stride[1], c4Region.dst.stride[2]); } -bool OpCommonUtils::canBlitFast(const Tensor::InsideDescribe::Region& region, const Tensor* dest, int pack, bool swapnc) { +bool OpCommonUtils::canBlitFast(const Tensor::InsideDescribe::Region& region, const Tensor* dest, int pack, bool swapnc, bool swapcw) { auto src = region.origin; int srcArea = 1; // FIXME: Support dimensions = 1 @@ -280,7 +290,7 @@ bool OpCommonUtils::canBlitFast(const Tensor::InsideDescribe::Region& region, co dstChannel = dest->length(1); } return canBlitFast(region, std::make_tuple(srcArea, inputChannel, inputBatch), - std::make_tuple(dstArea, dstChannel, dstBatch), pack, swapnc); + std::make_tuple(dstArea, dstChannel, dstBatch), pack, swapnc, swapcw); } void OpCommonUtils::turnToPackRegion(const Tensor::InsideDescribe::Region& region, diff --git a/source/core/OpCommonUtils.hpp b/source/core/OpCommonUtils.hpp index ecd17696d..ccc6f5343 100644 --- a/source/core/OpCommonUtils.hpp +++ b/source/core/OpCommonUtils.hpp @@ -23,14 +23,14 @@ public: static int computeStride(int32_t* strides, const int* shape, int length); static void* blobData(const Op* op); - static bool canBlitFast(const Tensor::InsideDescribe::Region& region, const Tensor* dest, int pack = 4, bool swapnc = false); + static bool canBlitFast(const Tensor::InsideDescribe::Region& region, const Tensor* dest, int pack = 4, bool swapnc = false, bool swapcw = false); static void turnToPackRegion(const Tensor::InsideDescribe::Region& region, Tensor::InsideDescribe::Region& c4Region, const Tensor* dest, int pack = 4, bool swapnc = false); // Inside - Axis - Outside typedef std::tuple SPLITS; static bool canBlitFast(const Tensor::InsideDescribe::Region& region, const SPLITS& srcSplits, - const SPLITS& dstSplits, int pack = 4, bool swapnc = false); + const SPLITS& dstSplits, int pack = 4, bool swapnc = false, bool swapcw = false); static void turnToPackRegion(const Tensor::InsideDescribe::Region& region, Tensor::InsideDescribe::Region& c4Region, const SPLITS& srcSplits, const SPLITS& dstSplits, int pack = 4, bool swapnc = false); static bool opNeedContent(int type, int index); diff --git a/source/core/Pipeline.cpp b/source/core/Pipeline.cpp index 2152b4101..b3818ed6c 100644 --- a/source/core/Pipeline.cpp +++ b/source/core/Pipeline.cpp @@ -428,7 +428,59 @@ void Pipeline::_recycleDynamicMemory(Command* command) { } } +void _reorderOpCommandList(Tensor* reuseTensor, Tensor* replacedTensor, std::vector>::iterator& cmdIterP, std::vector& info) { + for (auto& skipInfo : info) { + auto& skipBuffer = skipInfo.executeBuffer; + for (auto& skipComandP : skipBuffer.command) { + + auto& skipComand = *skipComandP; + // MNN_PRINT("search skip command, optype:%s, name:%s, input0:%p\n", + // EnumNameOpType(skipComand.op->type()), skipComand.info->name().c_str(), skipComand.inputs[0]); + if (skipComandP.get() == cmdIterP->get()) { + continue; + } + bool isSkipRaster = skipComand.op->type() == OpType_Raster; + for (int iInput = 0; iInput < skipComand.inputs.size(); ++iInput) { + + auto iTensor = skipComand.inputs[iInput]; + if (iTensor == replacedTensor) { + // MNN_PRINT("input, inside skipExecution optype:%s, name:%s, replace input:%p, with:%p\n", + // EnumNameOpType(skipComand.op->type()), skipComand.info->name().c_str(), iTensor, reuseTensor); + + skipComand.inputs[iInput] = reuseTensor; + TensorUtils::getDescribe(reuseTensor)->useCount++; + } else if (isSkipRaster) { + auto des = TensorUtils::getDescribe(iTensor); + for (int ir = 0; ir < des->regions.size(); ++ir) { + auto origin = des->regions[ir].origin; + if (origin == replacedTensor) { + des->regions[ir].origin = reuseTensor; + TensorUtils::getDescribe(reuseTensor)->useCount++; + // MNN_PRINT("input, inside skipExecution optype:%s, name:%s, replace input:%p, raster region:%p, with:%p\n", + // EnumNameOpType(skipComand.op->type()), skipComand.info->name().c_str(), iTensor, origin, reuseTensor); + } + } + } + } + + if (isSkipRaster) { + for (int iOputput = 0; iOputput < skipComand.outputs.size(); ++iOputput) { + if (skipComand.outputs[iOputput] == replacedTensor) { + // MNN_PRINT("output, inside skipExecution optype:%s, name:%s, replace raster output:%p, with:%p\n", + // EnumNameOpType(skipComand.op->type()), skipComand.info->name().c_str(), skipComand.outputs[iOputput], reuseTensor); + skipComand.outputs[iOputput] = reuseTensor; + TensorUtils::getDescribe(reuseTensor)->useCount++; + } + } + } + } + } + return; +} + + ErrorCode Pipeline::allocMemory(bool firstMalloc) { + // MNN_PRINT("allocMemory mtype:%d, cpubackendType:%d, cpuBackend runtime:%p\n", mBackend->type(), mBackupBackend->type(), mBackupBackend->getRuntime()); if (!firstMalloc) { // For session setNeedMalloc, if session's output is set as some input, It may cause error // Dup des to avoid it @@ -461,8 +513,10 @@ ErrorCode Pipeline::allocMemory(bool firstMalloc) { // Compute RefCount for (auto& info : mInfo) { auto& buffer = info.executeBuffer; + // MNN_PRINT("before resize, mInfo size:%lu, command size:%lu,op type:%s, op name:%s\n", mInfo.size(), buffer.command.size(), EnumNameOpType(info.op->type()), info.op->name()->c_str()); for (auto& iterP : buffer.command) { auto& iter = *iterP; + // MNN_PRINT("before resize, compute ref count tensor: %s, output0:%p\n", iter.info->name().c_str(), iter.outputs[0]); bool isRaster = iter.op->type() == OpType_Raster; for (auto t : iter.inputs) { auto des = TensorUtils::getDescribe(t); @@ -537,10 +591,11 @@ ErrorCode Pipeline::allocMemory(bool firstMalloc) { mBackend->onResizeBegin(); for (auto& info : mInfo) { auto& buffer = info.executeBuffer; - for (auto& iterP : buffer.command) { - auto& iter = *iterP; + for (auto iterP = buffer.command.begin(); iterP != buffer.command.end(); ++iterP) { + auto& iter = **iterP; // MNN_PRINT("before Resize: %d - %s\n", i, EnumNameOpType(iter.op->type())); // MNN_PRINT("before Resize: %s\n", iter.name.c_str()); + if (nullptr == iter.executionOrigin) { bool cached = false; /** Cache origin execution for fast resize*/ @@ -587,6 +642,7 @@ ErrorCode Pipeline::allocMemory(bool firstMalloc) { // Raster's inputs for (auto& r : des->regions) { auto allocRes = _allocTensor(r.origin, curBackend, mAllocInput, mOutputStatic); + // MNN_PRINT("alloc memory for input:%p, origin:%p, allocRes:%d\n", t, r.origin, allocRes); if (!allocRes) { return OUT_OF_MEMORY; } @@ -601,9 +657,14 @@ ErrorCode Pipeline::allocMemory(bool firstMalloc) { } // Check If need wrap bool isRaster = iter.op->type() == OpType_Raster; + // MNN_PRINT("isRaster:%d\n", isRaster); + bool skipExecution = true; + Tensor* reuseTensor = nullptr; + Tensor* replacedTensor = nullptr; for (int v=0; vregions.size()); if (isRaster) { // Raster's inputs for (auto& r : des->regions) { @@ -612,9 +673,16 @@ ErrorCode Pipeline::allocMemory(bool firstMalloc) { auto newTensor = WrapExecution::copyConstCache(origin, curBackend, mCacheConstTensors); if (nullptr != newTensor) { r.origin = newTensor; + skipExecution = false && skipExecution; + } else if ((reuseTensor = WrapExecution::getReuseTensor(origin, mBackupBackend.get(), curBackend))) { + r.origin = reuseTensor; + replacedTensor = t; } else { wrap = true; + skipExecution = false && skipExecution; } + } else { + skipExecution = false && skipExecution; } } } else { @@ -622,12 +690,32 @@ ErrorCode Pipeline::allocMemory(bool firstMalloc) { auto newTensor = WrapExecution::copyConstCache(t, curBackend, mCacheConstTensors); if (nullptr != newTensor) { iter.inputs[v] = newTensor; + skipExecution = false && skipExecution; + } else if ((reuseTensor = WrapExecution::getReuseTensor(t, mBackupBackend.get(), curBackend))) { + iter.inputs[v] = reuseTensor; + replacedTensor = t; + skipExecution = false && skipExecution; + wrap = false; } else { wrap = true; + skipExecution = false && skipExecution; } + } else { + skipExecution = false && skipExecution; } } } + + + if (skipExecution) { + // update following input of t with reuseTensor.op.output + _reorderOpCommandList(reuseTensor, replacedTensor, iterP, mInfo); + buffer.command.erase(iterP); + // release + iterP--; + continue; + } + { for (auto t : iter.outputs) { auto res = _allocTensor(t, curBackend, mAllocInput, mOutputStatic); @@ -642,7 +730,7 @@ ErrorCode Pipeline::allocMemory(bool firstMalloc) { } else { iter.execution = iter.executionOrigin; } - + // MNN_PRINT("before Resize 2, calling: %s \n", iter.info->name().c_str()); auto code = iter.execution->onResize(iter.inputs, iter.outputs); if (NO_ERROR != code && (!iter.info.get())) { MNN_ERROR("Resize error for type = %s, name = %s \n", iter.info->type().c_str(), iter.info->name().c_str()); @@ -679,6 +767,8 @@ ErrorCode Pipeline::execute() { auto& buffer = info.executeBuffer; for (auto& cmdP : buffer.command) { auto& cmd = *cmdP; + // MNN_PRINT("before run: %p \n", cmd.info.get()); + // MNN_PRINT("before run: %s \n", cmd.info->name().c_str()); auto code = cmd.execution->onExecute(cmd.inputs, cmd.outputs); if (NO_ERROR != code) { mBackend->onExecuteEnd(); diff --git a/source/core/Schedule.cpp b/source/core/Schedule.cpp index 76201dcb4..cc54f2e3a 100644 --- a/source/core/Schedule.cpp +++ b/source/core/Schedule.cpp @@ -112,6 +112,12 @@ static bool _setUpTensorInfo(std::vector>& tensors, cons static void generateScheduleGraph(vector& ops, const Net* net, const ScheduleConfig& configs, const vector>& allTensors) { + + // for (int i = 0; i < net->oplists()->size(); ++i) { + // auto op = net->oplists()->Get(i); + // MNN_PRINT("generateScheduleGraph, op type:%s, op name:%s\n", EnumNameOpType(op->type()), op->name()->c_str()); + // } + if (configs.path.inputs.empty() && configs.path.outputs.empty()) { // Use Default Linear schedule ops.clear(); @@ -129,7 +135,7 @@ static void generateScheduleGraph(vector& ops, const Net* net, const // 0: use, 1: no use std::vector opMask(net->oplists()->size()); ::memset(opMask.data(), 0, opMask.size() * sizeof(int)); - + // Set Initial Status std::set inputNames; std::set outputNames; diff --git a/source/core/Session.cpp b/source/core/Session.cpp index 434d23321..f24a0f68c 100644 --- a/source/core/Session.cpp +++ b/source/core/Session.cpp @@ -128,6 +128,16 @@ ErrorCode Session::run() const { MNN_ERROR("Can't run session because not resized\n"); return COMPUTE_SIZE_ERROR; } + +#ifdef LOG_VERBOSE + for (auto& iter : mInputs) { + auto& inputTensor = iter.second; + MNN_PRINT("before run, input name:%s, ptr:%p, shape:", iter.first.c_str(), inputTensor); + inputTensor->printShape(); + MNN_PRINT("\n"); + } +#endif + for (auto& iter : mPipelines) { auto error = iter->execute(); if (NO_ERROR != error) { @@ -163,6 +173,15 @@ void Session::_clearCache() { } ErrorCode Session::resize(bool isStatic) { + +#ifdef LOG_VERBOSE + for (auto& iter : mInputs) { + auto& inputTensor = iter.second; + MNN_PRINT("before resize, input name:%s, ptr:%p, hostPtr:%p, shape:", iter.first.c_str(), inputTensor, inputTensor->host()); + inputTensor->printShape(); + MNN_PRINT("\n"); + } +#endif bool firstMalloc = false; if (mNeedResize) { if (!isStatic) { @@ -196,6 +215,16 @@ ErrorCode Session::resize(bool isStatic) { mNeedMalloc = false; mNeedResize = false; } + +#ifdef LOG_VERBOSE + MNN_PRINT("session after resize\n"); + for (auto& iter : mOutputs) { + auto& outputTensor = iter.second; + MNN_PRINT("output name:%s, ptr:%p,shape:", iter.first.c_str(), outputTensor); + outputTensor->printShape(); + MNN_PRINT("\n"); + } +#endif return NO_ERROR; } bool Session::getInfo(Interpreter::SessionInfoCode code, void* ptr) const { diff --git a/source/core/Session.hpp b/source/core/Session.hpp index 7aff4593f..7bfee58ab 100644 --- a/source/core/Session.hpp +++ b/source/core/Session.hpp @@ -78,6 +78,10 @@ public: mNeedMalloc = flag; } + Runtime* getCPURuntime() { + return mRuntime.second.get(); + } + public: /** * @brief get backend that create the tensor. diff --git a/source/core/Tensor.cpp b/source/core/Tensor.cpp index f61a4cc5d..41250e1b8 100644 --- a/source/core/Tensor.cpp +++ b/source/core/Tensor.cpp @@ -123,6 +123,7 @@ Tensor::Tensor(bool deepCopy, const Tensor* tensor) { } Tensor::~Tensor() { + // MNN_PRINT("free tensor:%p\n", this); auto nativeDescribe = mDescribe->mContent.get(); if (nativeDescribe->memoryType == InsideDescribe::MEMORY_HOST) { if (nullptr != mBuffer.host) { @@ -160,6 +161,7 @@ Tensor* Tensor::clone(const Tensor* src, bool deepCopy) { return new Tensor(deepCopy, src); } + bool Tensor::copyFromHostTensor(const Tensor* hostTensor) { auto nativeDescribe = mDescribe->mContent.get(); auto bn = nativeDescribe->backend; @@ -409,13 +411,13 @@ void* Tensor::map(MapType mtype, DimensionType dtype) { if (nullptr == bn) { return nullptr; } - + auto mapPtr = bn->onMapTensor(mtype, dtype, this); if(mapPtr != nullptr) { // Get mapPtr in specific backend return mapPtr; } - + /* Common backend */ auto needSize = this->size(); void* hostPtr = malloc(needSize); @@ -424,7 +426,7 @@ void* Tensor::map(MapType mtype, DimensionType dtype) { //tmpTensor alloc MNN::Tensor tmpTensor(this, dtype, false); tmpTensor.buffer().host = (uint8_t *)hostPtr; - + //use onCopyBuffer bn->onCopyBuffer(this, &tmpTensor); } @@ -437,13 +439,13 @@ void Tensor::unmap(MapType mtype, DimensionType dtype, void *mapPtr) { if (nullptr == bn) { return; } - + bool ret = bn->onUnmapTensor(mtype, dtype, this, mapPtr); if(true == ret) { //do unmap already, just return return; } - + if(mtype == Tensor::MAP_TENSOR_WRITE) { //srcTensor alloc MNN::Tensor srcTensor(this, dtype, false); diff --git a/source/core/WrapExecution.cpp b/source/core/WrapExecution.cpp index 45754ba69..c739860b6 100644 --- a/source/core/WrapExecution.cpp +++ b/source/core/WrapExecution.cpp @@ -14,6 +14,8 @@ #include "backend/cpu/CPUCast.hpp" #include "backend/cpu/compute/CommonOptFunction.h" +// #define LOG_VERBOSE + namespace MNN { bool WrapExecution::needWrap(const Tensor* input, Backend* curBackend) { auto curType = curBackend ? curBackend->type() : MNN_FORWARD_CPU; @@ -87,10 +89,59 @@ Tensor* WrapExecution::copyConstCache(Tensor* t, Backend* curBackend, std::mapbackend; + auto srcBackendType = MNN_FORWARD_CPU; + auto usage = inputDes->usage; + + if (TensorUsage::CONSTANT != usage && TensorUsage::INPUT != usage) { + return nullptr; + } + + + if (nullptr != srcBackend) { + srcBackendType = srcBackend->type(); + } + MNN_ASSERT(inputDes->memoryType != Tensor::InsideDescribe::MEMORY_VIRTUAL); + // CPU -> CPU or XPU -> XPU + + if (srcBackendType == curBackend->type()) { + + return nullptr; // no need to copy or reuse + } + + auto& reuseCopyTensorMap = static_cast(cacheBackend)->getReuseCopyTensorMap(); + auto tensorAddr = t->host(); + auto tensorSize = t->size(); + + auto iter = reuseCopyTensorMap.find(std::make_pair(tensorAddr, tensorSize)); + + if (tensorAddr && iter != reuseCopyTensorMap.end() && std::get<2>(iter->second) != t) { +#ifdef LOG_VERBOSE + MNN_PRINT("getReuseTensor match cpu to gpu or gpu to cpu, input:%p, host:%p, size:%d, mapsize:%d, usage is input:%d, reused:%p, shape:", t, tensorAddr, tensorSize, reuseCopyTensorMap.size(), (TensorUsage::CONSTANT == usage || TensorUsage::INPUT == usage), std::get<2>(iter->second)); + t->printShape(); + MNN_PRINT("\n"); +#endif + return std::get<2>(iter->second); + } else { +#ifdef LOG_VERBOSE + MNN_PRINT("getReuseTensor cannot find reusable cpu to gpu or gpu to cpu, input:%p, host:%p, size:%d, mapsize:%d, usage:%d, shape:", t, tensorAddr, tensorSize, reuseCopyTensorMap.size(), (TensorUsage::CONSTANT == usage || TensorUsage::INPUT == usage)); + t->printShape(); + MNN_PRINT("\n"); +#endif + return nullptr; + } + +} + + +Tensor* WrapExecution::_getCopyTensor(Tensor* inputTensor, Tensor* outsideInput) { auto dstBackend = mExecution->backend(); auto inputDes = TensorUtils::getDescribe(inputTensor); auto srcBackend = inputDes->backend; + if (nullptr == srcBackend) { srcBackend = mCPUBackend; } @@ -100,18 +151,30 @@ Tensor* WrapExecution::_getCopyTensor(Tensor* inputTensor) { if (srcBackend->type() == dstBackend->type()) { return inputTensor; } + auto iter = mInputMaps.find(inputTensor); if (iter != mInputMaps.end()) { return std::get<2>(iter->second).get(); } + + auto& reuseCopyTensorMap = static_cast(mCPUBackend)->getReuseCopyTensorMap(); + auto tensorAddr = inputTensor->host(); + auto tensorSize = inputTensor->size(); + // CPU -> XPU if (srcBackend->type() == mCPUBackend->type()) { + std::shared_ptr wrapTensor(new Tensor); TensorUtils::copyShape(inputTensor, wrapTensor.get(), true); TensorUtils::adjustTensorForCompability(wrapTensor.get()); wrapTensor->buffer().type = inputTensor->buffer().type; TensorUtils::getDescribe(wrapTensor.get())->quantAttr = TensorUtils::getDescribe(inputTensor)->quantAttr; mInputMaps.insert(std::make_pair(inputTensor, std::make_tuple(dstBackend, dstBackend, wrapTensor))); +#ifdef LOG_VERBOSE + MNN_PRINT("match cpu to gpu, input:%p, host:%p, wrap:%p, host:%p. dst bn type:%d. outsideInput:%p, refcount:%d\n", inputTensor, inputTensor->host(), wrapTensor.get(), wrapTensor->host(), dstBackend->type(), outsideInput, TensorUtils::getDescribe(outsideInput)->useCount); +#endif + TensorUtils::getDescribe(outsideInput)->useCount++; + reuseCopyTensorMap.insert(std::make_pair(std::make_pair(tensorAddr, tensorSize), std::make_tuple(dstBackend, dstBackend, outsideInput))); return wrapTensor.get(); } // XPU -> CPU @@ -122,6 +185,11 @@ Tensor* WrapExecution::_getCopyTensor(Tensor* inputTensor) { TensorUtils::adjustTensorForCompability(wrapTensor.get()); TensorUtils::getDescribe(wrapTensor.get())->quantAttr = TensorUtils::getDescribe(inputTensor)->quantAttr; mInputMaps.insert(std::make_pair(inputTensor, std::make_tuple(mCPUBackend, srcBackend, wrapTensor))); + TensorUtils::getDescribe(outsideInput)->useCount++; +#ifdef LOG_VERBOSE + MNN_PRINT("match gpu to cpu, input:%p, host:%p, wrap:%p, host:%p. src bn type:%d, outsideInput:%p, refcount:%d\n", inputTensor, inputTensor->host(), wrapTensor.get(), wrapTensor->host(), srcBackend->type(), outsideInput, TensorUtils::getDescribe(outsideInput)->useCount); +#endif + reuseCopyTensorMap.insert(std::make_pair(std::make_pair(tensorAddr, tensorSize), std::make_tuple(mCPUBackend, srcBackend, outsideInput))); return wrapTensor.get(); } // XPU -> CPU -> XPU' @@ -137,6 +205,7 @@ Tensor* WrapExecution::_getCopyTensor(Tensor* inputTensor) { wrapTensor->buffer().type = inputTensor->buffer().type; mInputMaps.insert(std::make_pair(inputTensor, std::make_tuple(mCPUBackend, srcBackend, midTensor))); mInputMaps.insert(std::make_pair(midTensor.get(), std::make_tuple(dstBackend, dstBackend, wrapTensor))); + return wrapTensor.get(); } @@ -158,14 +227,15 @@ ErrorCode WrapExecution::onResize(const std::vector& inputs, const std: wrapDes->memoryType = Tensor::InsideDescribe::MEMORY_VIRTUAL; wrapDes->regions = des->regions; for (auto& r : wrapDes->regions) { - r.origin = _getCopyTensor(r.origin); + r.origin = _getCopyTensor(r.origin, inputTensor); } mWrapInputTensors[i] = mWrapForRaster.get(); } else { - mWrapInputTensors[i] = _getCopyTensor(inputTensor); + mWrapInputTensors[i] = _getCopyTensor(inputTensor, inputTensor); } } + for (int i = 0; i < outputs.size(); ++i) { MNN_ASSERT(TensorUtils::getDescribe(outputs[i])->backend == dstBackend); } @@ -177,7 +247,7 @@ ErrorCode WrapExecution::onResize(const std::vector& inputs, const std: auto src = iter.first; auto dst = std::get<2>(iter.second).get(); - if (TensorUtils::getDescribe(src)->usage == TensorUsage::CONSTANT && mStatic) { + if (TensorUtils::getDescribe(src)->usage == TensorUsage::CONSTANT && mStatic) { // copy constants auto srcDes = TensorUtils::getDescribe(src); memoryAllocSuccess = backend->onAcquireBuffer(dst, Backend::STATIC); if (memoryAllocSuccess) { @@ -206,6 +276,7 @@ ErrorCode WrapExecution::onResize(const std::vector& inputs, const std: backend->onReleaseBuffer(dst, Backend::DYNAMIC); } } + return result; } diff --git a/source/core/WrapExecution.hpp b/source/core/WrapExecution.hpp index d9b0bf98a..ed1426680 100644 --- a/source/core/WrapExecution.hpp +++ b/source/core/WrapExecution.hpp @@ -37,9 +37,9 @@ public: static bool needWrap(const Tensor* input, Backend* current); static Tensor* copyConstCache(Tensor* tensor, Backend* curBackend, std::map>& cache); - + static Tensor* getReuseTensor(Tensor* t, Backend* cacheBackend, Backend* curBackend); private: - Tensor *_getCopyTensor(Tensor *input); + Tensor *_getCopyTensor(Tensor *input, Tensor* outsideInput); Backend *mCPUBackend; std::shared_ptr mExecution; std::vector mWrapInputTensors; diff --git a/source/geometry/GeometryBinary.cpp b/source/geometry/GeometryBinary.cpp index 392494a55..bd3f0c995 100644 --- a/source/geometry/GeometryBinary.cpp +++ b/source/geometry/GeometryBinary.cpp @@ -123,7 +123,7 @@ public: input1Broadcast = true; } if (input0Broadcast || input1Broadcast) { - if ((context.forwardType() == MNN_FORWARD_CPU || context.forwardType() == MNN_FORWARD_CUDA || context.forwardType() == MNN_FORWARD_CPU_EXTENSION) && inp0format == outFormat && inp1format == outFormat && outFormat != MNN_DATA_FORMAT_NC4HW4 && input0->getType().code == halide_type_float) { + if ((context.forwardType() == MNN_FORWARD_CPU || context.forwardType() == MNN_FORWARD_CUDA || context.forwardType() == MNN_FORWARD_CPU_EXTENSION) && inp0format == outFormat && inp1format == outFormat && outFormat != MNN_DATA_FORMAT_NC4HW4 && input0->getType().code == halide_type_float && op->main_as_BinaryOp()->activationType() == 0) { if (!(input0Broadcast && input1Broadcast)) { // if (false) { // Use Loop instead of broadcast diff --git a/source/geometry/GeometryImageOp.cpp b/source/geometry/GeometryImageOp.cpp index 8f94dfe74..ebab40c47 100644 --- a/source/geometry/GeometryImageOp.cpp +++ b/source/geometry/GeometryImageOp.cpp @@ -33,130 +33,15 @@ namespace MNN { x_original = length_resized > 1 ? start_x * (length_original - 1) + x_resized * (end_x - start_x) * (length_original - 1) / (length_resized - 1) : 0.5 * (start_x + end_x) * (length_original - 1). */ struct InterpInfo { - float heightScale; - float widthScale; - float widthOffset = 0.0f; - float heightOffset = 0.0f; -}; -struct Interp3DInfo { float depthScale; float heightScale; float widthScale; float widthOffset = 0.0f; float heightOffset = 0.0f; float depthOffset = 0.0f; - }; -static void _ConverterInterp(const Interp* resize, InterpInfo* dstInfo, int inW, int inH, int outW, int outH, bool computeScale = true) { - switch (resize->ctm()) { - case CoordinateTransformationMode_NotSet: - { - // For compability, old model's nearest don't support halfpixels - if (resize->halfPixelCenters() && resize->resizeType() != 1) { - if (computeScale) { - dstInfo->heightScale = (float)(inH) / (float)(outH); - dstInfo->widthScale = (float)(inW) / (float)(outW); - } - dstInfo->widthOffset = 0.5f * dstInfo->widthScale - 0.5f; - dstInfo->heightOffset = 0.5f * dstInfo->heightScale - 0.5f; - } else if (resize->alignCorners()) { - if (computeScale) { - if (outH == 1) { - dstInfo->heightScale = 0.0f; - } else { - dstInfo->heightScale = (float)(inH - 1) / (float)(outH - 1); - } - if (outW == 1) { - dstInfo->widthScale = 0.0f; - } else { - dstInfo->widthScale = (float)(inW - 1) / (float)(outW - 1); - } - } - } else if (computeScale) { - dstInfo->heightScale = (float)(inH) / (float)(outH); - dstInfo->widthScale = (float)(inW) / (float)(outW); - } - break; - } - case CoordinateTransformationMode_AlignCorners: - { - if (computeScale) { - if (outH == 1) { - dstInfo->heightScale = 0.0f; - } else { - dstInfo->heightScale = (float)(inH - 1) / (float)(outH - 1); - } - if (outW == 1) { - dstInfo->widthScale = 0.0f; - } else { - dstInfo->widthScale = (float)(inW - 1) / (float)(outW - 1); - } - } - break; - } - case CoordinateTransformationMode_HalfPixels: - { - if (computeScale) { - dstInfo->heightScale = (float)(inH) / (float)(outH); - dstInfo->widthScale = (float)(inW) / (float)(outW); - } - dstInfo->widthOffset = 0.5f * dstInfo->widthScale - 0.5f; - dstInfo->heightOffset = 0.5f * dstInfo->heightScale - 0.5f; - break; - } - case CoordinateTransformationMode_PytorchHalfPixels: - { - if (outH > 1) { - if (computeScale) { - dstInfo->heightScale = (float)inH / (float)outH; - } - dstInfo->heightOffset = 0.5f * dstInfo->heightScale - 0.5f; - } else { - if (computeScale) { - dstInfo->heightScale = 0.0f; - } - } - if (outW > 1) { - if (computeScale) { - dstInfo->widthScale = (float)inW / (float)outW; - } - dstInfo->widthOffset = 0.5f * dstInfo->widthScale - 0.5f; - } else { - if (computeScale) { - dstInfo->widthScale = 0.0f; - } - } - break; - } - case CoordinateTransformationMode_Asymmetric: - { - if (computeScale) { - dstInfo->heightScale = (float)(inH) / (float)(outH); - dstInfo->widthScale = (float)(inW) / (float)(outW); - } - break; - } - case CoordinateTransformationMode_TensorflowHalfPixels: - { - if (computeScale) { - dstInfo->heightScale = (float)(inH) / (float)(outH); - dstInfo->widthScale = (float)(inW) / (float)(outW); - } - dstInfo->widthOffset = 0.5f * dstInfo->widthScale; - dstInfo->heightOffset = 0.5f * dstInfo->heightScale; - break; - } - case CoordinateTransformationMode_TensorflowCropAndResize: - { - //FIXME: Not support now - MNN_ERROR("Don't support CoordinateTransformationMode_TensorflowCropAndResize currently\n"); - break; - } - default: - break; - } -} -static void _ConverterInterp3D(const Interp* resize, Interp3DInfo* dstInfo, int inW, int inH, int inD, int outW, int outH, int outD, bool computeScale = true) { + +static void _ConverterInterp(const Interp* resize, InterpInfo* dstInfo, int inW, int inH, int inD, int outW, int outH, int outD, bool computeScale = true) { switch (resize->ctm()) { case CoordinateTransformationMode_NotSet: { @@ -197,22 +82,20 @@ static void _ConverterInterp3D(const Interp* resize, Interp3DInfo* dstInfo, int } case CoordinateTransformationMode_AlignCorners: { - if (computeScale) { - if (outD == 1) { - dstInfo->depthScale = 0.0f; - } else { - dstInfo->depthScale = (float)(inD - 1) / (float)(outD - 1); - } - if (outH == 1) { - dstInfo->heightScale = 0.0f; - } else { - dstInfo->heightScale = (float)(inH - 1) / (float)(outH - 1); - } - if (outW == 1) { - dstInfo->widthScale = 0.0f; - } else { - dstInfo->widthScale = (float)(inW - 1) / (float)(outW - 1); - } + if (outD == 1) { + dstInfo->depthScale = 0.0f; + } else { + dstInfo->depthScale = (float)(inD - 1) / (float)(outD - 1); + } + if (outH == 1) { + dstInfo->heightScale = 0.0f; + } else { + dstInfo->heightScale = (float)(inH - 1) / (float)(outH - 1); + } + if (outW == 1) { + dstInfo->widthScale = 0.0f; + } else { + dstInfo->widthScale = (float)(inW - 1) / (float)(outW - 1); } break; } @@ -293,29 +176,8 @@ static void _ConverterInterp3D(const Interp* resize, Interp3DInfo* dstInfo, int break; } } -static flatbuffers::Offset makeInterp(flatbuffers::FlatBufferBuilder& builder, const InterpInfo* info, int resizeType, const Op* op) { - flatbuffers::Offset temp; - if (nullptr != op->name()) { - temp = builder.CreateString(op->name()->str()); - } - InterpBuilder intpB(builder); - intpB.add_resizeType(resizeType); - intpB.add_widthScale(info->widthScale); - intpB.add_heightScale(info->heightScale); - intpB.add_heightOffset(info->heightOffset); - intpB.add_widthOffset(info->widthOffset); - auto offsetInterp = intpB.Finish().Union(); - OpBuilder opB(builder); - opB.add_type(OpType_Interp); - opB.add_main(offsetInterp); - opB.add_main_type(OpParameter_Interp); - if (nullptr != op->name()) { - opB.add_name(temp); - } - return opB.Finish(); -} -static flatbuffers::Offset makeInterp3D(flatbuffers::FlatBufferBuilder& builder, const Interp3DInfo* info, int resizeType, const Op* op) { +static flatbuffers::Offset makeInterp(flatbuffers::FlatBufferBuilder& builder, const InterpInfo* info, int resizeType, const Op* op, OpType type) { flatbuffers::Offset temp; if (nullptr != op->name()) { temp = builder.CreateString(op->name()->str()); @@ -330,7 +192,7 @@ static flatbuffers::Offset makeInterp3D(flatbuffers::FlatBufferBuilder& buil intp3DB.add_depthOffset(info->depthOffset); auto offsetInterp3D = intp3DB.Finish().Union(); OpBuilder opB(builder); - opB.add_type(OpType_Interp3D); + opB.add_type(type); opB.add_main(offsetInterp3D); opB.add_main_type(OpParameter_Interp); if (nullptr != op->name()) { @@ -365,10 +227,10 @@ public: info.widthScale = (float)inputs[0]->width() / (float)outputs[0]->width(); info.heightScale = (float)inputs[0]->height() / (float)outputs[0]->height(); flatbuffers::FlatBufferBuilder builder; - builder.Finish(makeInterp(builder, &info, 2, op)); + builder.Finish(makeInterp(builder, &info, 2, op, OpType_Interp)); res.command.emplace_back(GeometryComputerUtils::makeCommand(builder, {newInputs[0]}, newOutputs)); } - else if (OpType_Interp == op->type()) { + else if (OpType_Interp == op->type() && inputs[0]->dimensions() <= 4) { // Compute cord transform for interp auto resize = op->main_as_Interp(); auto inW = inputs[0]->width(); @@ -384,36 +246,33 @@ public: info.widthScale = 1.0f / inputs[1]->host()[3]; } } - _ConverterInterp(resize, &info, inW, inH, outW, outH, computeScale); + const int defaultDepth = 10; + _ConverterInterp(resize, &info, inW, inH, defaultDepth, outW, outH, defaultDepth, computeScale); flatbuffers::FlatBufferBuilder builder; - builder.Finish(makeInterp(builder, &info, resize->resizeType(), op)); + builder.Finish(makeInterp(builder, &info, resize->resizeType(), op, OpType_Interp)); res.command.emplace_back(GeometryComputerUtils::makeCommand(builder, {newInputs[0]}, newOutputs)); - } else if (OpType_Interp3D == op->type()) { + } else if (inputs[0]->dimensions() == 5) { // Compute cord transform for interp auto resize = op->main_as_Interp(); - auto inShape = inputs[0]->shape(); - auto outShape = outputs[0]->shape(); + auto inShape = newInputs[0]->shape(); + auto outShape = newOutputs[0]->shape(); auto inW = inShape[4]; auto inH = inShape[3]; auto inD = inShape[2]; auto outW = outShape[4]; auto outH = outShape[3]; auto outD = outShape[2]; - Interp3DInfo info; + InterpInfo info; bool computeScale = true; if (inputs.size() > 1 && inputs[1]->getType().code == halide_type_float) { computeScale = false; info.depthScale = 1.0f / inputs[1]->host()[2]; - if (inputs[0]->dimensions() >= 4) { - info.heightScale = 1.0f / inputs[1]->host()[3]; - } - if (inputs[0]->dimensions() >= 5) { - info.widthScale = 1.0f / inputs[1]->host()[4]; - } + info.heightScale = 1.0f / inputs[1]->host()[3]; + info.widthScale = 1.0f / inputs[1]->host()[4]; } - _ConverterInterp3D(resize, &info, inW, inH, inD, outW, outH, outD, computeScale); + _ConverterInterp(resize, &info, inW, inH, inD, outW, outH, outD, computeScale); flatbuffers::FlatBufferBuilder builder; - builder.Finish(makeInterp3D(builder, &info, resize->resizeType(), op)); + builder.Finish(makeInterp(builder, &info, resize->resizeType(), op, OpType_Interp3D)); res.command.emplace_back(GeometryComputerUtils::makeCommand(builder, {newInputs[0]}, newOutputs)); } else { SharedPtr cmdP = new Command; diff --git a/source/shape/ShapeConvTranspose3D.cpp b/source/shape/ShapeConvTranspose3D.cpp index 549fea394..12e2bc657 100644 --- a/source/shape/ShapeConvTranspose3D.cpp +++ b/source/shape/ShapeConvTranspose3D.cpp @@ -10,7 +10,6 @@ #include "shape/SizeComputer.hpp" #include "core/Macro.h" #include "core/TensorUtils.hpp" -#include namespace MNN { class ConvTranspose3DSizeComputer : public SizeComputer { public: diff --git a/source/shape/ShapeInterp.cpp b/source/shape/ShapeInterp.cpp index 13c3708bf..c824740f5 100644 --- a/source/shape/ShapeInterp.cpp +++ b/source/shape/ShapeInterp.cpp @@ -56,6 +56,7 @@ class InterpComputer : public SizeComputer { } } if (1 == inputSize) { + // For old mnn model from onnx auto interp = op->main_as_Interp(); // get output dims w = interp->outputWidth(); @@ -65,6 +66,7 @@ class InterpComputer : public SizeComputer { h = ih * interp->heightScale(); } } else { + // For mnn model from tensorflow auto shape = inputs[1]; // input shape(shape) // Tensorflow's interp: h, w if(2 != shape->buffer().dim[0].extent) { @@ -98,15 +100,18 @@ class InterpComputer : public SizeComputer { auto elementInM = (float)outputs[0]->elementSize() / 1024.0f / 1024.0f; auto interp = op->main_as_Interp(); auto unit = 0; + int dimensions = inputs[0]->dimensions(); + int interpDims = dimensions - 2; switch (interp->resizeType()) { case 1: + case 4: unit = 1; break; case 2: - unit = 4; + unit = (1 << interpDims); break; case 3: - unit = 16; + unit = (4 << interpDims); break; default: break; diff --git a/source/shape/ShapeInterp3D.cpp b/source/shape/ShapeInterp3D.cpp deleted file mode 100644 index 339ebffdf..000000000 --- a/source/shape/ShapeInterp3D.cpp +++ /dev/null @@ -1,129 +0,0 @@ -// -// ShapeInterp.cpp -// MNN -// -// Created by MNN on 2019/01/10. -// Copyright © 2018, Alibaba Group Holding Limited -// - -#include "shape/SizeComputer.hpp" -#include "core/Macro.h" - -namespace MNN { - -// Size Computer -class Interp3DComputer : public SizeComputer { - virtual bool onComputeSize(const MNN::Op* op, const std::vector& inputs, - const std::vector& outputs) const override { - MNN_ASSERT(1 == inputs.size() || 2 == inputs.size()); - MNN_ASSERT(1 == outputs.size()); - - auto& input = inputs[0]->buffer(); // input tensor(data) - auto& output = outputs[0]->buffer(); - int w = 0; - int h = 0; - int d = 0; - const int inputSize = (int)inputs.size(); - auto shape = inputs[0]->shape(); - auto iw = shape[4]; - auto ih = shape[3]; - auto id = shape[2]; - // copy dims - memcpy(output.dim, input.dim, sizeof(halide_dimension_t) * input.dimensions); - outputs[0]->buffer().dimensions = inputs[0]->dimensions(); - outputs[0]->buffer().type = inputs[0]->getType(); - auto format = TensorUtils::getDescribe(inputs[0])->dimensionFormat; - TensorUtils::getDescribe(outputs[0])->dimensionFormat = format; - if (2 == inputSize) { - auto shape = inputs[1]; // input shape(shape) - if(shape->length(0) == input.dimensions) { - // For Onnx's Resize - // Don't support batch / channel resize - for (int i=0; i<2; ++i) { - output.dim[i].extent = input.dim[i].extent; - } - if (shape->getType().code == halide_type_int) { - // Width / Height - auto shapePtr = shape->host(); - for (int i=2; ihost(); - for (int i=2; imain_as_Interp(); - // get output dims - w = interp3D->outputWidth(); - h = interp3D->outputHeight(); - d = interp3D->outputDepth(); - if (w == 0 || h == 0) { - w = iw * interp3D->widthScale(); - h = ih * interp3D->heightScale(); - d = id * interp3D->depthScale(); - } - } else { - auto shape = inputs[1]; // input shape(shape) - // Tensorflow's interp: d, h, w - if(3 != shape->buffer().dim[0].extent) { - MNN_ERROR("Tensorflow's interp's shape should be length two\n"); - return false; - } - if (shape->getType().code == halide_type_float) { - const float *shapeData = shape->host(); - w = shapeData[2]; - h = shapeData[1]; - d = shapeData[0]; - } else { - const int32_t *shapeData = shape->host(); - w = shapeData[2]; - h = shapeData[1]; - d = shapeData[0]; - } - } - if (0 == w && 0 == h) { - return false; - } - MNN_ASSERT(MNN_DATA_FORMAT_NHWC != format) - if (MNN_DATA_FORMAT_NHWC == format) { - //output.dim[2].extent = w; - //output.dim[1].extent = h; - MNN_ERROR("NHWC input format is not supported in Interp3D currently."); - } else { - output.dim[4].extent = w; - output.dim[3].extent = h; - output.dim[2].extent = d; - } - return true; - } - virtual float onComputeFlops(const MNN::Op* op, const std::vector& inputs, - const std::vector& outputs) const override { - auto elementInM = (float)outputs[0]->elementSize() / 1024.0f / 1024.0f; - auto interp3D = op->main_as_Interp(); - auto unit = 0; - switch (interp3D->resizeType()) { - case 1: - unit = 1; - break; - case 2: - unit = 4; - break; - case 3: - unit = 16; - break; - default: - break; - } - return unit * elementInM; - } -}; - -REGISTER_SHAPE_INPUTS(Interp3DComputer, OpType_Interp3D, {1}); -} // namespace MNN diff --git a/source/shape/ShapeReduction.cpp b/source/shape/ShapeReduction.cpp index f9046ae1f..680e36b1f 100644 --- a/source/shape/ShapeReduction.cpp +++ b/source/shape/ShapeReduction.cpp @@ -32,40 +32,37 @@ public: output->buffer().dimensions = 0; return true; } - std::set reduceDimSet; + uint8_t reduceMask[MNN_MAX_TENSOR_DIM]; + ::memset(reduceMask, 0, sizeof(uint8_t) * MNN_MAX_TENSOR_DIM); if (nullptr != reduce->dim()) { for (int i = 0; i < reduce->dim()->size(); ++i) { - reduceDimSet.insert(_getRealAxis(reduce->dim()->data()[i], inputs[0]->dimensions())); + reduceMask[_getRealAxis(reduce->dim()->data()[i], inputs[0]->dimensions())] = 1; } } else { auto input1 = inputs[1]; auto size = input1->elementSize(); auto dims = input1->host(); for (int i = 0; i < size; ++i) { - reduceDimSet.insert(_getRealAxis(dims[i], inputs[0]->dimensions())); + reduceMask[_getRealAxis(dims[i], inputs[0]->dimensions())] = 1; } } auto input = inputs[0]; const int inputDimensions = input->dimensions(); - if (reduceDimSet.find(-1) != reduceDimSet.end()) { - // dim set have -1 which mean applying reduction on last dimension - reduceDimSet.erase(-1); - reduceDimSet.insert(inputDimensions - 1); - } - std::vector newDims; + int offset = 0; for (int i = 0; i < inputDimensions; ++i) { - if (reduceDimSet.find(i) == reduceDimSet.end()) { - newDims.push_back(input->length(i)); - } else if (reduce->keepDims()) { - newDims.push_back(1); + if (1 == reduceMask[i]) { + if (reduce->keepDims()) { + output->buffer().dim[offset].extent = 1; + offset++; + } + continue; } + output->buffer().dim[offset].extent = input->length(i); + offset++; } - output->buffer().dimensions = (int)newDims.size(); - for (int i = 0; i < newDims.size(); ++i) { - output->buffer().dim[i].extent = newDims[i]; - } + output->buffer().dimensions = offset; TensorUtils::getDescribe(outputs[0])->dimensionFormat = TensorUtils::getDescribe(inputs[0])->dimensionFormat; return true; diff --git a/source/shape/ShapeRegister.cpp b/source/shape/ShapeRegister.cpp index 6a6d6a3a0..d9c0fb306 100644 --- a/source/shape/ShapeRegister.cpp +++ b/source/shape/ShapeRegister.cpp @@ -60,6 +60,7 @@ extern void ___ExpandDimsComputer__OpType_ExpandDims__(); extern void ___ShapeOneHot__OpType_OneHot__(); extern void ___ROIPoolingComputer__OpType_ROIPooling__(); extern void ___PaddingComputer__OpType_Padding__(); +extern void ___ConvTranspose3DSizeComputer__OpType_ConvTranspose3D__(); extern void ___SpaceToDepthSizeComputer__OpType_SpaceToDepth__(); extern void ___UnravelIndexSize__OpType_UnravelIndex__(); extern void ___ShapeDequantize__OpType_Dequantize__(); @@ -107,8 +108,6 @@ extern void ___SpaceToBatchNDSizeComputer__OpType_SpaceToBatchND__(); extern void ___PackComputer__OpType_Pack__(); extern void ___DeconvolutionSizeComputer__OpType_Deconvolution__(); extern void ___DeconvolutionSizeComputer__OpType_DeconvolutionDepthwise__(); -extern void ___ConvTranspose3DSizeComputer__OpType_ConvTranspose3D__(); -extern void ___Interp3DComputer__OpType_Interp3D__(); void registerShapeOps() { ___ShapeSizeComputer__OpType_Shape__(); @@ -171,6 +170,7 @@ ___ExpandDimsComputer__OpType_ExpandDims__(); ___ShapeOneHot__OpType_OneHot__(); ___ROIPoolingComputer__OpType_ROIPooling__(); ___PaddingComputer__OpType_Padding__(); +___ConvTranspose3DSizeComputer__OpType_ConvTranspose3D__(); ___SpaceToDepthSizeComputer__OpType_SpaceToDepth__(); ___UnravelIndexSize__OpType_UnravelIndex__(); ___ShapeDequantize__OpType_Dequantize__(); @@ -218,7 +218,5 @@ ___SpaceToBatchNDSizeComputer__OpType_SpaceToBatchND__(); ___PackComputer__OpType_Pack__(); ___DeconvolutionSizeComputer__OpType_Deconvolution__(); ___DeconvolutionSizeComputer__OpType_DeconvolutionDepthwise__(); -___ConvTranspose3DSizeComputer__OpType_ConvTranspose3D__(); -___Interp3DComputer__OpType_Interp3D__(); } } diff --git a/source/shape/SizeComputer.cpp b/source/shape/SizeComputer.cpp index 9fbb30c7a..b8ebe0d18 100644 --- a/source/shape/SizeComputer.cpp +++ b/source/shape/SizeComputer.cpp @@ -99,6 +99,7 @@ bool SizeComputer::computeOutputSize(const MNN::Op* op, const std::vectoronComputeSize(op, inputs, outputs); #ifdef MNN_DEBUG_TENSOR_SIZE + if (op->name() != nullptr) { MNN_PRINT("===> compute shape: %s, [%s]\n", op->name()->c_str(), MNN::EnumNameOpType(op->type())); } else { @@ -107,7 +108,7 @@ bool SizeComputer::computeOutputSize(const MNN::Op* op, const std::vectordimensionFormat), o->getType().code); + MNN_PRINT("\tptr=%p, format=%s, datatype=%d;\t", o, EnumNameMNN_DATA_FORMAT(TensorUtils::getDescribe(o)->dimensionFormat), o->getType().code); if (o->dimensions() == 0) { MNN_PRINT("\t*Scalar*"); } @@ -119,7 +120,7 @@ bool SizeComputer::computeOutputSize(const MNN::Op* op, const std::vectordimensionFormat), o->getType().code); + MNN_PRINT("\tptr=:%p, format=%s, datatype=%d;\t",o, EnumNameMNN_DATA_FORMAT(TensorUtils::getDescribe(o)->dimensionFormat), o->getType().code); if (o->dimensions() == 0) { MNN_PRINT("\t*Scalar*"); } @@ -128,6 +129,8 @@ bool SizeComputer::computeOutputSize(const MNN::Op* op, const std::vector>& tensors, const Net* net) if (tensors[i].get() == nullptr) { tensors[i].reset(new Tensor); TensorUtils::getDescribe(tensors[i].get())->index = i; + // MNN_PRINT("initTensors create tensor:%p, index:%d, backend:%d\n", tensors[i].get(), i, TensorUtils::getDescribe(tensors[i].get())->backend); } } if (describes) { @@ -136,18 +137,20 @@ bool initTensors(std::vector>& tensors, const Net* net) tb.dim[i].extent = extent; } tb.dimensions = idims->size(); - TensorUtils::setLinearLayout(tensor); } else { tb.dimensions = 0; } tensor->setType(inputParam->dtype()); TensorUtils::getDescribe(tensor)->dimensionFormat = inputParam->dformat(); + TensorUtils::setLinearLayout(tensor); } } return valid; } void initPipelineInfosFromOps(std::vector& infos, std::vector& ops, const std::vector>& allTensors) { for (const Op* op : ops) { + // MNN_PRINT("initPipelineInfosFromOps, op type:%s, op name:%s\n", EnumNameOpType(op->type()), op->name()->c_str()); + Schedule::PipelineInfo opInfo; opInfo.op = op; if (nullptr != op->outputIndexes()) { diff --git a/test.sh b/test.sh index 3dbb7a83d..7ba36646f 100755 --- a/test.sh +++ b/test.sh @@ -38,7 +38,7 @@ USER_HOME="$(echo -n $(bash -c "cd ~${USER_NAME} && pwd"))" # detect change SOURCE_CHANGE=$(git show --name-only | grep -E "^source/(internal|backend|core|common|cv|geometry|math|plugin|shape|utils)/.*\.(cpp|cc|c|hpp)$" | \ - grep -Ev "aliyun-log-c-sdk|hiai|tensorrt") + grep -Ev "aliyun-log-c-sdk|hiai|tensorrt|BackendRegister|FunctionDispatcher") PYMNN_CHANGE=$(git show --name-only | grep -E "^pymnn/.*\.(cpp|cc|c|h|hpp|py)$") PY_CHANGE=$(git show --name-only | grep -E "^pymnn/pip_package/MNN/.*\.(py)$") OPENCV_CHANGE=$(git show --name-only | grep -E "^tools/cv/.*\.(cpp|cc|c|h|hpp)$") diff --git a/test/op/ArgMaxTest.cpp b/test/op/ArgMaxTest.cpp index 2799ce215..b4a17bb09 100644 --- a/test/op/ArgMaxTest.cpp +++ b/test/op/ArgMaxTest.cpp @@ -28,6 +28,7 @@ public: op->main.AsArgMax()->softmaxThreshold = 0; return (Variable::create(Expr::create(std::move(op), {input}))); }; + // auto input_nhwc = _Input({128 * 1600, 64}, NHWC); auto input_nhwc = _Input({4, 4}, NHWC); auto input_nchw = _Input({4, 4}, NC4HW4); input_nhwc->setName("input_tensor_nhwc"); @@ -38,6 +39,7 @@ public: -9.0, -10.0, 11.0, 12.0, 13.0, 14.0, -15.0, -16.0}; auto inputPtr = input_nhwc->writeMap(); + memset(inputPtr, 0, input_nhwc->getInfo()->size * sizeof(float)); memcpy(inputPtr, inpudata, 16 * sizeof(float)); inputPtr = input_nchw->writeMap(); memcpy(inputPtr, inpudata, 16 * sizeof(float)); @@ -79,6 +81,7 @@ public: virtual ~ArgMinTest() = default; virtual bool run(int precision) { auto input = _Input({4, 4}, NHWC); + // auto input = _Input({128 * 160, 4}, NHWC); input->setName("input_tensor"); // set input data const float inpudata[] = {-1.0, 2.0, -3.0, 4.0, 5.0, -6.0, 7.0, -8.0, diff --git a/test/op/ConcatTest.cpp b/test/op/ConcatTest.cpp index cd6673142..ae23f945d 100644 --- a/test/op/ConcatTest.cpp +++ b/test/op/ConcatTest.cpp @@ -67,7 +67,6 @@ public: auto input2 = _Input({2, 0}, NCHW); input2->setName("input2"); // set input data - const float input2_data[] = {}; auto input2Ptr = input2->writeMap(); input2->unMap(); auto output = _Concat({input1, input2}, 1); diff --git a/tools/converter/source/optimizer/PostConverter.cpp b/tools/converter/source/optimizer/PostConverter.cpp index 4c5e97960..b8aa997f2 100644 --- a/tools/converter/source/optimizer/PostConverter.cpp +++ b/tools/converter/source/optimizer/PostConverter.cpp @@ -260,6 +260,9 @@ std::unique_ptr optimizeNetImpl(std::unique_ptr& originNet // Merge Relu6 Convolution "MergeRelu6ToConvolution", + // Merge Relu BinaryOp + "MergeReluToBinaryOp", + }; if (ctx->is_training) { std::vector::iterator iter = afterProgramConvert.begin(); diff --git a/tools/converter/source/optimizer/onnxextra/OnnxUpsample.cpp b/tools/converter/source/optimizer/onnxextra/OnnxUpsample.cpp index 7aa968b93..6b999c872 100644 --- a/tools/converter/source/optimizer/onnxextra/OnnxUpsample.cpp +++ b/tools/converter/source/optimizer/onnxextra/OnnxUpsample.cpp @@ -98,172 +98,6 @@ public: } }; -static int resizeInputDim(EXPRP expr) { - auto inputs = expr->inputs(); - auto x = inputs[0]; - auto dimSize = x->getInfo()->dim.size(); - return dimSize; -} - -static EXPRP _transformResize3D(EXPRP expr) { - auto inputs = expr->inputs(); - std::string resizeMode = ""; - std::string coordMode = "half_pixel"; // detect align_corner attribute - std::string nearestMode = "round_prefer_floor"; - auto op = expr->get(); - auto extraParam = op->main_as_Extra(); - const int attrSize = extraParam->attr()->size(); - float cubicFactor = -0.75f; - for (int i = 0; i < attrSize; ++i) { - auto attr = extraParam->attr()->GetAs(i); - const auto& key = attr->key()->str(); - if (key == "mode") { - resizeMode = attr->s()->str(); - } else if (key == "coordinate_transformation_mode") { - coordMode = attr->s()->str(); - } else if (key == "nearest_mode") { - nearestMode = attr->s()->str(); - } else if (key == "cubic_coeff_a") { - cubicFactor = attr->f(); - } - } - - std::unique_ptr mergeredResize3D(new OpT); - mergeredResize3D->type = OpType_Interp3D; - mergeredResize3D->main.type = OpParameter_Interp; - - std::unique_ptr resize3DParam(new InterpT); - // 1:near 2: bilinear 3: cubic - if (resizeMode == "nearest") { - if (nearestMode == "round_prefer_floor") { - resize3DParam->resizeType = 4; - } else if (nearestMode == "floor") { - resize3DParam->resizeType = 1; - } else { - MNN_ERROR("Don't support %s neareset mode, use round_prefer_floor instead\n", nearestMode.c_str()); - resize3DParam->resizeType = 4; - } - // TODO: trilinear and cubic interpolation -// } else if (resizeMode == "trilinear" || resizeMode == "linear") { -// resize3DParam->resizeType = 2; -// } else if (resizeMode == "cubic") { -// resize3DParam->resizeType = 3; -// resize3DParam->cubicCoeffA = cubicFactor; - } else { - MNN_ERROR("Unsupported Resize mode! ==> %s, use nearest instead\n", resizeMode.c_str()); - resize3DParam->resizeType = 1; - } - // For compability of old mnn - resize3DParam->alignCorners = (coordMode == "align_corners"); - resize3DParam->halfPixelCenters = (coordMode == "half_pixel"); - - /* - coordinate_transformation_mode: string - This attribute describes how to transform the coordinate in the resized tensor to the coordinate in the original - tensor. - - The coordinate of each dimension is transformed individually. Let's describe a case using axis x as an example. - Denote x_resized as the coordinate of axis x in the resized tensor, x_original as the coordinate of axis x in - the original tensor, length_original as the length of the original tensor in axis x, length_resized as the - length of the resized tensor in axis x, roi_x = (start_x, end_x) of the axis x in input "roi", scale = - length_resized / length_original, - - if coordinate_transformation_mode is "half_pixel", - x_original = (x_resized + 0.5) / scale - 0.5, - - if coordinate_transformation_mode is "pytorch_half_pixel", - x_original = length_resized > 1 ? (x_resized + 0.5) / scale - 0.5 : 0, - - if coordinate_transformation_mode is "align_corners", - x_original = x_resized * (length_original - 1) / (length_resized - 1), - - if coordinate_transformation_mode is "asymmetric", - x_original = x_resized / scale, - - if coordinate_transformation_mode is "tf_half_pixel_for_nn", - x_original = (x_resized + 0.5) / scale, - - if coordinate_transformation_mode is "tf_crop_and_resize", - x_original = length_resized > 1 ? start_x * (length_original - 1) + x_resized * (end_x - start_x) * - (length_original - 1) / (length_resized - 1) : 0.5 * (start_x + end_x) * (length_original - 1). - */ -#define SET_MODE(str, c) \ - if (coordMode == str) \ - resize3DParam->ctm = MNN::CoordinateTransformationMode_##c - SET_MODE("align_corners", AlignCorners); - SET_MODE("half_pixel", HalfPixels); - SET_MODE("pytorch_half_pixel", PytorchHalfPixels); - SET_MODE("tf_half_pixel_for_nn", TensorflowHalfPixels); - SET_MODE("tf_crop_and_resize", TensorflowCropAndResize); - SET_MODE("asymmetric", Asymmetric); -#undef SET_MODE - - VARP output; - if (inputs.size() == 2) { - auto info = inputs[1]->getInfo(); - auto ptr = inputs[1]->readMap(); - if (!ptr) { - mergeredResize3D->main.value = resize3DParam.release(); - auto output = Variable::create(Expr::create(mergeredResize3D.get(), {inputs[0], inputs[1]})); - return output->expr().first; - } - MNN_ASSERT((ptr[0] == 1) && (ptr[1] == 1)); - if (info->size > 2) { - resize3DParam->depthScale = ptr[2]; - } - if (info->size > 3) { - resize3DParam->heightScale = ptr[3]; - } - if (info->size > 4) { - resize3DParam->widthScale = ptr[4]; - } - mergeredResize3D->main.value = resize3DParam.release(); - auto resizeExpr = Expr::create(mergeredResize3D.get(), {inputs[0]}); - resizeExpr->setName(expr->name()); - output = Variable::create(resizeExpr); - return output->expr().first; - } - if (inputs.size() == 3) { - auto scaleT = inputs[2]; - auto info = inputs[2]->getInfo(); - auto scale = scaleT->readMap(); - if (nullptr == scale) { - // Compute shape dynamic - mergeredResize3D->main.value = resize3DParam.release(); - auto resizeExpr = Expr::create(mergeredResize3D.get(), {inputs[0], {inputs[2]}}); - resizeExpr->setName(expr->name()); - output = Variable::create(resizeExpr); - return output->expr().first; - } - MNN_THROW_CHECK(nullptr != scale, "Onnx resize's scale must be const"); - if (info->size > 2) { - resize3DParam->depthScale = scale[2]; - } - if (info->size > 3) { - resize3DParam->heightScale = scale[3]; - } - if (info->size > 4) { - resize3DParam->widthScale = scale[4]; - } - mergeredResize3D->main.value = resize3DParam.release(); - auto resizeExpr = Expr::create(mergeredResize3D.get(), {inputs[0]}); - resizeExpr->setName(expr->name()); - output = Variable::create(resizeExpr); - return output->expr().first; - } - if (inputs.size() == 4) { - auto sizes = inputs[3]; - auto name = sizes->name(); - - mergeredResize3D->main.value = resize3DParam.release(); - auto resizeExpr = Expr::create(mergeredResize3D.get(), {inputs[0], inputs[3]}); - resizeExpr->setName(expr->name()); - output = Variable::create(resizeExpr); - return output->expr().first; - } - return output->expr().first; -} - class OnnxReiszeTransform : public OnnxExtraManager::Transform { public: virtual EXPRP onExecute(EXPRP expr) const override { @@ -271,9 +105,6 @@ public: // input, roi, scales, sizes // for more information, please reference from https://github.com/onnx/onnx/blob/master/docs/Operators.md#Resize MNN_THROW_CHECK((inputs.size() >= 2), "Onnx Resize should have 2/3/4 inputs!"); - if (resizeInputDim(expr) == 5) { - return _transformResize3D(expr); - } std::string resizeMode = ""; std::string coordMode = "half_pixel"; // detect align_corner attribute std::string nearestMode = "round_prefer_floor"; @@ -366,47 +197,16 @@ public: VARP output; if (inputs.size() == 2) { - auto info = inputs[1]->getInfo(); - auto ptr = inputs[1]->readMap(); - if (!ptr) { - mergeredResize->main.value = resizeParam.release(); - auto output = Variable::create(Expr::create(mergeredResize.get(), {inputs[0], inputs[1]})); - return output->expr().first; - } - MNN_ASSERT((ptr[0] == 1) && (ptr[1] == 1)); - if (info->size > 2) { - resizeParam->heightScale = ptr[2]; - } - if (info->size > 3) { - resizeParam->widthScale = ptr[3]; - } mergeredResize->main.value = resizeParam.release(); - auto resizeExpr = Expr::create(mergeredResize.get(), {inputs[0]}); - resizeExpr->setName(expr->name()); - output = Variable::create(resizeExpr); + auto output = Variable::create(Expr::create(mergeredResize.get(), {inputs[0], inputs[1]})); + output->setName(expr->name()); return output->expr().first; } if (inputs.size() == 3) { auto scaleT = inputs[2]; - auto info = inputs[2]->getInfo(); - auto scale = scaleT->readMap(); - if (nullptr == scale) { - // Compute shape dynamic - mergeredResize->main.value = resizeParam.release(); - auto resizeExpr = Expr::create(mergeredResize.get(), {inputs[0], {inputs[2]}}); - resizeExpr->setName(expr->name()); - output = Variable::create(resizeExpr); - return output->expr().first; - } - MNN_THROW_CHECK(nullptr != scale, "Onnx resize's scale must be const"); - if (info->size > 2) { - resizeParam->heightScale = scale[2]; - } - if (info->size > 3) { - resizeParam->widthScale = scale[3]; - } + // Compute shape dynamic mergeredResize->main.value = resizeParam.release(); - auto resizeExpr = Expr::create(mergeredResize.get(), {inputs[0]}); + auto resizeExpr = Expr::create(mergeredResize.get(), {inputs[0], {inputs[2]}}); resizeExpr->setName(expr->name()); output = Variable::create(resizeExpr); return output->expr().first; diff --git a/tools/converter/source/optimizer/postconvert/MergeReluToBinary.cpp b/tools/converter/source/optimizer/postconvert/MergeReluToBinary.cpp new file mode 100644 index 000000000..771d89eb7 --- /dev/null +++ b/tools/converter/source/optimizer/postconvert/MergeReluToBinary.cpp @@ -0,0 +1,53 @@ +// +// MergeReluToBinaryOp.hpp +// MNNConverter +// +// Created by MNN on 2019/09/05. +// Copyright © 2018, Alibaba Group Holding Limited +// + +#include "../PostTreatUtils.hpp" +using namespace MNN; + +class MergeReluToBinaryOp : public PostConverter { +public: + virtual bool onExecute(std::unique_ptr& net) const override { + // Merge Layer + std::vector readyToDelete; + for (auto iter = net->oplists.begin(); iter != net->oplists.end(); iter++) { + MNN::OpT& currentOp = *(iter->get()); + if (currentOp.type != MNN::OpType_BinaryOp || currentOp.inputIndexes.size() != 2) { + continue; + } + DCHECK(currentOp.outputIndexes.size() == 1) << "Binary output ERROR!"; + + // merge Relu/Relu6 to Binary + std::vector nextOp = PostTreatUtils::_findOpByInputIndex(currentOp.outputIndexes[0], net.get()); + while (1) { + if (nextOp.size() != 1) { + break; + } + const int nextOutputIndex = nextOp[0]->outputIndexes[0]; + + bool nextRelu = (nextOp[0]->type == MNN::OpType_ReLU && nextOp[0]->main.AsRelu()->slope == 0.0f); + + if (PostTreatUtils::_isSingleInputOutput(nextOp[0]) && nextRelu) { + //LOG(INFO) << "Merge " << nextOp[0]->name.c_str()<< " into Binary: "; + // currentOp.name.c_str(); + currentOp.main.AsBinaryOp()->activationType = 1; + currentOp.outputIndexes[0] = nextOp[0]->outputIndexes[0]; + readyToDelete.push_back(nextOp[0]); + nextOp = PostTreatUtils::_findOpByInputIndex(nextOutputIndex, net.get()); + } else { + break; + } + } + } + for (auto op : readyToDelete) { + PostTreatUtils::_removeOpInNet(op, net.get()); + } + return true; + } +}; + +static PostConverterRegister __l("MergeReluToBinaryOp"); diff --git a/tools/cpp/backendTest.cpp b/tools/cpp/backendTest.cpp index 5763ae548..4af648ba1 100644 --- a/tools/cpp/backendTest.cpp +++ b/tools/cpp/backendTest.cpp @@ -85,6 +85,7 @@ static void compareForwadType(Interpreter* net, MNNForwardType expectType, MNNFo if (tensor->buffer().device == 0 && tensor->buffer().host == nullptr) { return true; } + std::shared_ptr copyTensor(new MNN::Tensor(tensor, tensor->getDimensionType())); tensor->copyToHostTensor(copyTensor.get()); correctResult.emplace_back(copyTensor); @@ -106,6 +107,8 @@ static void compareForwadType(Interpreter* net, MNNForwardType expectType, MNNFo if (tensor->buffer().device == 0 && tensor->buffer().host == nullptr) { return true; } + + tensor->wait(MNN::Tensor::MAP_TENSOR_READ, false); std::shared_ptr copyTensor(new MNN::Tensor(tensor, tensor->getDimensionType())); tensor->copyToHostTensor(copyTensor.get()); auto expectTensor = correctResult[index++]; diff --git a/tools/script/register.py b/tools/script/register.py index 5328f0c6a..ffa071753 100644 --- a/tools/script/register.py +++ b/tools/script/register.py @@ -160,8 +160,45 @@ def generateCoreMLFile(rootDir): f.write(l+'();\n') f.write("}\n}\n") +def generateNNAPIFile(rootDir): + coremlDir = os.path.join(rootDir, "source", "backend", "nnapi") + coremlExeDir = os.path.join(coremlDir, "execution") + coremlRegFile = os.path.join(coremlDir, "backend", "NNAPIOPRegister.cpp") + fileNames = os.listdir(coremlExeDir) + print(fileNames) + if len(fileNames) <= 1: + # Error dirs + return + funcNames = [] + for fi in fileNames: + f = os.path.join(coremlExeDir, fi) + if os.path.isdir(f): + continue + with open(f) as fileC: + c = fileC.read().split('\n') + c = list(filter(lambda l:l.find('REGISTER_NNAPI_OP_CREATOR')>=0, c)) + c = list(filter(lambda l:l.find('OpType')>=0, c)) + for l in c: + l = l.split('(')[1] + l = l.split(')')[0] + l = l.replace(' ', '') + l = l.split(',') + funcName = '___' + l[0] + '__' + l[1] + '__' + funcNames.append(funcName) + with open(coremlRegFile, 'w') as f: + f.write('// This file is generated by Shell for ops register\n') + f.write('namespace MNN {\n') + for l in funcNames: + f.write("extern void " + l + '();\n') + f.write('\n') + f.write('void registerNNAPIOps() {\n') + for l in funcNames: + f.write(l+'();\n') + f.write("}\n}\n") + import sys generateShape(sys.argv[1]) generateCPUFile(sys.argv[1]) generateGeoFile(sys.argv[1]) generateCoreMLFile(sys.argv[1]) +generateNNAPIFile(sys.argv[1])