4 Commits

Author	SHA1	Message	Date
liqing	28a6f1a614	beta 0.1.1.2 ... - fix register typo - add input count in conv model - add 5x5 winograd convolution for OpenCL - edit condition to use half in OpenCL - upgrade build.gradle	2019-05-14 19:54:21 +08:00
liqing	9bfb58a3ec	fix backend/op/sizer register	2019-05-09 19:39:33 +08:00
liqing	f2d6e8fe2d	beta 0.1.1.1 ... - use code generate for op/backend/sizer register - add pose demo - fix docs & script - improve cpu softmax performance 80% - improve converter ops fuse	2019-05-08 15:44:57 +08:00
liqing	5551108af8	beta 0.1.0	2019-04-19 20:50:09 +08:00