mirror of https://github.com/alibaba/MNN.git
266 lines
5.1 KiB
ArmAsm
266 lines
5.1 KiB
ArmAsm
//
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// MNNSamplerC1BilinearOpt.S
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// MNN
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//
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// Created by MNN on 2018/11/20.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifdef __aarch64__
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#include "MNNAsmGlobal.h"
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.text
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.align 5
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//void MNNSamplerC1BilinearOpt(const unsigned char* source, unsigned char* dest, float* points, size_t count, size_t iw, size_t ih, size_t yStride);
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asm_function MNNSamplerC1BilinearOpt
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//Auto: x0:source, x1:dest, x2:points, x3:count
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//Load: w4: xMax, w5: yMax, x6:yStride
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movi v23.4s, #0
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//v22.4s: ih-1, v23.4s:iw-1
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ld1 {v30.2s, v31.2s}, [x2]
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L8:
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cmp x3, #8
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blt L1
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dup v25.2d, x0
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dup v24.4s, w6
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dup v22.4s, w5
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dup v21.4s, w4
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ucvtf v22.4s, v22.4s
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ucvtf v21.4s, v21.4s
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movi v3.2s, #4
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scvtf v3.2s, v3.2s
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fmul v3.2s, v3.2s, v31.2s
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dup v26.4s, v3.s[0]
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dup v27.4s, v3.s[1]
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fadd v2.2s, v30.2s, v31.2s
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mov v28.s[0], v30.s[0]
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fadd v3.2s, v2.2s, v31.2s
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mov v29.s[0], v30.s[1]
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mov v28.s[1], v2.s[0]
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mov v29.s[1], v2.s[1]
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mov v28.s[2], v3.s[0]
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fadd v2.2s, v3.2s, v31.2s
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mov v29.s[2], v3.s[1]
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mov v28.s[3], v2.s[0]
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mov v29.s[3], v2.s[1]
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LoopL8:
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sub x3, x3, #8
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mov v4.16b, v28.16b
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mov v5.16b, v29.16b
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//v4, v6: x , v5, v7: y
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fmin v4.4s, v4.4s, v21.4s
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fadd v6.4s, v28.4s, v26.4s
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fadd v7.4s, v29.4s, v27.4s
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fmax v4.4s, v4.4s, v23.4s
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fmin v5.4s, v5.4s, v22.4s
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fadd v28.4s, v6.4s, v26.4s
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fadd v29.4s, v7.4s, v27.4s
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fmin v6.4s, v6.4s, v21.4s
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fmin v7.4s, v7.4s, v22.4s
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fmax v5.4s, v5.4s, v23.4s
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fmax v6.4s, v6.4s, v23.4s
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fmax v7.4s, v7.4s, v23.4s
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.macro COMPUTE_FOUR
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fcvtms v16.4s, v4.4s
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fcvtps v17.4s, v4.4s
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frintm v30.4s, v4.4s
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fcvtms v18.4s, v5.4s
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fcvtps v19.4s, v5.4s
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frintm v31.4s, v5.4s
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//v0: xf, v1:yf
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fabd v0.4s, v30.4s, v4.4s
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fabd v1.4s, v5.4s, v31.4s
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//v16, v17, v18, v19 -> x00, x01, x10, x11
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mul v30.4s, v18.4s, v24.4s
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mul v31.4s, v19.4s, v24.4s
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add v18.4s, v31.4s, v16.4s
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add v19.4s, v31.4s, v17.4s
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add v16.4s, v16.4s, v30.4s
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add v17.4s, v17.4s, v30.4s
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//Load
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uxtl v31.2d, v16.2s
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uxtl2 v30.2d, v16.4s
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uqadd v31.2d, v25.2d, v31.2d
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uqadd v30.2d, v25.2d, v30.2d
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mov x7, v31.d[0]
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ld1 {v2.b}[0], [x7]
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mov x7, v31.d[1]
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ld1 {v2.b}[1], [x7]
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mov x7, v30.d[0]
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ld1 {v2.b}[2], [x7]
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mov x7, v30.d[1]
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ld1 {v2.b}[3], [x7]
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uxtl v31.2d, v17.2s
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uxtl2 v30.2d, v17.4s
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uqadd v31.2d, v25.2d, v31.2d
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uqadd v30.2d, v25.2d, v30.2d
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mov x7, v31.d[0]
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ld1 {v2.b}[4], [x7]
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mov x7, v31.d[1]
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ld1 {v2.b}[5], [x7]
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mov x7, v30.d[0]
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ld1 {v2.b}[6], [x7]
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mov x7, v30.d[1]
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ld1 {v2.b}[7], [x7]
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uxtl v31.2d, v18.2s
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uxtl2 v30.2d, v18.4s
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uqadd v31.2d, v25.2d, v31.2d
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uqadd v30.2d, v25.2d, v30.2d
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mov x7, v31.d[0]
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ld1 {v3.b}[0], [x7]
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mov x7, v31.d[1]
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ld1 {v3.b}[1], [x7]
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mov x7, v30.d[0]
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ld1 {v3.b}[2], [x7]
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mov x7, v30.d[1]
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ld1 {v3.b}[3], [x7]
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uxtl v31.2d, v19.2s
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uxtl2 v30.2d, v19.4s
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uqadd v31.2d, v25.2d, v31.2d
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uqadd v30.2d, v25.2d, v30.2d
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mov x7, v31.d[0]
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ld1 {v3.b}[4], [x7]
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mov x7, v31.d[1]
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ld1 {v3.b}[5], [x7]
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mov x7, v30.d[0]
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ld1 {v3.b}[6], [x7]
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mov x7, v30.d[1]
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ld1 {v3.b}[7], [x7]
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uxtl v2.8h, v2.8b
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uxtl v3.8h, v3.8b
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uxtl v16.4s, v2.4h
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uxtl2 v17.4s, v2.8h
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uxtl v18.4s, v3.4h
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uxtl2 v19.4s, v3.8h
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ucvtf v16.4s, v16.4s
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ucvtf v17.4s, v17.4s
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ucvtf v18.4s, v18.4s
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ucvtf v19.4s, v19.4s
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fsub v17.4s, v17.4s, v16.4s
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fsub v19.4s, v19.4s, v18.4s
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fmla v16.4s, v17.4s, v0.4s
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fmla v18.4s, v19.4s, v0.4s
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fsub v18.4s, v18.4s, v16.4s
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fmla v16.4s, v18.4s, v1.4s
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fcvtzs v0.4s, v16.4s
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uqxtn v0.4h, v0.4s
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uqxtn v0.8b, v0.8h
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st1 {v0.s}[0], [x1], #4
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.endm
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COMPUTE_FOUR
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mov v4.16b, v6.16b
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mov v5.16b, v7.16b
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COMPUTE_FOUR
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cmp x3, #8
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bge LoopL8
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mov v30.s[0], v28.s[0]
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mov v30.s[1], v29.s[0]
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L1:
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cmp x3, #0
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beq End
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//int limit
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mov v21.s[0], w4
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mov v21.s[1], w5
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//float limit
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ucvtf v22.2s, v21.2s
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LoopL1:
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mov v0.8b, v30.8b
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fmin v0.2s, v0.2s, v22.2s
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fmax v0.2s, v0.2s, v23.2s
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fadd v30.2s, v30.2s, v31.2s
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//d1:x0y0, d2:x1y1
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fcvtms v1.2s, v0.2s // floor and turn int
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frintm v3.2s, v0.2s // floor
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fcvtps v2.2s, v0.2s // ceil and turn int
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//d16-d17 source pixels
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mov w8, v1.s[1]
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mov w7, v1.s[0]
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mov w9, v2.s[0]
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//v0:factor
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fabd v5.2s, v0.2s, v3.2s
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smull x8, w8, w6
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add x8, x8, x0
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sxtw x7, w7
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mov v6.s[0], v5.s[1]
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sxtw x9, w9
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add x10, x8, x7
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ld1 {v4.b}[0], [x10]
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add x10, x8, x9
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ld1 {v4.b}[1], [x10]
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mov w8, v2.s[1]
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umull x8, w8, w6
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add x8, x8, x0
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add x10, x8, x7
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ld1 {v4.b}[2], [x10]
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add x10, x8, x9
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ld1 {v4.b}[3], [x10]
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uxtl v4.8h, v4.8b
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uxtl v0.4s, v4.4h
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ucvtf v0.4s, v0.4s
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mov s1, v0.s[1]
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mov s2, v0.s[2]
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mov s3, v0.s[3]
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fsub s1, s1, s0
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fsub s3, s3, s2
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fmul s1, s1, s5
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fmul s3, s3, s5
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fadd s0, s0, s1
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fadd s2, s2, s3
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fsub s2, s2, s0
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fmul s2, s2, s6
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fadd s0, s0, s2
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fcvtzs s0, s0
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uqxtn v4.4h, v0.4s
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uqxtn v4.8b, v4.8h
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st1 {v4.b}[0], [x1], #1
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subs x3, x3, #1
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bne LoopL1
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End:
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ret
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#endif
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