mirror of https://github.com/alibaba/MNN.git
98 lines
3.7 KiB
C++
98 lines
3.7 KiB
C++
//
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// MatMulExecution.hpp
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// MNN
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//
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// Created by MNN on 2020/07/30.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifndef MatMulExecution_hpp
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#define MatMulExecution_hpp
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#include "backend/cuda/core/CUDABackend.hpp"
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#include "MNNCUDADefine.hpp"
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#include "CutlassGemmBatchedParam.hpp"
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#include "CutlassGemmParam.hpp"
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#include "MNNCUDAFunction.cuh"
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#ifdef ENABLE_CUDA_TUNE_PARAM
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#include "cutlass_common/tune/CutlassGemmTuneCommonExecution.hpp"
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#endif
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namespace MNN {
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namespace CUDA {
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class MatMulExecution :
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#ifdef ENABLE_CUDA_TUNE_PARAM
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public CutlassGemmTuneCommonExecution
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#else
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public Execution
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#endif
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{
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public:
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MatMulExecution(bool transposeA, bool transposeB, Backend *backend, int aS = 1, int bS = 1, int cS = 1);
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virtual ~MatMulExecution();
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virtual ErrorCode onResize(const std::vector<Tensor *> &inputs, const std::vector<Tensor *> &outputs) override;
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virtual ErrorCode onExecute(const std::vector<Tensor *> &inputs, const std::vector<Tensor *> &outputs) override;
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void setArguments(const std::vector<Tensor *> &inputs, const std::vector<Tensor *> &outputs);
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private:
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bool mTransposeA;
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bool mTransposeB;
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int mAs;
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int mBs;
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int mCs;
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Backend* mBackend = nullptr;
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std::shared_ptr<Tensor> mBiasTensor;
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GemmBatchedTensor_F16_F16_Linear_AlignCuda_Row_Column_Sm75 mGemmBatchedF16F16LnAlign1RCSm75;
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GemmTensor_F16_F16_Linear_AlignCuda_Sm75 mGemmF16F16LnAlign1Sm75;
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GemmBatchedTensor_F32_F32_Linear_AlignCuda_Row_Column_Sm75 mGemmBatchedF32F32LnAlign1RCSm75;
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GemmTensor_F32_F32_Linear_AlignCuda_Sm75 mGemmF32F32LnAlign1Sm75;
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GemmBatchedTensor_F16_F32_Linear_AlignCuda_Row_Column_Sm75 mGemmBatchedF16F32LnAlign1RCSm75;
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GemmTensor_F16_F32_Linear_AlignCuda_Sm75 mGemmF16F32LnAlign1Sm75;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Column_Sm75 mGemmBatchedF16F16LnAlign8RCSm75;
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GemmTensor_F16_F16_Linear_AlignTensor_Sm75 mGemmF16F16LnAlign8Sm75;
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GemmBatchedTensor_F32_F32_Linear_AlignTensor_Row_Column_Sm75 mGemmBatchedF32F32LnAlign8RCSm75;
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GemmTensor_F32_F32_Linear_AlignTensor_Sm75 mGemmF32F32LnAlign8Sm75;
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GemmBatchedTensor_F16_F32_Linear_AlignTensor_Row_Column_Sm75 mGemmBatchedF16F32LnAlign8RCSm75;
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GemmTensor_F16_F32_Linear_AlignTensor_Sm75 mGemmF16F32LnAlign8Sm75;
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GemmBatchedTensor_F16_F16_Linear_AlignTensor_Row_Row_Sm75 mGemmBatchedF16F16LnAlign8RRSm75;
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GemmBatchedTensor_F32_F32_Linear_AlignTensor_Row_Row_Sm75 mGemmBatchedF32F32LnAlign8RRSm75;
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GemmBatchedTensor_F16_F32_Linear_AlignTensor_Row_Row_Sm75 mGemmBatchedF16F32LnAlign8RRSm75;
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GemmBatchedCuda_F16_F16_Linear_AlignCuda_Row_Column mGemmBatchedCudaF16F16LnAlign1RC;
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GemmBatchedCuda_F32_F32_Linear_AlignCuda_Row_Column mGemmBatchedCudaF32F32LnAlign1RC;
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GemmBatchedCuda_F16_F32_Linear_AlignCuda_Row_Column mGemmBatchedCudaF16F32LnAlign1RC;
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GemmBatchedCuda_F16_F16_Linear_AlignCuda_Row_Row mGemmBatchedCudaF16F16LnAlign1RR;
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GemmBatchedCuda_F32_F32_Linear_AlignCuda_Row_Row mGemmBatchedCudaF32F32LnAlign1RR;
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GemmBatchedCuda_F16_F32_Linear_AlignCuda_Row_Row mGemmBatchedCudaF16F32LnAlign1RR;
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std::shared_ptr<Tensor> workspaceTensor;
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void* mWorkspace;
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void* mTempMatA;
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void* mTempMatB;
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void* mBiasPtr = nullptr;
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bool mNeedATempBuffer = false;
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bool mNeedBTempBuffer = false;
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bool mUseRRLayout = false;
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bool mResizeSetArgument = false;
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bool mNeedConvertMatAB = false;
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CutlassGemmInfo mGemmInfo;
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int mBatch = 1;
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int mGpuComputeCap;
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bool mIsTuned = false;
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bool mFp16Infer = false;
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bool mFp32Infer = false;
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bool mFp16Fp32MixInfer = false;
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bool mConvertGemmSplitK = false;
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bool mLargeBatchSmallGemm = false;
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};
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} // namespace CUDA
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} // namespace MNN
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#endif
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