mirror of https://github.com/alibaba/MNN.git
112 lines
3.7 KiB
C++
112 lines
3.7 KiB
C++
//
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// CutlassConvCommonExecution.hpp
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// MNN
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//
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// Created by MNN on 2023/03/22.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#ifndef CutlassConvCommonExecution_hpp
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#define CutlassConvCommonExecution_hpp
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#include "backend/cuda/core/CUDABackend.hpp"
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#include "core/Execution.hpp"
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#include "../CutlassGemmParam.hpp"
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#include "../bf16/CutlassGemmBf16Param.hpp"
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#include "../MNNCUDADefine.hpp"
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#include "../MNNCUDAFunction.cuh"
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#ifdef ENABLE_CUDA_TUNE_PARAM
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#include "tune/CutlassGemmTuneCommonExecution.hpp"
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#endif
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namespace MNN {
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namespace CUDA {
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class CutlassConvCommonExecution :
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#ifdef ENABLE_CUDA_TUNE_PARAM
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public CutlassGemmTuneCommonExecution
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#else
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public Execution
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#endif
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{
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public:
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CutlassConvCommonExecution(Backend* backend);
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virtual ~CutlassConvCommonExecution() = default;
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ErrorCode callCutlassGemmCudaCoreFloat16(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode callCutlassGemmCudaCoreFloat32(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode callCutlassGemmTensorCore884(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode callCutlassGemmTensorCore(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode callCutlassGemmBf16TensorCore(const std::vector<Tensor*> &inputs, const std::vector<Tensor*> &outputs);
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ErrorCode runCutlassGemmFunc();
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protected:
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Backend* mBackendPtr;
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void* mFilterAddr;
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void* mBiasAddr;
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CutlassGemmInfo mGemmInfo;
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const Op* mOp = nullptr;
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ConvolutionCommon::Im2ColParameter mIm2ColParamter;
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MemChunk mGpuIm2ColParam;
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void* mIm2ColBuffer;
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bool mIsConv1x1S1D1P0 = false;
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bool mNeedIm2Col = true;
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MemChunk mGpuKernelParam;
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bool mIsBlock = false;
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int mBlockNum = 1;
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GemmTensor_F16_F16_Linear_AlignTensor_Sm70 mGemmF16F16LnSm70;
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GemmTensor_F16_F32_Linear_AlignTensor_Sm70 mGemmF16F32LnSm70;
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GemmCuda_F16_F16_Linear_AlignCuda mGemmCudaF16F16Ln;
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GemmCuda_F16_F32_Linear_AlignCuda mGemmCudaF16F32Ln;
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GemmTensor_F16_F16_Relu_AlignTensor_Sm70 mGemmF16F16ReluSm70;
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GemmTensor_F16_F32_Relu_AlignTensor_Sm70 mGemmF16F32ReluSm70;
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GemmCuda_F16_F16_Relu_AlignCuda mGemmCudaF16F16Relu;
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GemmCuda_F16_F32_Relu_AlignCuda mGemmCudaF16F32Relu;
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GemmTensor_F16_F16_Relu6_AlignTensor_Sm70 mGemmF16F16Relu6Sm70;
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GemmTensor_F16_F32_Relu6_AlignTensor_Sm70 mGemmF16F32Relu6Sm70;
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GemmCuda_F16_F16_Relu6_AlignCuda mGemmCudaF16F16Relu6;
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GemmCuda_F16_F32_Relu6_AlignCuda mGemmCudaF16F32Relu6;
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GemmTensor_F16_F16_Linear_AlignTensor_Sm75 mGemmF16F16LnSm75;
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GemmTensor_F16_F32_Linear_AlignTensor_Sm75 mGemmF16F32LnSm75;
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GemmTensor_F16_F16_Relu_AlignTensor_Sm75 mGemmF16F16ReluSm75;
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GemmTensor_F16_F32_Relu_AlignTensor_Sm75 mGemmF16F32ReluSm75;
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GemmTensor_F16_F16_Relu6_AlignTensor_Sm75 mGemmF16F16Relu6Sm75;
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GemmTensor_F16_F32_Relu6_AlignTensor_Sm75 mGemmF16F32Relu6Sm75;
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GemmCuda_F32_F32_Relu_AlignCuda mGemmCudaF32F32Relu;
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GemmCuda_F32_F32_Relu6_AlignCuda mGemmCudaF32F32Relu6;
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GemmCuda_F32_F32_Linear_AlignCuda mGemmCudaF32F32Ln;
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#ifdef ENABLE_CUDA_BF16
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GemmTensor_BF16_BF16_Linear_AlignTensor_Sm80 mGemmBF16BF16LnSm80;
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GemmTensor_BF16_BF16_Relu_AlignTensor_Sm80 mGemmBF16BF16ReluSm80;
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GemmTensor_BF16_BF16_Relu6_AlignTensor_Sm80 mGemmBF16BF16Relu6Sm80;
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#endif
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int mGpuComputeCap = 75;
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bool mIsTuned = false;
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int mActivationType = 0;
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bool mFp16Infer = false;
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bool mFp32Infer = false;
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bool mFp16Fp32MixInfer = false;
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bool mBf16Infer = false;
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int mPrecisonLevel;
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std::shared_ptr<Tensor> workspaceTensor;
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void* mWorkspace;
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};
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} // namespace CUDA
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} // namespace MNN
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#endif /* CutlassConvCommonExecution */
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