From 917276a09738573bc3d1a582ab9956561bcd71ae Mon Sep 17 00:00:00 2001 From: Jiuyang liu Date: Thu, 12 Nov 2020 17:38:26 +0000 Subject: [PATCH] rewrite build.sc to depend on chisel and firrtl by source. --- .gitignore | 1 + .gitmodules | 18 +++++ Makefile | 12 ++- api-config-chipsalliance | 1 + berkeley-hardfloat | 1 + build.sc | 153 +++++++++++++++++++++------------------ chisel3 | 1 + chiseltest | 2 +- firrtl | 1 + rocket-chip | 2 +- treadle | 1 + 11 files changed, 117 insertions(+), 76 deletions(-) create mode 160000 api-config-chipsalliance create mode 160000 berkeley-hardfloat create mode 160000 chisel3 create mode 160000 firrtl create mode 160000 treadle diff --git a/.gitignore b/.gitignore index 7f7dca6d8..9c11124a9 100644 --- a/.gitignore +++ b/.gitignore @@ -342,6 +342,7 @@ hs_err_pid* .vscode .metals .bloop +.bsp .coursier mill.rdiB diff --git a/.gitmodules b/.gitmodules index 79125e2f5..e8db19adf 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,15 @@ +[submodule "chisel3"] + path = chisel3 + url = https://github.com/ucb-bar/chisel3 +[submodule "firrtl"] + path = firrtl + url = https://github.com/ucb-bar/firrtl +[submodule "treadle"] + path = treadle + url = https://github.com/ucb-bar/treadle +[submodule "hardfloat"] + path = hardfloat + url = https://github.com/ucb-bar/berkeley-hardfloat [submodule "rocket-chip"] path = rocket-chip url = https://github.com/chipsalliance/rocket-chip.git @@ -10,3 +22,9 @@ path = chiseltest url = https://github.com/ucb-bar/chisel-testers2.git branch = 3e3ecc5b25b7b6bc48341ec07c7a54b7ad53bcb7 +[submodule "api-config-chipsalliance"] + path = api-config-chipsalliance + url = https://github.com/chipsalliance/api-config-chipsalliance +[submodule "berkeley-hardfloat"] + path = berkeley-hardfloat + url = https://github.com/ucb-bar/berkeley-hardfloat diff --git a/Makefile b/Makefile index 4fbe1fab9..8acd31f90 100644 --- a/Makefile +++ b/Makefile @@ -129,11 +129,15 @@ cache: $(MAKE) emu IMAGE=Makefile clean: - rm -rf $(BUILD_DIR) + git submodule foreach git clean -fdx + git clean -fd init: git submodule update --init - @# do not use a recursive init to pull some not used submodules - cd ./rocket-chip/ && git submodule update --init api-config-chipsalliance hardfloat -.PHONY: verilog emu clean help init $(REF_SO) +bump: + git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master" + +bsp: + mill -i mill.contrib.BSP/install +.PHONY: verilog emu clean help init bump bsp $(REF_SO) diff --git a/api-config-chipsalliance b/api-config-chipsalliance new file mode 160000 index 000000000..fd8df1105 --- /dev/null +++ b/api-config-chipsalliance @@ -0,0 +1 @@ +Subproject commit fd8df1105a92065425cd353b6855777e35bd79b4 diff --git a/berkeley-hardfloat b/berkeley-hardfloat new file mode 160000 index 000000000..267357bda --- /dev/null +++ b/berkeley-hardfloat @@ -0,0 +1 @@ +Subproject commit 267357bdae5973a30565da6ebc728d513827ca5e diff --git a/build.sc b/build.sc index 09864c877..f342cbbe9 100644 --- a/build.sc +++ b/build.sc @@ -1,105 +1,118 @@ -import os.Path import mill._ import mill.modules.Util import scalalib._ -import coursier.maven.MavenRepository +import $ivy.`com.lihaoyi::mill-contrib-buildinfo:$MILL_VERSION` +import $ivy.`com.lihaoyi::mill-contrib-bsp:$MILL_VERSION` +import mill.contrib.buildinfo.BuildInfo +import $file.chisel3.build +import $file.firrtl.build +import $file.treadle.build +import $file.chiseltest.build +import $file.`berkeley-hardfloat`.build +import $file.`rocket-chip`.common +import $file.`api-config-chipsalliance`.`build-rules`.mill.build -object CustomZincWorkerModule extends ZincWorkerModule { - def repositories() = super.repositories ++ Seq( - MavenRepository("https://maven.aliyun.com/repository/public"), - MavenRepository("https://maven.aliyun.com/repository/apache-snapshots") - ) +val sv = "2.12.12" + +object myfirrtl extends firrtl.build.firrtlCrossModule(sv) { + override def millSourcePath = os.pwd / "firrtl" } +object mychisel3 extends chisel3.build.chisel3CrossModule(sv) { + override def millSourcePath = os.pwd / "chisel3" + + def firrtlModule: Option[PublishModule] = Some(myfirrtl) + + def treadleModule: Option[PublishModule] = Some(mytreadle) +} + +object mytreadle extends treadle.build.treadleCrossModule(sv) { + override def millSourcePath = os.pwd / "treadle" + + def firrtlModule: Option[PublishModule] = Some(myfirrtl) +} + +object mychiseltest extends chiseltest.build.chiseltestCrossModule(sv) { + override def scalaVersion = sv + override def millSourcePath = os.pwd / "chiseltest" + def chisel3Module: Option[PublishModule] = Some(mychisel3) + def treadleModule: Option[PublishModule] = Some(mytreadle) +} + +object myhardfloat extends `berkeley-hardfloat`.build.hardfloat { + override def scalaVersion = sv + + def chisel3Module: Option[PublishModule] = Some(mychisel3) +} + +object myconfig extends `api-config-chipsalliance`.`build-rules`.mill.build.config with PublishModule { + override def scalaVersion = sv + + override def millSourcePath = os.pwd / "api-config-chipsalliance" / "design" / "craft" + + override def pomSettings = T { + myrocketchip.pomSettings() + } + + override def publishVersion = T { + myrocketchip.publishVersion() + } +} + +object myrocketchip extends `rocket-chip`.common.CommonRocketChip { + override def scalaVersion = sv + + override def millSourcePath = os.pwd / "rocket-chip" + + def chisel3Module: Option[PublishModule] = Some(mychisel3) + + def hardfloatModule: PublishModule = myhardfloat + + def configModule: PublishModule = myconfig +} + + trait CommonModule extends ScalaModule { - override def scalaVersion = "2.12.10" + override def scalaVersion = sv override def scalacOptions = Seq("-Xsource:2.11") - override def zincWorker = CustomZincWorkerModule + override def moduleDeps: Seq[ScalaModule] = Seq(mychisel3) - private val macroParadise = ivy"org.scalamacros:::paradise:2.1.0" + private val macroParadise = ivy"org.scalamacros:::paradise:2.1.1" override def compileIvyDeps = Agg(macroParadise) override def scalacPluginIvyDeps = Agg(macroParadise) } -val chisel = Agg( - ivy"edu.berkeley.cs::chisel3:3.4.0" -) - -object `rocket-chip` extends SbtModule with CommonModule { - - override def ivyDeps = super.ivyDeps() ++ Agg( - ivy"${scalaOrganization()}:scala-reflect:${scalaVersion()}", - ivy"org.json4s::json4s-jackson:3.6.1" - ) ++ chisel - - - object `api-config-chipsalliance` extends CommonModule { - override def millSourcePath = super.millSourcePath / 'design / 'craft - } - - object macros extends SbtModule with CommonModule - - object hardfloat extends SbtModule with CommonModule { - override def ivyDeps = super.ivyDeps() ++ chisel - } - - override def moduleDeps = super.moduleDeps ++ Seq( - `api-config-chipsalliance`, macros, hardfloat - ) +object myinclusivecache extends CommonModule { + override def millSourcePath = os.pwd / "block-inclusivecache-sifive" / "design" / "craft" / "inclusivecache" + override def moduleDeps = super.moduleDeps ++ Seq(myrocketchip) } -object `block-inclusivecache-sifive` extends CommonModule { - override def ivyDeps = super.ivyDeps() ++ chisel - - override def millSourcePath = super.millSourcePath / 'design / 'craft / 'inclusivecache - - override def moduleDeps = super.moduleDeps ++ Seq(`rocket-chip`) +object myblocks extends CommonModule with SbtModule { + override def moduleDeps = super.moduleDeps ++ Seq(myrocketchip) } -object chiseltest extends CommonModule with SbtModule { - override def ivyDeps = super.ivyDeps() ++ Agg( - ivy"edu.berkeley.cs::treadle:1.3.0", - ivy"org.scalatest::scalatest:3.0.8", - ivy"com.lihaoyi::utest:0.7.4" - ) ++ chisel - object test extends Tests { - def ivyDeps = Agg(ivy"org.scalacheck::scalacheck:1.14.3") - def testFrameworks = Seq("org.scalatest.tools.Framework") - } -} - - object XiangShan extends CommonModule with SbtModule { override def millSourcePath = millOuterCtx.millSourcePath - override def forkArgs = Seq("-Xmx10G") - - override def ivyDeps = super.ivyDeps() ++ chisel override def moduleDeps = super.moduleDeps ++ Seq( - `rocket-chip`, - `block-inclusivecache-sifive`, - chiseltest + myrocketchip, + myinclusivecache, ) object test extends Tests { - override def ivyDeps = super.ivyDeps() ++ Agg( - ivy"org.scalatest::scalatest:3.0.4", - ivy"edu.berkeley.cs::chisel-iotesters:1.2+", + override def ivyDeps = Agg( + ivy"org.scalatest::scalatest:3.2.0", + ) + override def moduleDeps = super.moduleDeps ++ Seq( + mychiseltest ) - def testFrameworks = Seq( "org.scalatest.tools.Framework" ) - - def testOnly(args: String*) = T.command { - super.runMain("org.scalatest.tools.Runner", args: _*) - } } - } - diff --git a/chisel3 b/chisel3 new file mode 160000 index 000000000..e6192ea75 --- /dev/null +++ b/chisel3 @@ -0,0 +1 @@ +Subproject commit e6192ea75ce0d840b4b51a376921c2feecaa3b46 diff --git a/chiseltest b/chiseltest index 3e3ecc5b2..22d284600 160000 --- a/chiseltest +++ b/chiseltest @@ -1 +1 @@ -Subproject commit 3e3ecc5b25b7b6bc48341ec07c7a54b7ad53bcb7 +Subproject commit 22d2846004b03d545b657922f1a03c1497e3d847 diff --git a/firrtl b/firrtl new file mode 160000 index 000000000..c7bbb75b8 --- /dev/null +++ b/firrtl @@ -0,0 +1 @@ +Subproject commit c7bbb75b8b293d639848abaa9f68121f80947f42 diff --git a/rocket-chip b/rocket-chip index d6bd3c619..923ec05ed 160000 --- a/rocket-chip +++ b/rocket-chip @@ -1 +1 @@ -Subproject commit d6bd3c61993637c3f10544c59e861fae8af29f39 +Subproject commit 923ec05edecbbf509f614573b728ce8d029698aa diff --git a/treadle b/treadle new file mode 160000 index 000000000..7b786e802 --- /dev/null +++ b/treadle @@ -0,0 +1 @@ +Subproject commit 7b786e80233701adb16d2e8c39069669ec614b3a