diff --git a/src/main/scala/xiangshan/frontend/FrontendBundle.scala b/src/main/scala/xiangshan/frontend/FrontendBundle.scala
index fb15fd551..c8406ca4a 100644
--- a/src/main/scala/xiangshan/frontend/FrontendBundle.scala
+++ b/src/main/scala/xiangshan/frontend/FrontendBundle.scala
@@ -255,13 +255,19 @@ class PreDecodeInfo extends Bundle { // 8 bit
   def notCFI = brType === BrType.NotCfi
 }
 
+// pc = ftq.startAddr + Cat(offset, 0.U(1.W)) - Cat(borrow, 0.U(1.W))
+class FtqPcOffset(implicit p: Parameters) extends XSBundle {
+  val borrow = Bool()
+  val offset = UInt(log2Ceil(PredictWidth).W)
+}
+
 class FetchToIBuffer(implicit p: Parameters) extends XSBundle {
   val instrs           = Vec(PredictWidth, UInt(32.W))
   val valid            = UInt(PredictWidth.W)
   val enqEnable        = UInt(PredictWidth.W)
   val pd               = Vec(PredictWidth, new PreDecodeInfo)
   val foldpc           = Vec(PredictWidth, UInt(MemPredPCWidth.W))
-  val ftqOffset        = Vec(PredictWidth, ValidUndirectioned(UInt(log2Ceil(PredictWidth).W)))
+  val ftqPcOffset      = Vec(PredictWidth, ValidUndirectioned(new FtqPcOffset))
   val backendException = Vec(PredictWidth, Bool())
   val exceptionType    = Vec(PredictWidth, new ExceptionType)
   val crossPageIPFFix  = Vec(PredictWidth, Bool())
diff --git a/src/main/scala/xiangshan/frontend/IBuffer.scala b/src/main/scala/xiangshan/frontend/IBuffer.scala
index 25521442f..6af623a47 100644
--- a/src/main/scala/xiangshan/frontend/IBuffer.scala
+++ b/src/main/scala/xiangshan/frontend/IBuffer.scala
@@ -91,7 +91,7 @@ class IBufEntry(implicit p: Parameters) extends XSBundle {
   val pd               = new PreDecodeInfo
   val pred_taken       = Bool()
   val ftqPtr           = new FtqPtr
-  val ftqOffset        = UInt(log2Ceil(PredictWidth).W)
+  val ftqPcOffset      = new FtqPcOffset
   val exceptionType    = IBufferExceptionType()
   val backendException = Bool()
   val triggered        = TriggerAction()
@@ -99,13 +99,13 @@ class IBufEntry(implicit p: Parameters) extends XSBundle {
   val debug_seqNum     = InstSeqNum()
 
   def fromFetch(fetch: FetchToIBuffer, i: Int): IBufEntry = {
-    inst       := fetch.instrs(i)
-    pc         := fetch.pc(i)
-    foldpc     := fetch.foldpc(i)
-    pd         := fetch.pd(i)
-    pred_taken := fetch.ftqOffset(i).valid
-    ftqPtr     := fetch.ftqPtr
-    ftqOffset  := fetch.ftqOffset(i).bits
+    inst        := fetch.instrs(i)
+    pc          := fetch.pc(i)
+    foldpc      := fetch.foldpc(i)
+    pd          := fetch.pd(i)
+    pred_taken  := fetch.ftqPcOffset(i).valid
+    ftqPtr      := fetch.ftqPtr
+    ftqPcOffset := fetch.ftqPcOffset(i).bits
     exceptionType := IBufferExceptionType.cvtFromFetchExcpAndCrossPageAndRVCII(
       fetch.exceptionType(i),
       fetch.crossPageIPFFix(i),
@@ -139,7 +139,7 @@ class IBufEntry(implicit p: Parameters) extends XSBundle {
     cf.loadWaitStrict                    := DontCare
     cf.ssid                              := DontCare
     cf.ftqPtr                            := ftqPtr
-    cf.ftqOffset                         := ftqOffset
+    cf.ftqOffset                         := ftqPcOffset.offset
     cf.isLastInFtqEntry                  := isLastInFtqEntry
     cf.debug_seqNum                      := debug_seqNum
     cf
diff --git a/src/main/scala/xiangshan/frontend/ifu/Ifu.scala b/src/main/scala/xiangshan/frontend/ifu/Ifu.scala
index beb400093..1f23e1b0e 100644
--- a/src/main/scala/xiangshan/frontend/ifu/Ifu.scala
+++ b/src/main/scala/xiangshan/frontend/ifu/Ifu.scala
@@ -848,9 +848,10 @@ class Ifu(implicit p: Parameters) extends IfuModule
   io.toIBuffer.bits.pc        := s3_pc
   // Find last using PriorityMux
   io.toIBuffer.bits.isLastInFtqEntry := Reverse(PriorityEncoderOH(Reverse(io.toIBuffer.bits.enqEnable))).asBools
-  io.toIBuffer.bits.ftqOffset.zipWithIndex.foreach { case (a, i) =>
-    a.bits  := i.U
-    a.valid := checkerOutStage1.fixedTaken(i) && !s3_reqIsMmio
+  io.toIBuffer.bits.ftqPcOffset.zipWithIndex.foreach { case (a, i) =>
+    a.bits.borrow := false.B
+    a.bits.offset := i.U
+    a.valid       := checkerOutStage1.fixedTaken(i) && !s3_reqIsMmio
   }
   io.toIBuffer.bits.foldpc := s3_foldPc
   io.toIBuffer.bits.exceptionType := VecInit((s3_exceptionVec zip s3_crossPageExceptionVec).map { case (e, ce) =>