From d435f66e5b34ba24218ae61b0d8b427820a70b05 Mon Sep 17 00:00:00 2001 From: Muzi Date: Thu, 2 Oct 2025 09:10:06 +0800 Subject: [PATCH] fix(resolve): enqueue branch slot index --- src/main/scala/xiangshan/frontend/ftq/ResolveQueue.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/frontend/ftq/ResolveQueue.scala b/src/main/scala/xiangshan/frontend/ftq/ResolveQueue.scala index 78d0b2a08..92596406d 100644 --- a/src/main/scala/xiangshan/frontend/ftq/ResolveQueue.scala +++ b/src/main/scala/xiangshan/frontend/ftq/ResolveQueue.scala @@ -70,8 +70,8 @@ class ResolveQueue(implicit p: Parameters) extends FtqModule with HalfAlignHelpe mem(enqIndex(i)).bits.ftqIdx := branch.bits.ftqIdx mem(enqIndex(i)).bits.startVAddr := branch.bits.pc - val lastValid = mem(enqIndex(i)).bits.branches.lastIndexWhere(_.valid) - val branchSlot = mem(enqIndex(i)).bits.branches(lastValid + PopCount(hitPrevious(i)) + 1.U) + val firstEmpty = mem(enqIndex(i)).bits.branches.indexWhere(!_.valid) + val branchSlot = mem(enqIndex(i)).bits.branches(firstEmpty + PopCount(hitPrevious(i))) branchSlot.valid := true.B branchSlot.bits.target := branch.bits.target branchSlot.bits.taken := branch.bits.taken