diff --git a/Makefile b/Makefile
index 579a27614..9bb1e6715 100644
--- a/Makefile
+++ b/Makefile
@@ -88,7 +88,7 @@ MFC_ARGS += --split-verilog --dump-fir
 endif
 
 ifneq ($(FIRTOOL),)
-MFC_ARGS += --firtool-binary-path $(FIRTOOL)
+MFC_ARGS += --firtool-binary-path $(abspath $(FIRTOOL))
 endif
 
 # prefix of XSTop or XSNoCTop
@@ -201,6 +201,13 @@ else
 override SIM_ARGS += $(DEBUG_ARGS)
 endif
 
+# Coverage support
+ifneq ($(FIRRTL_COVER),)
+comma := ,
+splitcomma = $(foreach w,$(subst $(comma), ,$1),$(if $(strip $w),$w))
+override SIM_ARGS += $(foreach c,$(call splitcomma,$(FIRRTL_COVER)),--extract-$(c)-cover)
+endif
+
 # use RELEASE_ARGS for TopMain by default
 ifeq ($(PLDM), 1)
 TOPMAIN_ARGS += $(PLDM_ARGS)
diff --git a/difftest b/difftest
index 7f1ff0d03..0af0fec69 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 7f1ff0d039042f60e5e6a72a1e6f5426844324e9
+Subproject commit 0af0fec699446f78e9d5d01fb2606987a0540bb6
diff --git a/src/main/scala/top/ArgParser.scala b/src/main/scala/top/ArgParser.scala
index 2c8601138..b4b6c3fe0 100644
--- a/src/main/scala/top/ArgParser.scala
+++ b/src/main/scala/top/ArgParser.scala
@@ -226,7 +226,7 @@ object ArgParser {
           nextOption(config, tail)
       }
     }
-    val newArgs = DifftestModule.parseArgs(args)
+    val (newArgs, firtoolOptions) = DifftestModule.parseArgs(args)
     val config = nextOption(default, newArgs.toList).alter((site, here, up) => {
       case LogUtilsOptionsKey => LogUtilsOptions(
         here(DebugOptionsKey).EnableDebug,
@@ -240,6 +240,6 @@ object ArgParser {
         0
       )
     })
-    (config, firrtlOpts, firtoolOpts)
+    (config, firrtlOpts, firtoolOpts ++ firtoolOptions.map(_.option))
   }
 }