From ef913a6ad6801bab1ca28ee70af252642f098bbe Mon Sep 17 00:00:00 2001 From: Ziyue Zhang <46214232+Ziyue-Zhang@users.noreply.github.com> Date: Thu, 14 Aug 2025 15:15:33 +0800 Subject: [PATCH] fix(vlbusytable): remove wakeUpInt to avoid load fast wakes up vsetvli (#4941) --- src/main/scala/xiangshan/backend/rename/BusyTable.scala | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/main/scala/xiangshan/backend/rename/BusyTable.scala b/src/main/scala/xiangshan/backend/rename/BusyTable.scala index 722b832c8..8dc9f1625 100644 --- a/src/main/scala/xiangshan/backend/rename/BusyTable.scala +++ b/src/main/scala/xiangshan/backend/rename/BusyTable.scala @@ -88,7 +88,8 @@ class BusyTable(numReadPorts: Int, numWritePorts: Int, numPhyPregs: Int, pregWB: case FpWB(_, _) => allWakeUp.filter{x => x.bits.params.writeFpRf && !x.bits.params.hasLoadExu} case VfWB(_, _) => allWakeUp.filter(_.bits.params.writeVfRf) case V0WB(_, _) => allWakeUp.filter(_.bits.params.writeV0Rf) - case VlWB(_, _) => allWakeUp.filter(_.bits.params.writeVlRf) + // avoid load fast wakes, since load cancel signal not connected to vlbusytable, may have bug for vsetvli + case VlWB(_, _) => allWakeUp.filter(x => false) case _ => throw new IllegalArgumentException(s"WbConfig ${pregWB} is not permitted") } val loadDependency = RegInit(0.U.asTypeOf(Vec(numPhyPregs, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))))