From b80e92d8adea8eb0eafbbabecf1d4d3c8e404759 Mon Sep 17 00:00:00 2001 From: Zihao Yu Date: Sat, 23 Feb 2019 18:34:07 +0800 Subject: [PATCH 1/2] noop,fu,MDU: use pipeline multiplier * division should still trap --- src/main/scala/noop/Decode.scala | 4 ++-- src/main/scala/noop/EXU.scala | 5 ++++- src/main/scala/noop/fu/MDU.scala | 31 ++++++++++++++++++------------- 3 files changed, 24 insertions(+), 16 deletions(-) diff --git a/src/main/scala/noop/Decode.scala b/src/main/scala/noop/Decode.scala index ad240525d..8e250e2b3 100644 --- a/src/main/scala/noop/Decode.scala +++ b/src/main/scala/noop/Decode.scala @@ -56,6 +56,6 @@ object Instructions extends HasDecodeConst { def NOP = 0x00000013.U val DecodeDefault = List(InstrN, FuCsr, CsrJmp) val DecodeTable = ALUInstr.table ++ BRUInstr.table ++ LSUInstr.table ++ - //MDUInstr.table ++ CSRInstr.table ++ NOOPTrap.table - CSRInstr.table ++ NOOPTrap.table + MDUInstr.table ++ CSRInstr.table ++ NOOPTrap.table + //CSRInstr.table ++ NOOPTrap.table } diff --git a/src/main/scala/noop/EXU.scala b/src/main/scala/noop/EXU.scala index 90b5e68ef..10d60216b 100644 --- a/src/main/scala/noop/EXU.scala +++ b/src/main/scala/noop/EXU.scala @@ -74,7 +74,10 @@ class EXU extends Module with HasFuType { o.rfDest := i.rfDest } io.out.bits.pc := io.in.bits.pc - io.out.valid := io.in.valid && ((fuType =/= FuLsu) || lsu.io.out.valid) + io.out.valid := io.in.valid && MuxLookup(fuType, true.B, List( + FuLsu -> lsu.io.out.valid, + FuMdu -> mdu.io.out.valid + )) csr.io.instrCommit := io.csrCtrl.instrCommit } diff --git a/src/main/scala/noop/fu/MDU.scala b/src/main/scala/noop/fu/MDU.scala index f1a920dc4..460c2bfff 100644 --- a/src/main/scala/noop/fu/MDU.scala +++ b/src/main/scala/noop/fu/MDU.scala @@ -24,11 +24,11 @@ object MDUInstr extends HasDecodeConst { val table = Array( MUL -> List(InstrR, FuMdu, MduMul), - MULH -> List(InstrR, FuMdu, MduMulh), - DIV -> List(InstrR, FuMdu, MduDiv), - DIVU -> List(InstrR, FuMdu, MduDivu), - REM -> List(InstrR, FuMdu, MduRem), - REMU -> List(InstrR, FuMdu, MduRemu) + MULH -> List(InstrR, FuMdu, MduMulh) + //DIV -> List(InstrR, FuMdu, MduDiv), + //DIVU -> List(InstrR, FuMdu, MduDivu), + //REM -> List(InstrR, FuMdu, MduRem), + //REMU -> List(InstrR, FuMdu, MduRemu) ) } @@ -45,15 +45,20 @@ class MDU extends Module with HasMDUOpType { } val mulRes = (src1.asSInt * src2.asSInt).asUInt + val mulPipeOut = Pipe(io.in.fire(), mulRes, 4) io.out.bits := LookupTree(func, 0.U, List( - MduMul -> mulRes(31, 0), - MduMulh -> mulRes(63, 32), - MduDiv -> (src1.asSInt / src2.asSInt).asUInt, - MduDivu -> (src1 / src2), - MduRem -> (src1.asSInt % src2.asSInt).asUInt, - MduRemu -> (src1 % src2) + MduMul -> mulPipeOut.bits(31, 0), + MduMulh -> mulPipeOut.bits(63, 32) + //MduDiv -> (src1.asSInt / src2.asSInt).asUInt, + //MduDivu -> (src1 / src2), + //MduRem -> (src1.asSInt % src2.asSInt).asUInt, + //MduRemu -> (src1 % src2) )) - io.in.ready := true.B - io.out.valid := valid + val busy = RegInit(false.B) + when (io.in.valid && !busy) { busy := true.B } + when (mulPipeOut.valid) { busy := false.B } + + io.in.ready := !busy + io.out.valid := mulPipeOut.valid } From 41ec96a994234f6388a7f1a0cd3053d8f156c23a Mon Sep 17 00:00:00 2001 From: Zihao Yu Date: Sun, 24 Feb 2019 22:21:22 +0800 Subject: [PATCH 2/2] noop,fu,MDU: make mulLatency configurable --- src/main/scala/noop/fu/MDU.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/noop/fu/MDU.scala b/src/main/scala/noop/fu/MDU.scala index 460c2bfff..0cddaf51e 100644 --- a/src/main/scala/noop/fu/MDU.scala +++ b/src/main/scala/noop/fu/MDU.scala @@ -34,6 +34,7 @@ object MDUInstr extends HasDecodeConst { class MDU extends Module with HasMDUOpType { val io = IO(new FunctionUnitIO) + val mulLatency = 4 val (valid, src1, src2, func) = (io.in.valid, io.in.bits.src1, io.in.bits.src2, io.in.bits.func) def access(valid: Bool, src1: UInt, src2: UInt, func: UInt): UInt = { @@ -45,7 +46,7 @@ class MDU extends Module with HasMDUOpType { } val mulRes = (src1.asSInt * src2.asSInt).asUInt - val mulPipeOut = Pipe(io.in.fire(), mulRes, 4) + val mulPipeOut = Pipe(io.in.fire(), mulRes, mulLatency) io.out.bits := LookupTree(func, 0.U, List( MduMul -> mulPipeOut.bits(31, 0), MduMulh -> mulPipeOut.bits(63, 32) @@ -59,6 +60,6 @@ class MDU extends Module with HasMDUOpType { when (io.in.valid && !busy) { busy := true.B } when (mulPipeOut.valid) { busy := false.B } - io.in.ready := !busy + io.in.ready := (if (mulLatency == 0) true.B else !busy) io.out.valid := mulPipeOut.valid }