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In previous design, the smaller value between the stage1 and stage2
levels was always written back into the TLB entry. However, this
approach caused issues when exceptions occurred: a larger page could
mistakenly be treated as a smaller one. During TLB lookups this would
only result in performance bugs, for example:
(1) The first lookup of vpn 0x0 should return a 1 GB page, but instead a
2 MB page is written back. (2) The second lookup of vpn 0x0 + 4 MB
should hit, but because the level written back last time was incorrect,
it actually misses, triggering another PTW. (3) After the PTW completes,
a new 2 MB page starting at vpn 0x0 + 4 MB is written back.
However, this handling leads to a functional bug in the sfence scenario.
For a 1 GB page, an sfence with any address within the 1 GB range should
be able to invalidate the page. If the page is mistakenly treated as
only 2 MB, the sfence may fail to invalidate the page as expected,
causing a functional bug.
Specifically, for allStage with exceptions:
1. If stage1 encounters an exception, the entry’s level should be
written back as s1_level.
2. If stage2 encounters an exception: (1) If stage1 is a fakePTE, the
entry’s level should be written back as the maximum value (indicating
vsatp is misconfigured). (2) If stage1 is a non-leaf node, the entry’s
level should be written back as s1_level. (3) If stage1 is a leaf node,
the entry’s level should be written back as the smaller value of stage1
and stage2.
In fact, the stage1_level min stage2_level logic is used in multiple
places in the code. But in those other cases, it is only used for
lookups and does not affect sfence invalidation. Therefore, for now,
only this particular case needs to be fixed.
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1.Update Clint. Including two components: TIMER and SYSCNT.
2.TIMER is integrated inner XSTileWrap, while SYSCNT is integrated in
soc.
3.add SeperateTLBusIO: when it is true, TL bus appears as XSTOP IO port.
independent with new clint.
SeperateTLBusIO can be deleted after new clint ST test pass.
---------
Co-authored-by: good-circle <fenghaoyuan19@mails.ucas.ac.cn>
during the `s_pm` state, we set `isMisalignReg` from `isMisalignWire`.
Therefore, when `state === s_pm`, `isMisalignReg` has not yet been set,
so we need to modify it to `isMisalignReg`.
There is a situation:
* Cycle 0:
* tlb_req_0
* Cycle 1:
* tlb_req_0 -> need_gpa_wire
* tlb_req_1
* ptw_resp
* Cycle 2:
* need_gpa_wire -> need_gpa
* tlb_req_1 & ptw_resp -> p_hit (Bypass)
In this situation, need_gpa is set and would not be cleared, while the
origin tlb_req is responsed by bypass, so the TLB freezed.
This patch tries to fix this issue, by adding a p_hit_fast to get
whether bypass hit in Cycle 1.
The software-check exception caused by Zicfilp has higher priority than
an illegal-instruction exception but lower priority than instruction
access-fault
### 1. Purpose of this Pull Request
XSPdb is a specialized Python pdb-based debugging tool for RISC-V IP
cores, customized for Xiangshan's difftest interface. It provides
GDB-like interactive debugging capabilities, integrating: Terminal
command-line interface, RTL-level waveform toggling, Automated script
replay, System snapshot save/restore, Register initialization
configuration
### 2. Changes Made
* **New Tool (`XSPdb`)**: The core Python scripts for XSPdb have been
added under `scripts/xspdb/`. This tool provides an interactive
debugging console with standard pdb commands (e.g., breakpoints, step,
continue, register inspection).
* **Build System Integration**: A new Makefile, `pdb.mk`, has been
created to define the build targets and logic required for XSPdb.
* **Makefile Modification**: The root Makefile has been updated to
include `pdb.mk`, integrating the new `pdb` target into the main build
system.
### 3. Usage
The new tool can be built and used via a new `make` target.
1. **Build the XSPdb package**:
```bash
make pdb NOOP_HOME=$(pwd)
```
2. **Run a simulation with the XSPdb**:
```bash
make pdb-run NOOP_HOME=$(pwd)
```
---------
Co-authored-by: Zhicheng Yao <yaozhicheng@ict.ac.cn>
When use `-xprop=xmerge` policy, the un-initialized `stage1Hit` in Mux()
will cause the X-state propagate to output port `io.resp.valid`. Fix it
by moving `idle` check out of Mux(), which means the `io.resp.valid`
only valid when `!idle`.
The generated RTL will changed from:
```
wire io_resp_valid_0 =
stage1Hit
? ~idle & hptw_resp_stage2
: ~idle & mem_addr_update & ~need_last_s2xlate
& (guestFault | w_mem_resp & find_pte | s_pmp_check & accessFault | onlyS2xlate);
```
to:
```
wire io_resp_valid_0 =
~idle
& (stage1Hit
? hptw_resp_stage2
: mem_addr_update & ~need_last_s2xlate
& (guestFault | w_mem_resp & find_pte | s_pmp_check & accessFault
| onlyS2xlate));
```
Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>
The nc (non-cacheable) attribute instructions go through the MMIO
channel. Unlike standard MMIO instructions, nc instructions can be
executed speculatively. For MMIO instructions, there's no need to check
whether the IBuffer is full when enqueuing. However, nc instructions
must check for IBuffer fullness.
This PR primarily fixes the issue where nc instructions were incorrectly
allowed to enqueue into the IBuffer even when it was full.
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Some instances of this module may have io.out not connected. Under
normal circumstances, Chisel would not generate these modules, but due
to dontTouch here, these modules without io connections are still
generated. We do not yet understand the specific reason for this.
However, such Verilog cannot be synthesized on some FPGA platforms, so
in order to ensure the uniformity of RTL, we need to remove this code.
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In the previous design, vaddr was sign-extended to PAddrBits to prevent
cases where the physical address width exceeds the virtual address
width. However, in the SV48x4 mode, the actual width of vaddr is 50
bits, which ended up being truncated to 48 bits.
In the onlyStage2 case, the generated guest physical address (gpaddr)
should match vaddr. But due to the truncation, gpaddr was also limited
to 48 bits, and the upper 2 bits were lost (set to zero).
To fix this bug, and to better support future extensions—vaddr is now
extended to the maximum physical address width (PAddrBitsMax) as defined
by the RISC-V specification.
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`MemBackTypeMM`: requesting region backed by main memory (`!pmp.mmio`)
(don't care pbmt)
`MemPageTypeNC`: requesting `pbmt=nc` region (don't care backtype)
We need to tell L2 Cache about this via Tilelink to make it work.
This PR:
- ICache: Always work on main memory (`!pmp.mmio && pbmt=pmp`)
- `MemBackTypeMM` is always true
- `MemPageTypeNC` is always false (keep default value)
- Ifu/InstrUncache: Might be working on main memory, but pbmt=nc/io. Or
on real mmio region
- `MemBackTypeMM = !f3_pmp_mmio`
- `MemPageTypeNC = f3_itlb_pbmt === Pbmt.nc`
---------
Co-authored-by: Yanqin Li <maxpicca@qq.com>
* add bitmap wakeup the page table cache check hit state;
* modify the calculation of Bitmap permission data address, all of which
are accurate to 4K pages, and only return ITLB/DTLB page tables with 4K
granularity when permission check is enabled.
* fixed the issue that two requests in Bitmap check were merged and
missed the update permission;
* modify the permission query results of Super Page that are no longer
cached in PageTableCache;
* fixed the issue of l0Pets splicing format of PageTableCache output;
* fixed the issue that bitmap_checkfailed registers in PTW and HPTW were
not reset;
* fixed the issue that bitmapCacheEntry was not initialized;
* fixed the issue of Napot entry jmp_bitmap_check process;
* In BitmapCheck use parameters to selsct cf bits;
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This should not happen on a normal MMIO req (mmio is sent only when last
instruction is commited, so no redirect will happen).
But on a pbmt=nc area, we can do speculative fetch: #3944, so it can be
cancelled by backend/ifu redirects, we should reset MMIO fsm and cancel
(or flush) requests from InstrUncache.
The Napot extension requires that the lower 4 bits of the page table's
PPN satisfy 4'b1000. However, `pte_in.getPPN()` contains the original
PPN value, while ptw_resp.ppn has already been truncated once. So we
should use `pte_in.getPPN()` here to check Napot pages.
Haoyuan Feng
zhaohong1988
Tang Haojin
chengguanghui
Yanqin Li
Xin Tian
Yinan Xu
lwd
Xu, Zefan
Zhaoyang You
xu_zh
Muzi
SFangYy
Jiuyue Ma
Anzo
Ziyue Zhang
zhou tao
cz4e
Hu Gezhi
isaac