Commit Graph

41 Commits

Author SHA1 Message Date
LinJiawei 8cc1ac81c8 Backend: merge fp output and int output 2021-02-22 13:01:50 +08:00
Lingrui98 744c623c97 ftq and all: now we can compile 2021-01-22 23:18:59 +08:00
Yinan Xu bfb958a395 redirect: add redirect level to optimize redirect generation 2020-12-21 19:42:34 +08:00
ZhangZifei 0bdd9ead21 Merge branch 'master' into rs-sep 2020-11-24 17:09:22 +08:00
Yinan Xu 4693e1ab09 Merge remote-tracking branch 'origin/master' into fix-module-level 2020-11-18 12:30:42 +08:00
ZhangZifei cc1ab32b4b Alu: change Alu's log from Alu to AluExeUnit
the log in Alu will not have different name, so move it into
AluExeUnit module
2020-11-16 15:32:05 +08:00
ZhangZifei 6e86732da3 Alu: change Alu's log from Alu to AluExeUnit
the log in Alu will not have different name, so move it into
AluExeUnit module
2020-11-16 15:26:34 +08:00
LinJiawei 52c3f215e5 [WIP] exu: spilt exuConfig and it's module 2020-11-16 12:54:50 +08:00
LinJiawei 9684eb4fac EXU: spilt int data path and float data path 2020-11-15 20:35:03 +08:00
LinJiawei e18c367f53 [Backend]: Optimize exu and fu 2020-11-08 17:12:59 +08:00
LinJiawei 8b4ffe053b Merge remote-tracking branch 'origin/rs-new' into xs-fpu 2020-11-06 15:08:39 +08:00
Yinan Xu da10912fea src: remove unused import BoringUtils 2020-11-02 19:19:16 +08:00
Yinan Xu 35bfeecb90 csr: use IO for mtip,msip,meip 2020-11-02 18:46:22 +08:00
ZhangZifei 70017c2f06 RSNew: add redirect to BPQue && change MulDiv/Alu's log 2020-10-31 18:10:39 +08:00
Yinan Xu 42707b3b5e roqIdx: use CircularQueuePtr 2020-10-21 18:52:10 +08:00
GouLingrui 036b8a85fc Merge remote-tracking branch 'origin/master' into br-his 2020-09-16 13:07:33 +08:00
GouLingrui e077413e78 Merge remote-tracking branch 'origin/master' into br-his 2020-09-07 19:57:20 +08:00
ZhangZifei be4f89876b Redirect: fix redirect need flush and fix some log 2020-09-06 15:56:48 +08:00
ZhangZifei 45a56a299b Roq: add flush pipe logic for fence instr 2020-09-05 17:12:25 +08:00
ZhangZifei b8f08ca06c Fence: add fence decode and rewrite some fence logic. need roq redirect 2020-09-03 15:23:00 +08:00
ZhangZifei c1d738ede7 alu: fix bug of wrong sfence src 2020-08-25 16:59:54 +08:00
ZhangZifei 37ee565a9e TLB: add assert to avoid other alu(1/2/3) exec sfence/fence.i 2020-08-24 09:31:18 +08:00
ZhangZifei a8741d6f31 TLB: add sfence exec to ALU, the first alu 2020-08-23 21:24:55 +08:00
ZhangZifei c564e9b8b0 ALU: remove jump from ALU 2020-08-23 16:47:07 +08:00
zhanglinjuan e965d004d0 loop: add brTag compare when synchronizing specCnt with nSpecCnt 2020-08-12 23:14:07 +08:00
Lingrui98 59d92720f7 ALU, Jump: wrap roqIdx into brInfo 2020-08-01 19:10:07 +08:00
zhanglinjuan 608ba82cb0 backend: adaptive backend interface with frontend 2020-07-31 23:30:44 +08:00
LinJiawei 691af0f8d3 RoqIdx: rename 'olderThan' to 'needFlush' 2020-07-29 12:56:11 +08:00
LinJiawei b2e6921ea1 Refactor redirect, cputest pass, microbench fail 2020-07-28 20:53:53 +08:00
GouLingrui e1d867a0cf BPU, IFU, Ibuffer, EXU: fix instrvalid bug in BPU s1, fix bugs related to inst offset 2020-07-22 15:35:04 +08:00
zhanglinjuan d26eb7110c Merge branch 'bug-boringutils' into dev-bpu-rvc 2020-07-20 11:14:23 +08:00
zhanglinjuan af280c516c replace _type into btbType 2020-07-19 21:27:21 +08:00
zhanglinjuan 2f931f3763 ifu: support RVC prediction and late jump of RVI 2020-07-19 20:41:14 +08:00
LinJiawei aceedc59b6 Merge 'master' into 'add-fp' 2020-07-18 10:58:27 +08:00
LinJiawei c7054babd2 Freelist: use checkpoint to recovery 2020-07-16 22:59:41 +08:00
GouLingrui eca3848f2d Merge remote-tracking branch 'origin/master' into dev-bpu-pipeline-rebase 2020-07-15 22:52:05 +08:00
LinJiawei b9fd18920f Remove xiangshan.utils 2020-07-14 19:38:20 +08:00
zhanglinjuan 29e9d85c8c bpu: Merge: block Stage2 when Stage3 is blocked 2020-07-14 17:21:54 +08:00
jinyue110 376a2ab18e Merge branch 'master' into dev-frontend-debug 2020-07-12 16:20:49 +08:00
LinJiawei 65c62b20fb Merge master into refactor-exu 2020-07-11 15:40:01 +08:00
LinJiawei cafb355860 Refactor exu 2020-07-11 15:02:46 +08:00