Yinan Xu 7b441e5e45 alu: fix maxu/minu/rol/ror results (#1085) ... * bump difftest * alu: fix max and maxu result * alu: fix src1 generated by opcode Co-authored-by: Zhangfw <471348957@qq.com>		2021-10-04 11:29:26 +08:00
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autorun	misc: update PCL information (#899)	2021-07-24 23:26:38 +08:00
coverage	misc: update PCL information (#899)	2021-07-24 23:26:38 +08:00
utils	128KB L1D + non-inclusive L2/L3 (#1051)	2021-09-27 12:17:48 +08:00
statistics.py	misc: update PCL information (#899)	2021-07-24 23:26:38 +08:00
vlsi_mem_gen	scripts,vlsi_mem_gen: never split srams (#728)	2021-03-30 13:24:08 +08:00
xiangshan.py	alu: fix maxu/minu/rol/ror results (#1085)	2021-10-04 11:29:26 +08:00