Yinan Xu fd09b64ad1 dispatch2: optimize slow path and enqPtr matching timing (#1650) ... * dpq: add slow path for non-critical registers This commit separates the data module in Dispatch to slow and fast path. Slow path stores the data with a bad timing at Dispatch but a good timing at Dispatch2. Thus should benefit the timing at Dispatch, such as the LFST. For now, we merge the slow and fast data module. Chisel DCE does not eliminate the dead registers. We manully merge the two data modules for now. * dpq: optimize timing for enqPtr/deqPtr matching This commit optimizes the matching timing between enqPtr and deqPtr, which is used further for bypassing enqData to deqData. Now enqOffset and deqPtr/enqPtr matching work in parallel.		2022-07-13 21:27:51 +08:00
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main/scala	dispatch2: optimize slow path and enqPtr matching timing (#1650)	2022-07-13 21:27:51 +08:00
test/scala	sim,mmio: remove the vga device (#1638)	2022-07-12 09:45:19 +08:00