mirror of https://github.com/openssl/openssl.git
riscv: Provide a vector only implementation of Chacha20 cipher
Although we have a Zvkb version of Chacha20, the Zvkb from the RISC-V Vector Cryptography Bit-manipulation extension was ratified in late 2023 and does not come to the RVA23 Profile. Many CPUs in 2024 currently do not support Zvkb but may have Vector and Bit-manipulation, which are already in the RVA22 Profile. This commit provides a vector-only implementation that replaced the vror with vsll+vsrl+vor and can provide enough speed for Chacha20 for new CPUs this year. Signed-off-by: Yangyu Chen <cyy@cyyself.name> Reviewed-by: Paul Dale <ppzgs1@gmail.com> Reviewed-by: Tomas Mraz <tomas@openssl.org> (Merged from https://github.com/openssl/openssl/pull/24069)
This commit is contained in:
Yangyu Chen
Tomas Mraz
parent
7cbca5a6d6
commit
03ce37e117
254
crypto/chacha/asm/chacha-riscv64-zbb-zvkb.pl → crypto/chacha/asm/chacha-riscv64-v-zbb.pl
Normal file → Executable file
254
crypto/chacha/asm/chacha-riscv64-zbb-zvkb.pl → crypto/chacha/asm/chacha-riscv64-v-zbb.pl
Normal file → Executable file
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@ -37,9 +37,10 @@
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# - RV64I
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# - RISC-V Vector ('V') with VLEN >= 128
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# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
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# - RISC-V Basic Bit-manipulation extension ('Zbb')
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# - RISC-V Zicclsm(Main memory supports misaligned loads/stores)
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# Optional:
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# - RISC-V Vector Cryptography Bit-manipulation extension ('Zvkb')
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use strict;
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use warnings;
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@ -54,15 +55,18 @@ use riscv;
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my $output = $#ARGV >= 0 && $ARGV[$#ARGV] =~ m|\.\w+$| ? pop : undef;
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my $flavour = $#ARGV >= 0 && $ARGV[0] !~ m|\.| ? shift : undef;
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my $use_zvkb = $flavour && $flavour =~ /zvkb/i ? 1 : 0;
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my $isaext = "_v_zbb" . ( $use_zvkb ? "_zvkb" : "" );
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$output and open STDOUT, ">$output";
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my $code = <<___;
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.text
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___
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# void ChaCha20_ctr32_zbb_zvkb(unsigned char *out, const unsigned char *inp,
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# size_t len, const unsigned int key[8],
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# const unsigned int counter[4]);
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# void ChaCha20_ctr32@{[$isaext]}(unsigned char *out, const unsigned char *inp,
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# size_t len, const unsigned int key[8],
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# const unsigned int counter[4]);
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################################################################################
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my ( $OUTPUT, $INPUT, $LEN, $KEY, $COUNTER ) = ( "a0", "a1", "a2", "a3", "a4" );
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my ( $CONST_DATA0, $CONST_DATA1, $CONST_DATA2, $CONST_DATA3 ) = ( "a5", "a6",
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@ -90,6 +94,92 @@ my (
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$V22, $V23, $V24, $V25, $V26, $V27, $V28, $V29, $V30, $V31,
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) = map( "v$_", ( 0 .. 31 ) );
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sub chacha_sub_round {
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my (
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$A0, $B0, $C0,
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$A1, $B1, $C1,
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$A2, $B2, $C2,
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$A3, $B3, $C3,
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$S_A0, $S_B0, $S_C0,
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$S_A1, $S_B1, $S_C1,
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$S_A2, $S_B2, $S_C2,
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$S_A3, $S_B3, $S_C3,
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$ROL_SHIFT,
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$V_T0, $V_T1, $V_T2, $V_T3,
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) = @_;
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# a += b; c ^= a; c <<<= $ROL_SHIFT;
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if ($use_zvkb) {
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my $code = <<___;
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@{[vadd_vv $A0, $A0, $B0]}
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add $S_A0, $S_A0, $S_B0
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@{[vadd_vv $A1, $A1, $B1]}
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add $S_A1, $S_A1, $S_B1
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@{[vadd_vv $A2, $A2, $B2]}
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add $S_A2, $S_A2, $S_B2
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@{[vadd_vv $A3, $A3, $B3]}
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add $S_A3, $S_A3, $S_B3
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@{[vxor_vv $C0, $C0, $A0]}
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xor $S_C0, $S_C0, $S_A0
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@{[vxor_vv $C1, $C1, $A1]}
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xor $S_C1, $S_C1, $S_A1
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@{[vxor_vv $C2, $C2, $A2]}
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xor $S_C2, $S_C2, $S_A2
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@{[vxor_vv $C3, $C3, $A3]}
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xor $S_C3, $S_C3, $S_A3
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@{[vror_vi $C0, $C0, 32 - $ROL_SHIFT]}
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@{[roriw $S_C0, $S_C0, 32 - $ROL_SHIFT]}
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@{[vror_vi $C1, $C1, 32 - $ROL_SHIFT]}
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@{[roriw $S_C1, $S_C1, 32 - $ROL_SHIFT]}
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@{[vror_vi $C2, $C2, 32 - $ROL_SHIFT]}
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@{[roriw $S_C2, $S_C2, 32 - $ROL_SHIFT]}
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@{[vror_vi $C3, $C3, 32 - $ROL_SHIFT]}
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@{[roriw $S_C3, $S_C3, 32 - $ROL_SHIFT]}
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___
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return $code;
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} else {
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my $code = <<___;
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@{[vadd_vv $A0, $A0, $B0]}
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add $S_A0, $S_A0, $S_B0
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@{[vadd_vv $A1, $A1, $B1]}
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add $S_A1, $S_A1, $S_B1
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@{[vadd_vv $A2, $A2, $B2]}
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add $S_A2, $S_A2, $S_B2
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@{[vadd_vv $A3, $A3, $B3]}
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add $S_A3, $S_A3, $S_B3
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@{[vxor_vv $C0, $C0, $A0]}
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xor $S_C0, $S_C0, $S_A0
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@{[vxor_vv $C1, $C1, $A1]}
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xor $S_C1, $S_C1, $S_A1
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@{[vxor_vv $C2, $C2, $A2]}
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xor $S_C2, $S_C2, $S_A2
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@{[vxor_vv $C3, $C3, $A3]}
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xor $S_C3, $S_C3, $S_A3
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@{[vsll_vi $V_T0, $C0, $ROL_SHIFT]}
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@{[vsll_vi $V_T1, $C1, $ROL_SHIFT]}
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@{[vsll_vi $V_T2, $C2, $ROL_SHIFT]}
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@{[vsll_vi $V_T3, $C3, $ROL_SHIFT]}
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@{[vsrl_vi $C0, $C0, 32 - $ROL_SHIFT]}
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@{[vsrl_vi $C1, $C1, 32 - $ROL_SHIFT]}
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@{[vsrl_vi $C2, $C2, 32 - $ROL_SHIFT]}
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@{[vsrl_vi $C3, $C3, 32 - $ROL_SHIFT]}
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@{[vor_vv $C0, $C0, $V_T0]}
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@{[roriw $S_C0, $S_C0, 32 - $ROL_SHIFT]}
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@{[vor_vv $C1, $C1, $V_T1]}
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@{[roriw $S_C1, $S_C1, 32 - $ROL_SHIFT]}
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@{[vor_vv $C2, $C2, $V_T2]}
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@{[roriw $S_C2, $S_C2, 32 - $ROL_SHIFT]}
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@{[vor_vv $C3, $C3, $V_T3]}
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@{[roriw $S_C3, $S_C3, 32 - $ROL_SHIFT]}
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___
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return $code;
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}
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}
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sub chacha_quad_round_group {
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my (
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$A0, $B0, $C0, $D0,
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@ -101,109 +191,59 @@ sub chacha_quad_round_group {
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$S_A1, $S_B1, $S_C1, $S_D1,
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$S_A2, $S_B2, $S_C2, $S_D2,
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$S_A3, $S_B3, $S_C3, $S_D3,
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$V_T0, $V_T1, $V_T2, $V_T3,
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) = @_;
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my $code = <<___;
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# a += b; d ^= a; d <<<= 16;
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@{[vadd_vv $A0, $A0, $B0]}
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add $S_A0, $S_A0, $S_B0
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@{[vadd_vv $A1, $A1, $B1]}
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add $S_A1, $S_A1, $S_B1
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@{[vadd_vv $A2, $A2, $B2]}
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add $S_A2, $S_A2, $S_B2
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@{[vadd_vv $A3, $A3, $B3]}
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add $S_A3, $S_A3, $S_B3
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@{[vxor_vv $D0, $D0, $A0]}
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xor $S_D0, $S_D0, $S_A0
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@{[vxor_vv $D1, $D1, $A1]}
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xor $S_D1, $S_D1, $S_A1
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@{[vxor_vv $D2, $D2, $A2]}
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xor $S_D2, $S_D2, $S_A2
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@{[vxor_vv $D3, $D3, $A3]}
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xor $S_D3, $S_D3, $S_A3
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@{[vror_vi $D0, $D0, 32 - 16]}
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@{[roriw $S_D0, $S_D0, 32 - 16]}
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@{[vror_vi $D1, $D1, 32 - 16]}
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@{[roriw $S_D1, $S_D1, 32 - 16]}
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@{[vror_vi $D2, $D2, 32 - 16]}
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@{[roriw $S_D2, $S_D2, 32 - 16]}
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@{[vror_vi $D3, $D3, 32 - 16]}
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@{[roriw $S_D3, $S_D3, 32 - 16]}
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@{[chacha_sub_round
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$A0, $B0, $D0,
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$A1, $B1, $D1,
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$A2, $B2, $D2,
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$A3, $B3, $D3,
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$S_A0, $S_B0, $S_D0,
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$S_A1, $S_B1, $S_D1,
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$S_A2, $S_B2, $S_D2,
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$S_A3, $S_B3, $S_D3,
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16,
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$V_T0, $V_T1, $V_T2, $V_T3]}
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# c += d; b ^= c; b <<<= 12;
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@{[vadd_vv $C0, $C0, $D0]}
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add $S_C0, $S_C0, $S_D0
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@{[vadd_vv $C1, $C1, $D1]}
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add $S_C1, $S_C1, $S_D1
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@{[vadd_vv $C2, $C2, $D2]}
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add $S_C2, $S_C2, $S_D2
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@{[vadd_vv $C3, $C3, $D3]}
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add $S_C3, $S_C3, $S_D3
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@{[vxor_vv $B0, $B0, $C0]}
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xor $S_B0, $S_B0, $S_C0
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@{[vxor_vv $B1, $B1, $C1]}
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xor $S_B1, $S_B1, $S_C1
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@{[vxor_vv $B2, $B2, $C2]}
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xor $S_B2, $S_B2, $S_C2
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@{[vxor_vv $B3, $B3, $C3]}
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xor $S_B3, $S_B3, $S_C3
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@{[vror_vi $B0, $B0, 32 - 12]}
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@{[roriw $S_B0, $S_B0, 32 - 12]}
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@{[vror_vi $B1, $B1, 32 - 12]}
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@{[roriw $S_B1, $S_B1, 32 - 12]}
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@{[vror_vi $B2, $B2, 32 - 12]}
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@{[roriw $S_B2, $S_B2, 32 - 12]}
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@{[vror_vi $B3, $B3, 32 - 12]}
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@{[roriw $S_B3, $S_B3, 32 - 12]}
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@{[chacha_sub_round
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$C0, $D0, $B0,
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$C1, $D1, $B1,
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$C2, $D2, $B2,
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$C3, $D3, $B3,
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$S_C0, $S_D0, $S_B0,
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$S_C1, $S_D1, $S_B1,
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$S_C2, $S_D2, $S_B2,
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$S_C3, $S_D3, $S_B3,
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12,
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$V_T0, $V_T1, $V_T2, $V_T3]}
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# a += b; d ^= a; d <<<= 8;
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@{[vadd_vv $A0, $A0, $B0]}
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add $S_A0, $S_A0, $S_B0
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@{[vadd_vv $A1, $A1, $B1]}
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add $S_A1, $S_A1, $S_B1
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@{[vadd_vv $A2, $A2, $B2]}
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add $S_A2, $S_A2, $S_B2
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@{[vadd_vv $A3, $A3, $B3]}
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add $S_A3, $S_A3, $S_B3
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@{[vxor_vv $D0, $D0, $A0]}
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xor $S_D0, $S_D0, $S_A0
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@{[vxor_vv $D1, $D1, $A1]}
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xor $S_D1, $S_D1, $S_A1
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@{[vxor_vv $D2, $D2, $A2]}
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xor $S_D2, $S_D2, $S_A2
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@{[vxor_vv $D3, $D3, $A3]}
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xor $S_D3, $S_D3, $S_A3
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@{[vror_vi $D0, $D0, 32 - 8]}
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@{[roriw $S_D0, $S_D0, 32 - 8]}
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@{[vror_vi $D1, $D1, 32 - 8]}
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@{[roriw $S_D1, $S_D1, 32 - 8]}
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@{[vror_vi $D2, $D2, 32 - 8]}
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@{[roriw $S_D2, $S_D2, 32 - 8]}
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@{[vror_vi $D3, $D3, 32 - 8]}
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@{[roriw $S_D3, $S_D3, 32 - 8]}
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@{[chacha_sub_round
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$A0, $B0, $D0,
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$A1, $B1, $D1,
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$A2, $B2, $D2,
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$A3, $B3, $D3,
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$S_A0, $S_B0, $S_D0,
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$S_A1, $S_B1, $S_D1,
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$S_A2, $S_B2, $S_D2,
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$S_A3, $S_B3, $S_D3,
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8,
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$V_T0, $V_T1, $V_T2, $V_T3]}
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# c += d; b ^= c; b <<<= 7;
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@{[vadd_vv $C0, $C0, $D0]}
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add $S_C0, $S_C0, $S_D0
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@{[vadd_vv $C1, $C1, $D1]}
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add $S_C1, $S_C1, $S_D1
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@{[vadd_vv $C2, $C2, $D2]}
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add $S_C2, $S_C2, $S_D2
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@{[vadd_vv $C3, $C3, $D3]}
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add $S_C3, $S_C3, $S_D3
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@{[vxor_vv $B0, $B0, $C0]}
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xor $S_B0, $S_B0, $S_C0
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@{[vxor_vv $B1, $B1, $C1]}
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xor $S_B1, $S_B1, $S_C1
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@{[vxor_vv $B2, $B2, $C2]}
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xor $S_B2, $S_B2, $S_C2
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@{[vxor_vv $B3, $B3, $C3]}
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xor $S_B3, $S_B3, $S_C3
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@{[vror_vi $B0, $B0, 32 - 7]}
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@{[roriw $S_B0, $S_B0, 32 - 7]}
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@{[vror_vi $B1, $B1, 32 - 7]}
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@{[roriw $S_B1, $S_B1, 32 - 7]}
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@{[vror_vi $B2, $B2, 32 - 7]}
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@{[roriw $S_B2, $S_B2, 32 - 7]}
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@{[vror_vi $B3, $B3, 32 - 7]}
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@{[roriw $S_B3, $S_B3, 32 - 7]}
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@{[chacha_sub_round
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$C0, $D0, $B0,
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$C1, $D1, $B1,
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$C2, $D2, $B2,
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$C3, $D3, $B3,
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$S_C0, $S_D0, $S_B0,
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$S_C1, $S_D1, $S_B1,
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$S_C2, $S_D2, $S_B2,
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$S_C3, $S_D3, $S_B3,
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7,
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$V_T0, $V_T1, $V_T2, $V_T3]}
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___
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return $code;
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@ -211,9 +251,9 @@ ___
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$code .= <<___;
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.p2align 3
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.globl ChaCha20_ctr32_zbb_zvkb
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.type ChaCha20_ctr32_zbb_zvkb,\@function
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ChaCha20_ctr32_zbb_zvkb:
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.globl ChaCha20_ctr32@{[$isaext]}
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.type ChaCha20_ctr32@{[$isaext]},\@function
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ChaCha20_ctr32@{[$isaext]}:
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addi sp, sp, -96
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sd s0, 0(sp)
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sd s1, 8(sp)
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@ -305,7 +345,8 @@ ChaCha20_ctr32_zbb_zvkb:
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$STATE0, $STATE4, $STATE8, $STATE12,
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$STATE1, $STATE5, $STATE9, $STATE13,
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$STATE2, $STATE6, $STATE10, $STATE14,
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$STATE3, $STATE7, $STATE11, $STATE15]}
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$STATE3, $STATE7, $STATE11, $STATE15,
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$V24, $V25, $V26, $V27]}
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@{[chacha_quad_round_group
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$V3, $V4, $V9, $V14,
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$V0, $V5, $V10, $V15,
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@ -314,7 +355,8 @@ ChaCha20_ctr32_zbb_zvkb:
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$STATE3, $STATE4, $STATE9, $STATE14,
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$STATE0, $STATE5, $STATE10, $STATE15,
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$STATE1, $STATE6, $STATE11, $STATE12,
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$STATE2, $STATE7, $STATE8, $STATE13]}
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$STATE2, $STATE7, $STATE8, $STATE13,
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$V24, $V25, $V26, $V27]}
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bnez $T0, .Lround_loop
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li $T0, 64
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@ -468,7 +510,7 @@ ChaCha20_ctr32_zbb_zvkb:
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addi sp, sp, 96
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ret
|
||||
.size ChaCha20_ctr32_zbb_zvkb,.-ChaCha20_ctr32_zbb_zvkb
|
||||
.size ChaCha20_ctr32@{[$isaext]},.-ChaCha20_ctr32@{[$isaext]}
|
||||
___
|
||||
|
||||
print $code;
|
||||
|
|
@ -22,7 +22,7 @@ IF[{- !$disabled{asm} -}]
|
|||
|
||||
$CHACHAASM_c64xplus=chacha-c64xplus.s
|
||||
|
||||
$CHACHAASM_riscv64=chacha_riscv.c chacha_enc.c chacha-riscv64-zbb-zvkb.s
|
||||
$CHACHAASM_riscv64=chacha_riscv.c chacha_enc.c chacha-riscv64-v-zbb.s chacha-riscv64-v-zbb-zvkb.s
|
||||
$CHACHADEF_riscv64=INCLUDE_C_CHACHA20
|
||||
|
||||
# Now that we have defined all the arch specific variables, use the
|
||||
|
|
@ -53,4 +53,5 @@ GENERATE[chacha-s390x.S]=asm/chacha-s390x.pl
|
|||
GENERATE[chacha-ia64.S]=asm/chacha-ia64.pl
|
||||
GENERATE[chacha-ia64.s]=chacha-ia64.S
|
||||
GENERATE[chacha-loongarch64.S]=asm/chacha-loongarch64.pl
|
||||
GENERATE[chacha-riscv64-zbb-zvkb.s]=asm/chacha-riscv64-zbb-zvkb.pl
|
||||
GENERATE[chacha-riscv64-v-zbb.s]=asm/chacha-riscv64-v-zbb.pl
|
||||
GENERATE[chacha-riscv64-v-zbb-zvkb.s]=asm/chacha-riscv64-v-zbb.pl zvkb
|
||||
|
|
|
|||
|
|
@ -40,16 +40,23 @@
|
|||
#include "crypto/chacha.h"
|
||||
#include "crypto/riscv_arch.h"
|
||||
|
||||
void ChaCha20_ctr32_zbb_zvkb(unsigned char *out, const unsigned char *inp,
|
||||
size_t len, const unsigned int key[8],
|
||||
const unsigned int counter[4]);
|
||||
void ChaCha20_ctr32_v_zbb_zvkb(unsigned char *out, const unsigned char *inp,
|
||||
size_t len, const unsigned int key[8],
|
||||
const unsigned int counter[4]);
|
||||
|
||||
void ChaCha20_ctr32_v_zbb(unsigned char *out, const unsigned char *inp,
|
||||
size_t len, const unsigned int key[8],
|
||||
const unsigned int counter[4]);
|
||||
|
||||
void ChaCha20_ctr32(unsigned char *out, const unsigned char *inp, size_t len,
|
||||
const unsigned int key[8], const unsigned int counter[4])
|
||||
{
|
||||
if (len > CHACHA_BLK_SIZE && RISCV_HAS_ZVKB() && RISCV_HAS_ZBB() &&
|
||||
riscv_vlen() >= 128) {
|
||||
ChaCha20_ctr32_zbb_zvkb(out, inp, len, key, counter);
|
||||
if (len > CHACHA_BLK_SIZE && RISCV_HAS_ZBB() && riscv_vlen() >= 128) {
|
||||
if (RISCV_HAS_ZVKB()) {
|
||||
ChaCha20_ctr32_v_zbb_zvkb(out, inp, len, key, counter);
|
||||
} else {
|
||||
ChaCha20_ctr32_v_zbb(out, inp, len, key, counter);
|
||||
}
|
||||
} else {
|
||||
ChaCha20_ctr32_c(out, inp, len, key, counter);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -598,6 +598,15 @@ sub vmv_v_v {
|
|||
return ".word ".($template | ($vs1 << 15) | ($vd << 7));
|
||||
}
|
||||
|
||||
sub vor_vv {
|
||||
# vor.vv vd, vs2, vs1
|
||||
my $template = 0b0010101_00000_00000_000_00000_1010111;
|
||||
my $vd = read_vreg shift;
|
||||
my $vs2 = read_vreg shift;
|
||||
my $vs1 = read_vreg shift;
|
||||
return ".word ".($template | ($vs2 << 20) | ($vs1 << 15) | ($vd << 7));
|
||||
}
|
||||
|
||||
sub vor_vv_v0t {
|
||||
# vor.vv vd, vs2, vs1, v0.t
|
||||
my $template = 0b0010100_00000_00000_000_00000_1010111;
|
||||
|
|
@ -747,6 +756,15 @@ sub vsll_vi {
|
|||
return ".word ".($template | ($vs2 << 20) | ($uimm << 15) | ($vd << 7));
|
||||
}
|
||||
|
||||
sub vsrl_vi {
|
||||
# vsrl.vi vd, vs2, uimm, vm
|
||||
my $template = 0b1010001_00000_00000_011_00000_1010111;
|
||||
my $vd = read_vreg shift;
|
||||
my $vs2 = read_vreg shift;
|
||||
my $uimm = shift;
|
||||
return ".word ".($template | ($vs2 << 20) | ($uimm << 15) | ($vd << 7));
|
||||
}
|
||||
|
||||
sub vsrl_vx {
|
||||
# vsrl.vx vd, vs2, rs1
|
||||
my $template = 0b1010001_00000_00000_100_00000_1010111;
|
||||
|
|
|
|||
Loading…
Reference in New Issue