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Apply the AES-GCM unroll8 optimisation to Microsoft Azure Cobalt 100 

Performance improvements range from 18% to 32%.

Change-Id: Ifb89eeac3c0625a582a25ff07cf7f9c9ec8f5ba6

Reviewed-by: Hugo Landau <hlandau@openssl.org>
Reviewed-by: Neil Horman <nhorman@openssl.org>
Reviewed-by: Tomas Mraz <tomas@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/23651)
This commit is contained in:
Tom Cosgrove 2024-02-21 09:11:20 +00:00 committed by Tomas Mraz
parent 1afb326da4
commit 11adf9a75d
2 changed files with 4 additions and 0 deletions
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3
crypto/arm_arch.h
View File

@ -103,6 +103,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
# define ARM_CPU_IMP_ARM 0x41 # define ARM_CPU_IMP_ARM 0x41
# define HISI_CPU_IMP 0x48 # define HISI_CPU_IMP 0x48
# define ARM_CPU_IMP_APPLE 0x61 # define ARM_CPU_IMP_APPLE 0x61
# define ARM_CPU_IMP_MICROSOFT 0x6D
# define ARM_CPU_PART_CORTEX_A72 0xD08 # define ARM_CPU_PART_CORTEX_A72 0xD08
# define ARM_CPU_PART_N1 0xD0C # define ARM_CPU_PART_N1 0xD0C
@ -124,6 +125,8 @@ extern unsigned int OPENSSL_armv8_rsa_neonized;
# define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038 # define APPLE_CPU_PART_M2_BLIZZARD_MAX 0x038
# define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039 # define APPLE_CPU_PART_M2_AVALANCHE_MAX 0x039
# define MICROSOFT_CPU_PART_COBALT_100 0xD49
# define MIDR_PARTNUM_SHIFT 4 # define MIDR_PARTNUM_SHIFT 4
# define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT) # define MIDR_PARTNUM_MASK (0xfffU << MIDR_PARTNUM_SHIFT)
# define MIDR_PARTNUM(midr) \ # define MIDR_PARTNUM(midr) \

1
crypto/armcap.c
View File

@ -418,6 +418,7 @@ void OPENSSL_cpuid_setup(void)
} }
if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) || if ((MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) ||
MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) ||
MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_COBALT_100) ||
MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) && MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2)) &&
(OPENSSL_armcap_P & ARMV8_SHA3)) (OPENSSL_armcap_P & ARMV8_SHA3))
OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3; OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3;