mirror of https://github.com/openssl/openssl.git
				
				
				
			perlasm/sparcv9_modes.pl: fix typo in IV save code and switch to less
aggressive ASI.
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			@ -16,7 +16,15 @@
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# block sizes [though few percent better for not so long ones]. All
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# this based on suggestions from David Miller.
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my ($inp,$out,$len,$key,$ivec,$enc)=map("%i$_",(0..5));
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sub asm_init {		# to be called with @ARGV as argument
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    for (@_)		{ $::abibits=64 if (/\-m64/ || /\-xarch\=v9/); }
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    if ($::abibits==64)	{ $::bias=2047; $::frame=192; $::size_t_cc="%xcc"; }
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    else		{ $::bias=0;    $::frame=112; $::size_t_cc="%icc"; }
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}
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# unified interface
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my ($inp,$out,$len,$key,$ivec)=map("%i$_",(0..5));
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# local variables
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my ($ileft,$iright,$ooff,$omask,$ivoff,$blk_init)=map("%l$_",(0..7));
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sub alg_cbc_encrypt_implement {
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			@ -202,9 +210,9 @@ $::code.=<<___;
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	add		$inp, 16, $inp
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	sub		$len, 1, $len
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	stda		%f0, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f0, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	add		$out, 8, $out
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	stda		%f2, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f2, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	brnz,pt		$len, .L${bits}_cbc_enc_blk_loop
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	add		$out, 8, $out
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			@ -552,13 +560,13 @@ $::code.=<<___;
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	fxor		%f8, %f4, %f4
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	fxor		%f10, %f6, %f6
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	stda		%f0, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f0, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	add		$out, 8, $out
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	stda		%f2, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f2, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	add		$out, 8, $out
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	stda		%f4, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f4, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	add		$out, 8, $out
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	stda		%f6, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f6, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	bgu,pt		$::size_t_cc, .L${bits}_cbc_dec_blk_loop2x
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	add		$out, 8, $out
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			@ -571,17 +579,17 @@ $::code.=<<___;
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	nop
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___
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$::code.=<<___ if ($::evp);
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	st		%f0, [$ivec + 0]
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	st		%f1, [$ivec + 4]
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	st		%f2, [$ivec + 8]
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	st		%f3, [$ivec + 12]
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	st		%f12, [$ivec + 0]	! write out ivec
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	st		%f13, [$ivec + 4]
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	st		%f14, [$ivec + 8]
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	st		%f15, [$ivec + 12]
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___
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$::code.=<<___ if (!$::evp);
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	brnz,pn		$ivoff, 3b
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	nop
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	std		%f0, [$ivec + 0]	! write out ivec
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	std		%f2, [$ivec + 8]
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	std		%f12, [$ivec + 0]	! write out ivec
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	std		%f14, [$ivec + 8]
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___
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$::code.=<<___;
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	ret
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			@ -867,13 +875,13 @@ $::code.=<<___;
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	fxor		%f12, %f4, %f4
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	fxor		%f8, %f6, %f6
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	stda		%f0, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f0, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	add		$out, 8, $out
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	stda		%f2, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f2, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	add		$out, 8, $out
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	stda		%f4, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f4, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	add		$out, 8, $out
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	stda		%f6, [$out]0xf2		! ASI_BLK_INIT, T4-specific
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	stda		%f6, [$out]0xe2		! ASI_BLK_INIT, T4-specific
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	bgu,pt		$::size_t_cc, .L${bits}_ctr32_blk_loop2x
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	add		$out, 8, $out
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