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RISC-V: Add Zbb orn and its pseudo instruction opcode to rv64gc in riscv.pm 

Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>

Reviewed-by: Paul Yang <paulyang.inf@gmail.com>
Reviewed-by: Paul Dale <ppzgs1@gmail.com>
(Merged from https://github.com/openssl/openssl/pull/27990)
This commit is contained in:
Julian Zhu 2025-07-08 18:09:36 +08:00 committed by Pauli
parent ba2c314a60
commit 5a68746099
1 changed files with 19 additions and 0 deletions
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19
crypto/perlasm/riscv.pm
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@ -289,6 +289,15 @@ ___
return $code;
}
sub orn_rv64i {
my ($rd, $rs1, $rs2) = @_;
my $code=<<___;
not $rd, $rs2
or $rd, $rd, $rs1
___
return $code;
}
# Scalar crypto instructions
sub aes64ds {
@ -388,6 +397,16 @@ sub clmulh {
return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
}
sub orn {
# Encoding for orn rd, rs1, rs2
# 0100000 _ rs2 _ rs1 _110_ rd _0110011
my $template = 0b0100000_00000_00000_110_00000_0110011;
my $rd = read_reg shift;
my $rs1 = read_reg shift;
my $rs2 = read_reg shift;
return ".word ".($template | ($rs2 << 20) | ($rs1 << 15) | ($rd << 7));
}
sub rev8 {
# Encoding for rev8 rd, rs instruction on RV64
# XXXXXXXXXXXXX_ rs _XXX_ rd _XXXXXXX