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Add AES implementation in generic riscv64 asm 

This implementation is based on the four-table approach, along the same
lines as the non-constant-time implementation in aes_core.c The
implementation is in perlasm.

Utility functions are defined to automatically stack/unstack registers
as needed for prologues and epilogues. See riscv-elf-psabi-doc at
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/ for ABI details.

Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Signed-off-by: Henry Brausen <henry.brausen@vrull.eu>

Reviewed-by: Tomas Mraz <tomas@openssl.org>
Reviewed-by: Paul Dale <pauli@openssl.org>
(Merged from https://github.com/openssl/openssl/pull/17640)
This commit is contained in:
Henry Brausen 2022-01-28 01:13:04 -07:00 committed by Pauli
parent ec26144288
commit b3504b600c
2 changed files with 1714 additions and 0 deletions
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1709
crypto/aes/asm/aes-riscv64.pl Normal file
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5
crypto/aes/build.info
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@ -47,6 +47,9 @@ IF[{- !$disabled{asm} -}]
# aes-c64xplus.s implements AES_ctr32_encrypt
$AESDEF_c64xplus=AES_ASM AES_CTR_ASM
$AESASM_riscv64=aes_cbc.c aes-riscv64.s
$AESDEF_riscv64=AES_ASM
# Now that we have defined all the arch specific variables, use the
# appropriate one, and define the appropriate macros
IF[$AESASM_{- $target{asm_arch} -}]
@ -114,6 +117,8 @@ GENERATE[aes-parisc.s]=asm/aes-parisc.pl
GENERATE[aes-mips.S]=asm/aes-mips.pl
INCLUDE[aes-mips.o]=..
GENERATE[aes-riscv64.s]=asm/aes-riscv64.pl
GENERATE[aesv8-armx.S]=asm/aesv8-armx.pl
INCLUDE[aesv8-armx.o]=..
GENERATE[vpaes-armv8.S]=asm/vpaes-armv8.pl