mirror of https://github.com/alibaba/MNN.git
113 lines
4.3 KiB
C++
113 lines
4.3 KiB
C++
//
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// CPUInstanceNorm.hpp
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// MNN
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//
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// Created by MNN on 2019/02/28.
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// Copyright © 2018, Alibaba Group Holding Limited
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//
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#include "backend/cpu/CPUInstanceNorm.hpp"
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#include <math.h>
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#include "backend/cpu/CPUBackend.hpp"
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#include "core/Concurrency.h"
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#include <MNN/MNNDefine.h>
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#include "core/Macro.h"
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#include "core/TensorUtils.hpp"
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#ifdef MNN_USE_NEON
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#include <arm_neon.h>
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#endif
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namespace MNN {
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CPUInstanceNorm::CPUInstanceNorm(Backend* backend, const MNN::Op* op) : Execution(backend) {
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auto normParam = op->main_as_BatchNorm();
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const int channels = normParam->channels();
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mEpsilon = normParam->epsilon();
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mScale.reset(ALIGN_UP4(channels));
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mScale.clear();
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if (normParam->slopeData() && normParam->slopeData()->data()) {
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::memcpy(mScale.get(), normParam->slopeData()->data(), channels * sizeof(float));
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}
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mBias.reset(ALIGN_UP4(channels));
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mBias.clear();
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if (normParam->biasData() && normParam->biasData()->data()) {
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::memcpy(mBias.get(), normParam->biasData()->data(), channels * sizeof(float));
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}
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}
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ErrorCode CPUInstanceNorm::onExecute(const std::vector<Tensor*>& inputs, const std::vector<Tensor*>& outputs) {
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MNN_ASSERT(3 == inputs.size());
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MNN_ASSERT(1 == outputs.size());
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auto input = inputs[0];
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MNN_ASSERT(MNN_DATA_FORMAT_NC4HW4 == TensorUtils::getDescribe(input)->dimensionFormat);
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auto mean = inputs[1];
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auto variance = inputs[2];
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auto output = outputs[0];
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const int batch = input->batch();
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const int batchStride = input->stride(0);
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const int channelsDiv4 = UP_DIV(input->channel(), 4);
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const int inImageSize = input->stride(1);
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const float* scalePtr = mScale.get();
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const float* biasPtr = mBias.get();
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const float* meanPtr = mean->host<float>();
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const float* variancePtr = variance->host<float>();
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for (int b = 0; b < batch; ++b) {
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const float* batchMeanPtr = meanPtr + b * mean->stride(0);
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const float* batchVariancePtr = variancePtr + b * variance->stride(0);
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const float* batchInputPtr = input->host<float>() + b * batchStride;
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float* batchOutputPtr = output->host<float>() + b * batchStride;
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MNN_CONCURRENCY_BEGIN(ic, channelsDiv4);
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const int channelOffset = (int)ic << 2;
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const float* channelsInputPtr = batchInputPtr + channelOffset * inImageSize;
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float* channelsOutputPtr = batchOutputPtr + channelOffset * inImageSize;
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#ifdef MNN_USE_NEON
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float32x4_t epsilon = vdupq_n_f32(mEpsilon);
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float32x4_t batchVariance = vld1q_f32(batchVariancePtr + channelOffset);
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float32x4_t meanValue = vld1q_f32(batchMeanPtr + channelOffset);
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float32x4_t scaleValue = vld1q_f32(scalePtr + channelOffset);
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float32x4_t biasVaule = vld1q_f32(biasPtr + channelOffset);
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float32x4_t rsqrt = vrsqrteq_f32(batchVariance + epsilon);
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float32x4_t gamma = vmulq_f32(scaleValue, rsqrt);
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float32x4_t beta = vsubq_f32(biasVaule, meanValue * gamma);
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for (int i = 0; i < inImageSize; ++i) {
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float32x4_t value = vld1q_f32(channelsInputPtr + i * 4);
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vst1q_f32(channelsOutputPtr + i * 4, value * gamma + beta);
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}
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#else
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float gamma[4];
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float beta[4];
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for (int k = 0; k < 4; ++k) {
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const int index = channelOffset + k;
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gamma[k] = scalePtr[index] / sqrt(batchVariancePtr[index] + mEpsilon);
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beta[k] = biasPtr[index] - scalePtr[index] * batchMeanPtr[index] / sqrt(batchVariancePtr[index] + mEpsilon);
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}
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for (int i = 0; i < inImageSize; ++i) {
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for (int k = 0; k < 4; ++k) {
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channelsOutputPtr[i * 4 + k] = channelsInputPtr[i * 4 + k] * gamma[k] + beta[k];
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}
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}
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#endif
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MNN_CONCURRENCY_END();
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}
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return NO_ERROR;
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}
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class CPUInstanceNormCreator : public CPUBackend::Creator {
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public:
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virtual Execution* onCreate(const std::vector<Tensor*>& inputs, const std::vector<Tensor*>& outputs,
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const MNN::Op* op, Backend* backend) const override {
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return new CPUInstanceNorm(backend, op);
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}
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};
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REGISTER_CPU_OP_CREATOR(CPUInstanceNormCreator, OpType_InstanceNorm);
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} // namespace MNN
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