33 lines
743 B
Scala
33 lines
743 B
Scala
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package device
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import chisel3._
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import chisel3.util._
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import chipsalliance.rocketchip.config.Parameters
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import freechips.rocketchip.diplomacy.AddressSet
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import utils._
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// we support 256 interrupt bits by default
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class IntrGenIO extends Bundle {
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val intrVec = Output(UInt(256.W))
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}
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class AXI4IntrGenerator
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(
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address: Seq[AddressSet]
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)(implicit p: Parameters)
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extends AXI4SlaveModule(address, executable = false, _extra = new IntrGenIO)
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{
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override lazy val module = new AXI4SlaveModuleImp(this){
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val intrReg = RegInit(VecInit(Seq.fill(8)(0.U(32.W))))
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io.extra.get.intrVec := Cat(intrReg.reverse)
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when (in.w.fire()) {
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intrReg(waddr(4, 2)) := in.w.bits.data(31, 0)
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}
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in.r.bits.data := intrReg(raddr)
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}
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}
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