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Merge 1d4ac8f12f into 1e7e38e249

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junxiong-ji 2025-04-22 10:21:37 +08:00 committed by GitHub
parent 1e7e38e249 1d4ac8f12f
commit 1855c8aba4
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GPG Key ID: B5690EEEBB952194
2 changed files with 200 additions and 188 deletions
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316
src/main/scala/xiangshan/backend/fu/Bku.scala
View File

@ -22,43 +22,70 @@ import chisel3.util._
import utility.{LookupTreeDefault, ParallelMux, ParallelXOR, SignExt, ZeroExt}
import utility.{XSDebug, XSError}
import xiangshan._
import xiangshan.HasXSParameter
import xiangshan.backend.fu.util._
class CountModule(implicit p: Parameters) extends XSModule {
val io = IO(new Bundle() {
val src = Input(UInt(XLEN.W))
val func = Input(UInt())
val regEnable = Input(Bool())
val out = Output(UInt(XLEN.W))
})
class BkuSrcInput(implicit p: Parameters) extends XSBundle {
val src: Vec[UInt] = Vec(2, UInt(XLEN.W))
val func: UInt = FuOpType()
val regEnable: Bool = Bool()
val funcReg: UInt = FuOpType()
def connect(src: Vec[UInt], func: UInt, regEnable: Bool, funcReg: UInt): Unit = {
this.src := src
this.func := func
this.regEnable := regEnable
this.funcReg := funcReg
}
}
/**
* 2-input, 1-output function unit IO bundle for BKU
*/
class BkuSrcIO(implicit p: Parameters) extends XSBundle {
val in : BkuSrcInput = Input(new BkuSrcInput)
val out: UInt = Output(UInt(XLEN.W))
}
/**
* BKU module with 2 input and 1 output
*/
abstract class BkuSrcModule(implicit p: Parameters) extends XSModule {
val io: BkuSrcIO = IO(new BkuSrcIO)
val src1 = io.in.src(0)
val src2 = io.in.src(1)
val func = io.in.func
val regEnable = io.in.regEnable
val funcReg = io.in.funcReg
}
class CountModule(implicit p: Parameters) extends BkuSrcModule {
def encode(bits: UInt): UInt = {
LookupTreeDefault(bits, 0.U, List(0.U -> 2.U(2.W), 1.U -> 1.U(2.W)))
}
def clzi(msb: Int, left: UInt, right: UInt): UInt = {
Mux(left(msb),
Cat(left(msb) && right(msb), !right(msb), if(msb==1)right(0) else right(msb-1, 0)),
Cat(left(msb) && right(msb), !right(msb), if (msb == 1) right(0) else right(msb - 1, 0)),
left)
}
// stage 0
val c0 = Wire(Vec(32, UInt(2.W)))
val c1 = Wire(Vec(16, UInt(3.W)))
val countSrc = Mux(io.func(1), Reverse(io.src), io.src)
val countSrc = Mux(func(1), Reverse(src1), src1)
for(i <- 0 until 32){ c0(i) := encode(countSrc(2*i+1, 2*i)) }
for(i <- 0 until 16){ c1(i) := clzi(1, c0(i*2+1), c0(i*2)) }
for(i <- 0 until 32){ c0(i) := encode(countSrc(2 * i + 1, 2 * i)) }
for(i <- 0 until 16){ c1(i) := clzi(1, c0(i * 2 + 1), c0(i * 2)) }
// pipeline registers
val funcReg = RegEnable(io.func, io.regEnable)
val c2 = Reg(Vec(8, UInt(4.W)))
val cpopTmp = Reg(Vec(4, UInt(5.W)))
when (io.regEnable) {
when (regEnable) {
for (i <- 0 until 8) {
c2(i) := clzi(2, c1(i*2+1), c1(i*2))
c2(i) := clzi(2, c1(i * 2 + 1), c1(i * 2))
}
for (i <- 0 until 4) {
cpopTmp(i) := PopCount(io.src(i*16+15, i*16))
cpopTmp(i) := PopCount(src1(i * 16 + 15, i * 16))
}
}
@ -66,8 +93,8 @@ class CountModule(implicit p: Parameters) extends XSModule {
val c3 = Wire(Vec(4, UInt(5.W)))
val c4 = Wire(Vec(2, UInt(6.W)))
for(i <- 0 until 4){ c3(i) := clzi(3, c2(i*2+1), c2(i*2)) }
for(i <- 0 until 2){ c4(i) := clzi(4, c3(i*2+1), c3(i*2)) }
for (i <- 0 until 4) { c3(i) := clzi(3, c2(i * 2 + 1), c2(i * 2)) }
for (i <- 0 until 2) { c4(i) := clzi(4, c3(i * 2 + 1), c3(i * 2)) }
val zeroRes = clzi(5, c4(1), c4(0))
val zeroWRes = Mux(funcReg(1), c4(1), c4(0))
@ -77,35 +104,29 @@ class CountModule(implicit p: Parameters) extends XSModule {
val cpopRes = cpopLo32 +& cpopHi32
val cpopWRes = cpopLo32
io.out := Mux(funcReg(2), Mux(funcReg(0), cpopWRes, cpopRes), Mux(funcReg(0), zeroWRes, zeroRes))
io.out := Mux(
funcReg(2),
Mux(funcReg(0), cpopWRes, cpopRes),
Mux(funcReg(0), zeroWRes, zeroRes)
)
}
class ClmulModule(implicit p: Parameters) extends XSModule {
val io = IO(new Bundle() {
val src = Vec(2, Input(UInt(XLEN.W)))
val func = Input(UInt())
val regEnable = Input(Bool())
val out = Output(UInt(XLEN.W))
})
class ClmulModule(implicit p: Parameters) extends BkuSrcModule {
// stage 0
val (src1, src2) = (io.src(0), io.src(1))
val mul0 = Wire(Vec(64, UInt(128.W)))
val mul1 = Wire(Vec(32, UInt(128.W)))
val mul2 = Wire(Vec(16, UInt(128.W)))
(0 until XLEN) map { i =>
(0 until XLEN) foreach { i =>
mul0(i) := Mux(src1(i), if(i==0) src2 else Cat(src2, 0.U(i.W)), 0.U)
}
(0 until 32) map { i => mul1(i) := mul0(i*2) ^ mul0(i*2+1)}
(0 until 16) map { i => mul2(i) := mul1(i*2) ^ mul1(i*2+1)}
(0 until 32) foreach { i => mul1(i) := mul0(i * 2) ^ mul0(i * 2 + 1)}
(0 until 16) foreach { i => mul2(i) := mul1(i * 2) ^ mul1(i * 2 + 1)}
// pipeline registers
val funcReg = RegEnable(io.func, io.regEnable)
val mul3 = Reg(Vec(8, UInt(128.W)))
when (io.regEnable) {
(0 until 8) map { i => mul3(i) := mul2(i*2) ^ mul2(i*2+1)}
when (regEnable) {
(0 until 8) map { i => mul3(i) := mul2(i * 2) ^ mul2(i * 2 + 1)}
}
// stage 1
@ -122,81 +143,65 @@ class ClmulModule(implicit p: Parameters) extends XSModule {
))
}
class MiscModule(implicit p: Parameters) extends XSModule {
val io = IO(new Bundle() {
val src = Vec(2, Input(UInt(XLEN.W)))
val func = Input(UInt())
val regEnable = Input(Bool())
val out = Output(UInt(XLEN.W))
})
val (src1, src2) = (io.src(0), io.src(1))
class MiscModule(implicit p: Parameters) extends BkuSrcModule {
def xpermLUT(table: UInt, idx: UInt, width: Int) : UInt = {
// ParallelMux((0 until XLEN/width).map( i => i.U -> table(i)).map( x => (x._1 === idx, x._2)))
LookupTreeDefault(idx, 0.U(width.W), (0 until XLEN/width).map( i => i.U -> table(i*width+width-1, i*width)))
LookupTreeDefault(idx, 0.U(width.W), (0 until XLEN / width).map { i =>
i.U -> table(i * width + width - 1, i * width)
})
}
val xpermnVec = Wire(Vec(16, UInt(4.W)))
(0 until 16).map( i => xpermnVec(i) := xpermLUT(src1, src2(i*4+3, i*4), 4))
xpermnVec.zipWithIndex.foreach { case (sink, i) =>
sink := xpermLUT(src1, src2(i * 4 + 3, i * 4), 4)
}
val xpermn = Cat(xpermnVec.reverse)
val xpermbVec = Wire(Vec(8, UInt(8.W)))
(0 until 8).map( i => xpermbVec(i) := Mux(src2(i*8+7, i*8+3).orR, 0.U, xpermLUT(src1, src2(i*8+2, i*8), 8)))
xpermbVec.zipWithIndex.foreach { case (sink, i) =>
sink := Mux(src2(i * 8 + 7, i * 8 + 3).orR, 0.U, xpermLUT(src1, src2(i * 8 + 2, i * 8), 8))
}
val xpermb = Cat(xpermbVec.reverse)
io.out := RegEnable(Mux(io.func(0), xpermb, xpermn), io.regEnable)
io.out := RegEnable(Mux(func(0), xpermb, xpermn), regEnable)
}
class HashModule(implicit p: Parameters) extends XSModule {
val io = IO(new Bundle() {
val src = Input(UInt(XLEN.W))
val func = Input(UInt())
val regEnable = Input(Bool())
val out = Output(UInt(XLEN.W))
})
val src1 = io.src
val sha256sum0 = ROR32(src1, 2) ^ ROR32(src1, 13) ^ ROR32(src1, 22)
val sha256sum1 = ROR32(src1, 6) ^ ROR32(src1, 11) ^ ROR32(src1, 25)
val sha256sig0 = ROR32(src1, 7) ^ ROR32(src1, 18) ^ SHR32(src1, 3)
val sha256sig1 = ROR32(src1, 17) ^ ROR32(src1, 19) ^ SHR32(src1, 10)
val sha512sum0 = ROR64(src1, 28) ^ ROR64(src1, 34) ^ ROR64(src1, 39)
val sha512sum1 = ROR64(src1, 14) ^ ROR64(src1, 18) ^ ROR64(src1, 41)
val sha512sig0 = ROR64(src1, 1) ^ ROR64(src1, 8) ^ SHR64(src1, 7)
val sha512sig1 = ROR64(src1, 19) ^ ROR64(src1, 61) ^ SHR64(src1, 6)
class HashModule(implicit p: Parameters) extends BkuSrcModule {
val sha256sum0 = SHA2.sha256sum0(src1)
val sha256sum1 = SHA2.sha256sum1(src1)
val sha256sig0 = SHA2.sha256sig0(src1)
val sha256sig1 = SHA2.sha256sig1(src1)
val sha512sum0 = SHA2.sha512sum0(src1)
val sha512sum1 = SHA2.sha512sum1(src1)
val sha512sig0 = SHA2.sha512sig0(src1)
val sha512sig1 = SHA2.sha512sig1(src1)
val sm3p0 = ROR32(src1, 23) ^ ROR32(src1, 15) ^ src1
val sm3p1 = ROR32(src1, 9) ^ ROR32(src1, 17) ^ src1
val shaSource = VecInit(Seq(
SignExt(sha256sum0(31,0), XLEN),
SignExt(sha256sum1(31,0), XLEN),
SignExt(sha256sig0(31,0), XLEN),
SignExt(sha256sig1(31,0), XLEN),
require(XLEN == 64)
val shaSource = VecInit(
SignExt(sha256sum0, XLEN),
SignExt(sha256sum1, XLEN),
SignExt(sha256sig0, XLEN),
SignExt(sha256sig1, XLEN),
sha512sum0,
sha512sum1,
sha512sig0,
sha512sig1
))
val sha = shaSource(io.func(2,0))
val sm3 = Mux(io.func(0), SignExt(sm3p1(31,0), XLEN), SignExt(sm3p0(31,0), XLEN))
)
val sha = shaSource(func(2, 0))
val sm3 = Mux(
func(0),
SignExt(sm3p1(31, 0), XLEN),
SignExt(sm3p0(31, 0), XLEN)
)
io.out := RegEnable(Mux(io.func(3), sm3, sha), io.regEnable)
io.out := RegEnable(Mux(func(3), sm3, sha), regEnable)
}
class BlockCipherModule(implicit p: Parameters) extends XSModule {
val io = IO(new Bundle() {
val src = Vec(2, Input(UInt(XLEN.W)))
val func = Input(UInt())
val regEnable = Input(Bool())
val out = Output(UInt(XLEN.W))
})
val (src1, src2, func, funcReg) = (io.src(0), io.src(1), io.func, RegEnable(io.func, io.regEnable))
val src1Bytes = VecInit((0 until 8).map(i => src1(i*8+7, i*8)))
val src2Bytes = VecInit((0 until 8).map(i => src2(i*8+7, i*8)))
class BlockCipherModule(implicit p: Parameters) extends BkuSrcModule {
val src1Bytes = VecInit((0 until 8).map(i => src1(i * 8 + 7, i * 8)))
val src2Bytes = VecInit((0 until 8).map(i => src2(i * 8 + 7, i * 8)))
// AES
val aesSboxIn = ForwardShiftRows(src1Bytes, src2Bytes)
@ -208,14 +213,14 @@ class BlockCipherModule(implicit p: Parameters) extends XSModule {
val iaesSboxOut = Wire(Vec(8, UInt(8.W)))
aesSboxOut.zip(aesSboxMid).zip(aesSboxIn)foreach { case ((out, mid), in) =>
when (io.regEnable) {
when (regEnable) {
mid := SboxInv(SboxAesTop(in))
}
out := SboxAesOut(mid)
}
iaesSboxOut.zip(iaesSboxMid).zip(iaesSboxIn)foreach { case ((out, mid), in) =>
when (io.regEnable) {
when (regEnable) {
mid := SboxInv(SboxIaesTop(in))
}
out := SboxIaesOut(mid)
@ -224,7 +229,7 @@ class BlockCipherModule(implicit p: Parameters) extends XSModule {
val aes64es = aesSboxOut.asUInt
val aes64ds = iaesSboxOut.asUInt
val imMinIn = RegEnable(src1Bytes, io.regEnable)
val imMinIn = RegEnable(src1Bytes, regEnable)
val aes64esm = Cat(MixFwd(Seq(aesSboxOut(4), aesSboxOut(5), aesSboxOut(6), aesSboxOut(7))),
MixFwd(Seq(aesSboxOut(0), aesSboxOut(1), aesSboxOut(2), aesSboxOut(3))))
@ -234,29 +239,29 @@ class BlockCipherModule(implicit p: Parameters) extends XSModule {
MixInv(Seq(imMinIn(0), imMinIn(1), imMinIn(2), imMinIn(3))))
val rcon = WireInit(VecInit(Seq("h01".U, "h02".U, "h04".U, "h08".U,
"h10".U, "h20".U, "h40".U, "h80".U,
"h1b".U, "h36".U, "h00".U)))
val rcon = VecInit(0x01.U, 0x02.U, 0x04.U, 0x08.U,
0x10.U, 0x20.U, 0x40.U, 0x80.U,
0x1b.U, 0x36.U, 0x00.U)
val ksSboxIn = Wire(Vec(4, UInt(8.W)))
val ksSboxTop = Reg(Vec(4, Vec(21, Bool())))
val ksSboxOut = Wire(Vec(4, UInt(8.W)))
ksSboxIn(0) := Mux(src2(3,0) === "ha".U, src1Bytes(4), src1Bytes(5))
ksSboxIn(1) := Mux(src2(3,0) === "ha".U, src1Bytes(5), src1Bytes(6))
ksSboxIn(2) := Mux(src2(3,0) === "ha".U, src1Bytes(6), src1Bytes(7))
ksSboxIn(3) := Mux(src2(3,0) === "ha".U, src1Bytes(7), src1Bytes(4))
ksSboxIn(0) := Mux(src2(3, 0) === 0xa.U, src1Bytes(4), src1Bytes(5))
ksSboxIn(1) := Mux(src2(3, 0) === 0xa.U, src1Bytes(5), src1Bytes(6))
ksSboxIn(2) := Mux(src2(3, 0) === 0xa.U, src1Bytes(6), src1Bytes(7))
ksSboxIn(3) := Mux(src2(3, 0) === 0xa.U, src1Bytes(7), src1Bytes(4))
ksSboxOut.zip(ksSboxTop).zip(ksSboxIn).foreach{ case ((out, top), in) =>
when (io.regEnable) {
when (regEnable) {
top := SboxAesTop(in)
}
out := SboxAesOut(SboxInv(top))
}
val ks1Idx = RegEnable(src2(3,0), io.regEnable)
val ks1Idx = RegEnable(src2(3, 0), regEnable)
val aes64ks1i = Cat(ksSboxOut.asUInt ^ rcon(ks1Idx), ksSboxOut.asUInt ^ rcon(ks1Idx))
val aes64ks2Temp = src1(63,32) ^ src2(31,0)
val aes64ks2 = RegEnable(Cat(aes64ks2Temp ^ src2(63,32), aes64ks2Temp), io.regEnable)
val aes64ks2Temp = src1(63, 32) ^ src2(31, 0)
val aes64ks2 = RegEnable(Cat(aes64ks2Temp ^ src2(63, 32), aes64ks2Temp), regEnable)
val aesResult = LookupTreeDefault(funcReg, aes64es, List(
BKUOpType.aes64es -> aes64es,
@ -269,94 +274,65 @@ class BlockCipherModule(implicit p: Parameters) extends XSModule {
))
// SM4
val sm4SboxIn = src2Bytes(func(1,0))
val sm4SboxIn = src2Bytes(func(1, 0))
val sm4SboxTop = Reg(Vec(21, Bool()))
when (io.regEnable) {
when (regEnable) {
sm4SboxTop := SboxSm4Top(sm4SboxIn)
}
val sm4SboxOut = SboxSm4Out(SboxInv(sm4SboxTop))
val sm4ed = sm4SboxOut ^ (sm4SboxOut<<8) ^ (sm4SboxOut<<2) ^ (sm4SboxOut<<18) ^ ((sm4SboxOut&"h3f".U)<<26) ^ ((sm4SboxOut&"hc0".U)<<10)
val sm4ks = sm4SboxOut ^ ((sm4SboxOut&"h07".U)<<29) ^ ((sm4SboxOut&"hfe".U)<<7) ^ ((sm4SboxOut&"h01".U)<<23) ^ ((sm4SboxOut&"hf8".U)<<13)
val sm4Source = VecInit(Seq(
sm4ed(31,0),
Cat(sm4ed(23,0), sm4ed(31,24)),
Cat(sm4ed(15,0), sm4ed(31,16)),
Cat(sm4ed( 7,0), sm4ed(31,8)),
sm4ks(31,0),
Cat(sm4ks(23,0), sm4ks(31,24)),
Cat(sm4ks(15,0), sm4ks(31,16)),
Cat(sm4ks( 7,0), sm4ks(31,8))
))
val sm4Result = SignExt((sm4Source(funcReg(2,0)) ^ RegEnable(src1(31,0), io.regEnable))(31,0), XLEN)
val sm4ed = sm4SboxOut ^ (sm4SboxOut << 8).asUInt ^ (sm4SboxOut << 2).asUInt ^ (sm4SboxOut << 18).asUInt ^
((sm4SboxOut & 0x3f.U) << 26).asUInt ^ ((sm4SboxOut & 0xc0.U) << 10).asUInt
val sm4ks = sm4SboxOut ^ ((sm4SboxOut & 0x07.U) << 29).asUInt ^ ((sm4SboxOut & 0xfe.U) << 7).asUInt ^
((sm4SboxOut & 0x01.U) << 23).asUInt ^ ((sm4SboxOut & 0xf8.U) << 13).asUInt
val sm4Source = VecInit(
sm4ed(31, 0),
Cat(sm4ed(23, 0), sm4ed(31, 24)),
Cat(sm4ed(15, 0), sm4ed(31, 16)),
Cat(sm4ed( 7, 0), sm4ed(31, 8)),
sm4ks(31, 0),
Cat(sm4ks(23, 0), sm4ks(31, 24)),
Cat(sm4ks(15, 0), sm4ks(31, 16)),
Cat(sm4ks( 7, 0), sm4ks(31, 8))
)
val sm4Result = SignExt((sm4Source(funcReg(2, 0)) ^ RegEnable(src1(31, 0), regEnable))(31, 0), XLEN)
io.out := Mux(funcReg(3), sm4Result, aesResult)
}
class CryptoModule(implicit p: Parameters) extends XSModule {
val io = IO(new Bundle() {
val src = Vec(2, Input(UInt(XLEN.W)))
val func = Input(UInt())
val regEnable = Input(Bool())
val out = Output(UInt(XLEN.W))
})
val (src1, src2, func) = (io.src(0), io.src(1), io.func)
val funcReg = RegEnable(func, io.regEnable)
val hashModule = Module(new HashModule)
hashModule.io.src := src1
hashModule.io.func := func
hashModule.io.regEnable := io.regEnable
val blockCipherModule = Module(new BlockCipherModule)
blockCipherModule.io.src(0) := src1
blockCipherModule.io.src(1) := src2
blockCipherModule.io.func := func
blockCipherModule.io.regEnable := io.regEnable
io.out := Mux(funcReg(4), hashModule.io.out, blockCipherModule.io.out)
}
class Bku(cfg: FuConfig)(implicit p: Parameters) extends FuncUnit(cfg) with HasPipelineReg {
override def latency = 2
val (src1, src2, func) = (
io.in.bits.data.src(0),
io.in.bits.data.src(1),
io.in.bits.ctrl.fuOpType
)
val bkuSrcInput = Wire(new BkuSrcInput)
val src1 = io.in.bits.data.src(0)
val src2 = io.in.bits.data.src(1)
val func = io.in.bits.ctrl.fuOpType
val fire = io.in.fire
val funcReg = RegEnable(func, fire)
bkuSrcInput.connect(VecInit(src1, src2), func, fire, funcReg)
val countModule = Module(new CountModule)
countModule.io.src := src1
countModule.io.func := func
countModule.io.regEnable := regEnable(1)
val clmulModule = Module(new ClmulModule)
clmulModule.io.src(0) := src1
clmulModule.io.src(1) := src2
clmulModule.io.func := func
clmulModule.io.regEnable := regEnable(1)
val miscModule = Module(new MiscModule)
miscModule.io.src(0) := src1
miscModule.io.src(1) := src2
miscModule.io.func := func
miscModule.io.regEnable := regEnable(1)
val cryptoModule = Module(new CryptoModule)
cryptoModule.io.src(0) := src1
cryptoModule.io.src(1) := src2
cryptoModule.io.func := func
cryptoModule.io.regEnable := regEnable(1)
val hashModule = Module(new HashModule)
val blockCipherModule = Module(new BlockCipherModule)
countModule.io.in := bkuSrcInput
clmulModule.io.in := bkuSrcInput
miscModule.io.in := bkuSrcInput
hashModule.io.in := bkuSrcInput
blockCipherModule.io.in := bkuSrcInput
// CountModule, ClmulModule, MiscModule, and CryptoModule have a latency of 1 cycle
val funcReg = RegEnable(func, io.in.fire)
val result = Mux(funcReg(5), cryptoModule.io.out,
Mux(funcReg(3), countModule.io.out,
Mux(funcReg(2),miscModule.io.out, clmulModule.io.out)))
val result = Mux(
funcReg(5),
Mux(funcReg(4), hashModule.io.out, blockCipherModule.io.out),
Mux(
funcReg(3),
countModule.io.out,
Mux(funcReg(2), miscModule.io.out, clmulModule.io.out)
)
)
io.out.bits.res.data := RegEnable(result, regEnable(2))
// connectNonPipedCtrlSingal

72
src/main/scala/xiangshan/backend/fu/util/CryptoUtils.scala
View File

@ -21,24 +21,6 @@ import chisel3.util._
import xiangshan._
import org.chipsalliance.cde.config.Parameters
// 32bits shift right
object SHR32 {
def apply(bits: UInt, shamt: Int) = {
require(shamt>0 && shamt<32)
if(shamt == 31) Cat(0.U(63.W), bits(31))
else Cat(0.U((32+shamt).W), bits(31,shamt))
}
}
// 64bits shift right
object SHR64 {
def apply(bits: UInt, shamt: Int) = {
require(shamt>0 && shamt<64)
if(shamt == 63) Cat(bits(62,0), bits(63))
else Cat(0.U(shamt.W), bits(63,shamt))
}
}
// 32bits Rotate shift
object ROR32 {
def apply(bits: UInt, shamt: Int) = {
@ -457,3 +439,57 @@ object MixInv {
ByteDec(Seq(bytes(0), bytes(1), bytes(2), bytes(3))))
}
}
object SHA2 {
private val sha256sum0cfg: Seq[Int] = Seq( 2, 13, 22)
private val sha256sum1cfg: Seq[Int] = Seq( 6, 11, 25)
private val sha512sum0cfg: Seq[Int] = Seq(28, 34, 39)
private val sha512sum1cfg: Seq[Int] = Seq(14, 18, 41)
private val sha256sig0cfg: Seq[Int] = Seq( 7, 18, 3)
private val sha256sig1cfg: Seq[Int] = Seq(17, 19, 10)
private val sha512sig0cfg: Seq[Int] = Seq( 1, 8, 7)
private val sha512sig1cfg: Seq[Int] = Seq(19, 61, 6)
private def sum(x: UInt, sew: Int, n: Int): UInt = {
require(x.getWidth >= sew, s"Invalid width: ${x.getWidth}")
val src = x(sew - 1, 0)
val config = (sew, n) match {
case (32, 0) => sha256sum0cfg
case (32, 1) => sha256sum1cfg
case (64, 0) => sha512sum0cfg
case (64, 1) => sha512sum1cfg
case _ => throw new IllegalArgumentException("Invalid sew or N")
}
val result = Wire(UInt(sew.W))
result := config.map(cfg => src.rotateRight(cfg)).reduce(_ ^ _)
result
}
def sha256sum0(x: UInt): UInt = sum(x, 32, 0)
def sha256sum1(x: UInt): UInt = sum(x, 32, 1)
def sha512sum0(x: UInt): UInt = sum(x, 64, 0)
def sha512sum1(x: UInt): UInt = sum(x, 64, 1)
private def sig(x: UInt, sew: Int, n: Int): UInt = {
require(x.getWidth >= sew, s"Invalid width: ${x.getWidth}")
val src = x(sew - 1, 0)
val config = (sew, n) match {
case (32, 0) => sha256sig0cfg
case (32, 1) => sha256sig1cfg
case (64, 0) => sha512sig0cfg
case (64, 1) => sha512sig1cfg
case _ => throw new IllegalArgumentException("Invalid sew or N")
}
val result = Wire(UInt(sew.W))
result := src.rotateRight(config(0)) ^ src.rotateRight(config(1)) ^ (src >> config(2)).asUInt
result
}
def sha256sig0(x: UInt): UInt = sig(x, 32, 0)
def sha256sig1(x: UInt): UInt = sig(x, 32, 1)
def sha512sig0(x: UInt): UInt = sig(x, 64, 0)
def sha512sig1(x: UInt): UInt = sig(x, 64, 1)
}