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fix(ResetGen): sync 3 cycles by default (#4733)

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Tang Haojin 2025-05-26 18:36:51 +08:00 committed by GitHub
parent 872d75c4d4
commit 1a5f716e97
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GPG Key ID: B5690EEEBB952194
4 changed files with 9 additions and 9 deletions
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2
huancun

@ -1 +1 @@
Subproject commit c5e02bd61625fd53ad2410999ff7d57a61234230
Subproject commit 7c9d4cbb2a6d315c701e81c2acf0a5ab9d9af5e4

8
src/main/scala/top/XSNoCTop.scala
View File

@ -167,8 +167,8 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc
// imsic bare io
val imsic = wrapper.u_imsic_bus_top.module.msi.map(x => IO(chiselTypeOf(x)))
val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen(2, io.dft_reset) })
val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen(2, io.dft_reset) }
val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(noc_clock, noc_reset) { ResetGen(io.dft_reset) })
val soc_reset_sync = withClockAndReset(soc_clock, soc_reset) { ResetGen(io.dft_reset) }
wrapper.core_with_l2.module.io.dft.zip(io.dft).foreach { case (a, b) => a := b }
wrapper.core_with_l2.module.io.dft_reset.zip(io.dft_reset).foreach { case (a, b) => a := b }
// device clock and reset
@ -197,7 +197,7 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc
2. SoC initialize reset during Power on/off flow
*/
val cpuReset = reset.asBool || !soc_rst_n
val cpuReset_sync = withClockAndReset(clock, cpuReset.asAsyncReset)(ResetGen(2, io.dft_reset))
val cpuReset_sync = withClockAndReset(clock, cpuReset.asAsyncReset)(ResetGen(io.dft_reset))
//Interrupt sources collect
val msip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(clint.head(0), 3, 0)}
val mtip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(clint.head(1), 3, 0)}
@ -205,7 +205,7 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc
val seip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(plic.last(0), 3, 0)}
val nmi_31 = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(nmi.head(0), 3, 0)}
val nmi_43 = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(nmi.head(1), 3, 0)}
val debugIntr = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(debug.head(0),3,0)}
val debugIntr = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(debug.head(0), 3, 0)}
val msi_info_vld = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(core_with_l2.module.io.msiInfo.valid, 3, 0)}
val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, debugIntr, msi_info_vld)

6
src/main/scala/xiangshan/XSTileWrap.scala
View File

@ -101,9 +101,9 @@ class XSTileWrap()(implicit p: Parameters) extends LazyModule
val iso_en = Option.when(EnablePowerDown) (Input (Bool()))
})
val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen(2, io.dft_reset))
val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen(2, io.dft_reset)))
val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen(2, io.dft_reset))
val reset_sync = withClockAndReset(clock, (reset.asBool || io.hartResetReq).asAsyncReset)(ResetGen(io.dft_reset))
val noc_reset_sync = EnableCHIAsyncBridge.map(_ => withClockAndReset(clock, noc_reset.get)(ResetGen(io.dft_reset)))
val soc_reset_sync = withClockAndReset(clock, soc_reset)(ResetGen(io.dft_reset))
// override LazyRawModuleImp's clock and reset
childClock := clock

2
utility

@ -1 +1 @@
Subproject commit 0113cfce3fbd1131281ebad048971dbac47b61a0
Subproject commit 8ef84f12393af527dfd1dc073549fa336332eff1