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device,AXI4RAM: move assignments of rvalid and bvalid to AXI4Slave

This commit is contained in:
Zihao Yu 2019-03-03 16:53:04 +08:00
parent e68f8385f3
commit 3735f2f62f
2 changed files with 3 additions and 3 deletions
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3
src/main/scala/device/AXI4RAM.scala
View File

@ -20,9 +20,6 @@ class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4,
when (in.w.fire()) {
mem.write(index(waddr) + writeBeatCnt, wdata, in.w.bits.strb.toBools)
}
in.b.valid := BoolStopWatch(in.w.fire() && wLast, in.b.fire(), startHighPriority = true)
val ren = in.ar.fire() || (in.r.fire() && !rLast)
in.r.bits.data := RegEnable(Cat(mem.read(index(raddr) + readBeatCnt).reverse), ren)
in.r.valid := BoolStopWatch(ren && (in.ar.fire() || r_busy), in.r.fire(), startHighPriority = true)
}

3
src/main/scala/device/AXI4Slave.scala
View File

@ -31,6 +31,8 @@ abstract class AXI4SlaveModule[T <: AXI4Lite](_type :T = new AXI4) extends Modul
val r_busy = BoolStopWatch(in.ar.fire(), in.r.fire() && rLast, startHighPriority = true)
in.ar.ready := in.r.ready || !r_busy
in.r.bits.resp := AXI4Parameters.RESP_OKAY
val ren = in.ar.fire() || (in.r.fire() && !rLast)
in.r.valid := BoolStopWatch(ren && (in.ar.fire() || r_busy), in.r.fire(), startHighPriority = true)
val waddr = Wire(UInt())
@ -53,6 +55,7 @@ abstract class AXI4SlaveModule[T <: AXI4Lite](_type :T = new AXI4) extends Modul
in.aw.ready := !w_busy
in. w.ready := in.aw.valid || (w_busy)
in.b.bits.resp := AXI4Parameters.RESP_OKAY
in.b.valid := BoolStopWatch(in.w.fire() && wLast, in.b.fire(), startHighPriority = true)
in match {
case axi4: AXI4 =>