fix(resolve): flush entries that have been redirected by backend (#5085)

Meta of entries that have been redirected by backend may be overwritten
by BPU already while they remain in resolve queue. In this case, FTQ
will send BPU wrong meta.

src/main/scala/xiangshan/frontend/ftq/Bundles.scala

@@ -37,6 +37,7 @@ class MetaEntry(implicit p: Parameters) extends FtqBundle {
 
 class ResolveEntry(implicit p: Parameters) extends FtqBundle {
   val ftqIdx:     FtqPtr     = new FtqPtr
+  val flushed:    Bool       = Bool()
   val startVAddr: PrunedAddr = PrunedAddr(VAddrBits)
   // TODO: Reconsider branch number
   val branches: Vec[Valid[BranchInfo]] = Vec(ResolveEntryBranchNumber, Valid(new BranchInfo))

src/main/scala/xiangshan/frontend/ftq/Ftq.scala

@@ -23,6 +23,7 @@ package xiangshan.frontend.ftq
 import chisel3._
 import chisel3.util._
 import org.chipsalliance.cde.config.Parameters
+import utility.DelayN
 import utility.HasCircularQueuePtrHelper
 import utility.HasPerfEvents
 import utility.ParallelPriorityMux
@@ -290,15 +291,19 @@ class Ftq(implicit p: Parameters) extends FtqModule
   io.toBpu.redirect.bits.speculationMeta := speculationQueue(redirect.bits.ftqIdx.value)
   io.toBpu.redirectFromIFU               := ifuRedirect.valid
 
+  resolveQueue.io.backendRedirect    := DelayN(backendRedirect.valid, 2)
+  resolveQueue.io.backendRedirectPtr := DelayN(backendRedirect.bits.ftqIdx, 2)
+
   // --------------------------------------------------------------------------------
   // Resolve and train BPU
   // --------------------------------------------------------------------------------
+
   resolveQueue.io.backendResolve := io.fromBackend.resolve
 
-  metaQueue.io.ren   := resolveQueue.io.bpuTrain.valid
+  metaQueue.io.ren   := resolveQueue.io.bpuTrain.valid && !resolveQueue.io.bpuTrain.bits.flushed
   metaQueue.io.raddr := resolveQueue.io.bpuTrain.bits.ftqIdx.value
 
-  io.toBpu.train.valid           := RegNext(resolveQueue.io.bpuTrain.valid)
+  io.toBpu.train.valid           := RegNext(resolveQueue.io.bpuTrain.valid && !resolveQueue.io.bpuTrain.bits.flushed)
   io.toBpu.train.bits.meta       := metaQueue.io.rdata.meta
   io.toBpu.train.bits.startVAddr := RegEnable(resolveQueue.io.bpuTrain.bits.startVAddr, resolveQueue.io.bpuTrain.valid)
   io.toBpu.train.bits.branches   := RegEnable(resolveQueue.io.bpuTrain.bits.branches, resolveQueue.io.bpuTrain.valid)

src/main/scala/xiangshan/frontend/ftq/ResolveQueue.scala

@@ -25,8 +25,10 @@ import xiangshan.frontend.bpu.HalfAlignHelper
 class ResolveQueue(implicit p: Parameters) extends FtqModule with HalfAlignHelper {
 
   class ResolveQueueIO extends Bundle {
-    val backendResolve: Vec[Valid[Resolve]] = Input(Vec(backendParams.BrhCnt, Valid(new Resolve)))
-    val bpuTrain:       Valid[ResolveEntry] = Output(Valid(new ResolveEntry))
+    val backendResolve:     Vec[Valid[Resolve]] = Input(Vec(backendParams.BrhCnt, Valid(new Resolve)))
+    val backendRedirect:    Bool                = Input(Bool())
+    val backendRedirectPtr: FtqPtr              = Input(new FtqPtr)
+    val bpuTrain:           Valid[ResolveEntry] = Output(Valid(new ResolveEntry))
   }
 
   val io: ResolveQueueIO = IO(new ResolveQueueIO)
@@ -79,6 +81,10 @@ class ResolveQueue(implicit p: Parameters) extends FtqModule with HalfAlignHelpe
     }
   }
 
+  when(io.backendRedirect) {
+    mem.foreach(entry => entry.bits.flushed := entry.bits.ftqIdx > io.backendRedirectPtr)
+  }
+
   private val deqValid = mem(deqPtr.value).valid && !io.backendResolve.map(branch =>
     branch.valid && branch.bits.ftqIdx === mem(deqPtr.value).bits.ftqIdx
   ).reduce(_ || _)
@@ -89,7 +95,8 @@ class ResolveQueue(implicit p: Parameters) extends FtqModule with HalfAlignHelpe
   when(deqValid) {
     deqPtr := deqPtr + 1.U
 
-    mem(deqPtr.value).valid := false.B
+    mem(deqPtr.value).valid        := false.B
+    mem(deqPtr.value).bits.flushed := false.B
     mem(deqPtr.value).bits.branches.foreach(_.valid := false.B)
   }