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fix(VSegmentUnit): adjust the fullva bit width of the tlb req (#4892)
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This commit is contained in:
Anzo 2025-07-29 16:03:46 +08:00 committed by GitHub
parent 2cf64d6d43
commit 71802692d9
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1 changed files with 6 additions and 6 deletions
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12
src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala
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@ -428,12 +428,12 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule
val vaddr = nextBaseVaddr + realSegmentOffset
val misalignLowVaddr = Cat(latchVaddr(latchVaddr.getWidth - 1, 3), 0.U(3.W))
val misalignLowVaddrDup = Cat(latchVaddrDup(latchVaddrDup.getWidth - 1, 3), 0.U(3.W))
val misalignHighVaddr = Cat(latchVaddr(latchVaddr.getWidth - 1, 3) + 1.U, 0.U(3.W))
val misalignHighVaddrDup = Cat(latchVaddrDup(latchVaddrDup.getWidth - 1, 3) + 1.U, 0.U(3.W))
val notCross16ByteVaddr = Cat(latchVaddr(latchVaddr.getWidth - 1, 4), 0.U(4.W))
val notCross16ByteVaddrDup = Cat(latchVaddrDup(latchVaddrDup.getWidth - 1, 4), 0.U(4.W))
val misalignLowVaddr = Cat(latchVaddr(VAddrBits - 1, 3), 0.U(3.W))
val misalignLowVaddrDup = Cat(latchVaddrDup(VAddrBits - 1, 3), 0.U(3.W))
val misalignHighVaddr = Cat(latchVaddr(VAddrBits - 1, 3) + 1.U, 0.U(3.W))
val misalignHighVaddrDup = Cat(latchVaddrDup(VAddrBits - 1, 3) + 1.U, 0.U(3.W))
val notCross16ByteVaddr = Cat(latchVaddr(VAddrBits - 1, 4), 0.U(4.W))
val notCross16ByteVaddrDup = Cat(latchVaddrDup(VAddrBits - 1, 4), 0.U(4.W))
// val misalignVaddr = Mux(notCross16ByteReg, notCross16ByteVaddr, Mux(isFirstSplit, misalignLowVaddr, misalignHighVaddr))
val misalignVaddr = Mux(isFirstSplit, misalignLowVaddr, misalignHighVaddr)
val misalignVaddrDup = Mux(isFirstSplit, misalignLowVaddrDup, misalignHighVaddrDup)