refactor(XSNoCTop): Inherit XSNoCDiffTop from XSNoCTop instead composite (#4709)

Use inherit instead of composite to reduce redundant IO port definitions
and connections. At the same time, we are able to keep the original
module name `XSTop` unchanged.

Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>

.github/workflows/emu.yml

@@ -99,7 +99,7 @@ jobs:
         run: |
           cd $GITHUB_WORKSPACE
           python3 ./difftest/scripts/st_tools/interface.py ./difftest/build/rtl/GatewayEndpoint.sv
-          python3 ./difftest/scripts/st_tools/interface.py ./build/rtl/XSDiffTop.sv --core --filelist ./build/rtl/filelist.f --simtop ./difftest/build/rtl/SimTop.sv
+          python3 ./difftest/scripts/st_tools/interface.py ./build/rtl/XSTop.sv --core --filelist ./build/rtl/filelist.f --simtop ./difftest/build/rtl/SimTop.sv
           cp -r -v ./difftest/build/* ./build/
           verilator --lint-only -Wno-fatal --top-module XSDiffTopChecker build/XSDiffTopChecker.sv build/rtl/*sv build/rtl/*v -Ibuild/generated-src/ -LDFLAGS -"lreadline"
 

src/main/scala/top/Top.scala

@@ -500,7 +500,8 @@ object TopMain extends App {
   ChiselDB.init(enableChiselDB && !envInFPGA)
 
   if (config(SoCParamsKey).UseXSNoCDiffTop) {
-    Generator.execute(firrtlOpts, DisableMonitors(p => new XSNoCDiffTop()(p))(config), firtoolOpts)
+    val soc = DisableMonitors(p => LazyModule(new XSNoCDiffTop()(p)))(config)
+    Generator.execute(firrtlOpts, soc.module, firtoolOpts)
   } else if (config(SoCParamsKey).UseXSTileDiffTop) {
     Generator.execute(firrtlOpts, DisableMonitors(p => new XSTileDiffTop()(p))(config), firtoolOpts)
   } else {

src/main/scala/top/XSNoCTop.scala

@@ -342,50 +342,26 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc
   lazy val module = new XSNoCTopImp(this)
 }
 
-class XSNoCDiffTop(implicit p: Parameters) extends Module {
-  override val desiredName: String = "XSDiffTop"
-  val l_soc = LazyModule(new XSNoCTop())
-  val soc = Module(l_soc.module)
+class XSNoCDiffTop(implicit p: Parameters) extends XSNoCTop
+{
+  class XSNoCDiffTopImp(wrapper: XSNoCTop) extends XSNoCTopImp(wrapper) {
+    // TODO:
+    // XSDiffTop is only part of DUT, we can not instantiate difftest here.
+    // Temporarily we collect Performance counters for each DiffTop, need control signals passed from Difftest
+    val timer = IO(Input(UInt(64.W)))
+    val logEnable = IO(Input(Bool()))
+    val clean = IO(Input(Bool()))
+    val dump = IO(Input(Bool()))
 
-  // Expose XSTop IOs outside, i.e. io
-  def exposeIO(data: Data, name: String): Unit = {
-    val dummy = IO(chiselTypeOf(data)).suggestName(name)
-    dummy <> data
-  }
-  def exposeOptionIO(data: Option[Data], name: String): Unit = {
-    if (data.isDefined) {
-      val dummy = IO(chiselTypeOf(data.get)).suggestName(name)
-      dummy <> data.get
+    withClockAndReset(clock, cpuReset_sync) {
+      XSLog.collect(timer, logEnable, clean, dump)
     }
+    DifftestWiring.createAndConnectExtraIOs()
+    Profile.generateJson("XiangShan")
+    XSNoCDiffTopChecker()
   }
-  exposeIO(l_soc.clint, "clint")
-  exposeIO(l_soc.debug, "debug")
-  exposeIO(l_soc.plic, "plic")
-  exposeIO(l_soc.beu, "beu")
-  exposeIO(l_soc.nmi, "nmi")
-  soc.clock := clock
-  soc.reset := reset.asAsyncReset
-  exposeIO(soc.soc_clock, "soc_clock")
-  exposeIO(soc.soc_reset, "soc_reset")
-  exposeIO(soc.io, "io")
-  exposeOptionIO(soc.noc_clock, "noc_clock")
-  exposeOptionIO(soc.noc_reset, "noc_reset")
-  exposeOptionIO(soc.imsic_axi4, "imsic_axi4")
-  exposeOptionIO(soc.imsic_m_tl, "imsic_m_tl")
-  exposeOptionIO(soc.imsic_s_tl, "imsic_s_tl")
-  exposeOptionIO(soc.imsic, "imsic")
 
-  // TODO:
-  // XSDiffTop is only part of DUT, we can not instantiate difftest here.
-  // Temporarily we collect Performance counters for each DiffTop, need control signals passed from Difftest
-  val timer = IO(Input(UInt(64.W)))
-  val logEnable = IO(Input(Bool()))
-  val clean = IO(Input(Bool()))
-  val dump = IO(Input(Bool()))
-  XSLog.collect(timer, logEnable, clean, dump)
-  DifftestWiring.createAndConnectExtraIOs()
-  Profile.generateJson("XiangShan")
-  XSNoCDiffTopChecker()
+  override lazy val module = new XSNoCDiffTopImp(this)
 }
 
 // TODO:
@@ -420,7 +396,7 @@ object XSNoCDiffTopChecker {
         |    for (i = 0; i < `CONFIG_XSCORE_NR; i = i+1)
         |    begin: u_CPU_TOP
         |    // FIXME: add missing ports
-        |    XSDiffTop u_XSTop (
+        |    XSTop u_XSTop (
         |        .clock                   (cpu_clk),
         |        .noc_clock               (sys_clk),
         |        .soc_clock               (sys_clk),