build: bump chisel 6.7.0 (#5069)

build.sc

@@ -39,12 +39,12 @@ val defaultScalaVersion = "2.13.15"
 val pwd = os.Path(sys.env("MILL_WORKSPACE_ROOT"))
 
 def defaultVersions = Map(
-  "chisel"        -> ivy"org.chipsalliance::chisel:6.6.0",
-  "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:6.6.0",
+  "chisel"        -> ivy"org.chipsalliance::chisel:6.7.0",
+  "chisel-plugin" -> ivy"org.chipsalliance:::chisel-plugin:6.7.0",
   "chiseltest"    -> ivy"edu.berkeley.cs::chiseltest:6.0.0"
 )
 /* resolve firtool dependency */
-import $ivy.`org.chipsalliance::chisel:6.6.0`
+import $ivy.`org.chipsalliance::chisel:6.7.0`
 import $ivy.`org.chipsalliance::firtool-resolver:1.3.0`
 
 trait HasChisel extends SbtModule {

coupledL2

@@ -1 +1 @@
-Subproject commit 5a610b42f3e6f10ceb23fa73ca98439071e7d41d
+Subproject commit abf2f7467f6b5666d2c3a6578ba8277cd7304696

huancun

@@ -1 +1 @@
-Subproject commit 7c9d4cbb2a6d315c701e81c2acf0a5ab9d9af5e4
+Subproject commit 65ef077373ecf398b4cecdea06b65ef9b8d79044

openLLC

@@ -1 +1 @@
-Subproject commit e41f5393d30f169ee2f142c429843a0c59062ef6
+Subproject commit 9e6f78209b2f215fb9f6a8f0de250995ff3ab63d

rocket-chip

@@ -1 +1 @@
-Subproject commit bcf2051a45fcd6c4b84a62a679888c2dae75cce4
+Subproject commit 46f1efefa1ff431bffe3262e4830bc50316842f4

src/main/scala/device/standalone/StandAloneDevice.scala

@@ -18,7 +18,7 @@ package device.standalone
 
 import chisel3._
 import chisel3.util._
-import chisel3.experimental.{annotate, ChiselAnnotation}
+import chisel3.experimental.annotate
 import chisel3.experimental.dataview._
 import freechips.rocketchip.diplomacy._
 import org.chipsalliance.cde.config.Parameters
@@ -149,18 +149,14 @@ abstract class StandAloneDevice (
 class StandAloneDeviceImp(outer: StandAloneDevice)(implicit p: Parameters) extends LazyModuleImp(outer) with RequireAsyncReset {
   p(SoCParamsKey).XSTopPrefix.foreach { prefix =>
     val mod = this.toNamed
-    annotate(new ChiselAnnotation {
-      def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
-    })
+    annotate(this)(Seq(NestedPrefixModulesAnnotation(mod, prefix, true)))
   }
 }
 
 class StandAloneDeviceRawImp(outer: StandAloneDevice)(implicit p: Parameters) extends LazyRawModuleImp(outer) {
   p(SoCParamsKey).XSTopPrefix.foreach { prefix =>
     val mod = this.toNamed
-    annotate(new ChiselAnnotation {
-      def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
-    })
+    annotate(this)(Seq(NestedPrefixModulesAnnotation(mod, prefix, true)))
   }
 }
 

src/main/scala/top/Top.scala

@@ -42,7 +42,7 @@ import freechips.rocketchip.tilelink._
 import freechips.rocketchip.interrupts._
 import freechips.rocketchip.amba.axi4._
 import freechips.rocketchip.jtag.JTAGIO
-import chisel3.experimental.{annotate, ChiselAnnotation}
+import chisel3.experimental.annotate
 import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
 import scala.collection.mutable.{Map}
 
@@ -244,9 +244,7 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc()
   {
     soc.XSTopPrefix.foreach { prefix =>
       val mod = this.toNamed
-      annotate(new ChiselAnnotation {
-        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
-      })
+      annotate(this)(Seq(NestedPrefixModulesAnnotation(mod, prefix, true)))
     }
 
     val dma = socMisc.map(m => IO(Flipped(new VerilogAXI4Record(m.dma.elts.head.params))))

src/main/scala/top/XSNoCTop.scala

@@ -35,7 +35,7 @@ import freechips.rocketchip.tilelink._
 import coupledL2.tl2chi.{CHIAsyncBridgeSink, PortIO}
 import freechips.rocketchip.tile.MaxHartIdBits
 import freechips.rocketchip.util.{AsyncQueueParams, AsyncQueueSource}
-import chisel3.experimental.{ChiselAnnotation, annotate}
+import chisel3.experimental.annotate
 import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
 import freechips.rocketchip.util.AsyncResetSynchronizerShiftReg
 
@@ -48,9 +48,7 @@ abstract class BaseXSSocImp(wrapper: BaseXSSoc) extends LazyRawModuleImp(wrapper
 
   socParams.soc.XSTopPrefix.foreach { prefix =>
     val mod = this.toNamed
-    annotate(new ChiselAnnotation {
-      def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
-    })
+    annotate(this)(Seq(NestedPrefixModulesAnnotation(mod, prefix, true)))
   }
 
   val clock = IO(Input(Clock()))

src/main/scala/xiangshan/backend/fu/vector/Mgtu.scala

@@ -21,9 +21,6 @@ package xiangshan.backend.fu.vector
 import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
-import chiseltest._
-import org.scalatest.flatspec.AnyFlatSpec
-import org.scalatest.matchers.must.Matchers
 import top.{ArgParser, BaseConfig, DefaultConfig}
 import xiangshan._
 import xiangshan.backend.fu.vector.Bundles.{Vl}

src/main/scala/xiangshan/cache/mmu/TLB.scala

@@ -28,7 +28,6 @@ import org.chipsalliance.cde.config.Parameters
 import chisel3._
 import chisel3.util._
 import difftest._
-import freechips.rocketchip.util.SRAMAnnotation
 import xiangshan._
 import utils._
 import utility._

utility

@@ -1 +1 @@
-Subproject commit 40180f69c2256f228ca9949f19179f550031d5db
+Subproject commit c8d424348b0a058753116558c3d7066dba375f17

yunsuan

@@ -1 +1 @@
-Subproject commit cadd3c2f43096e253d61296b33ac697be8354e29
+Subproject commit 955921186e34bb8915806582a238181a6dc3435c