Merge branch 'master' into br_sync_lowpower
This commit is contained in:
zhaohong1988
GitHub
commit
90dbd0cb5b
|
|
@ -6,22 +6,22 @@
|
|||
url = https://github.com/OpenXiangShan/difftest.git
|
||||
[submodule "ready-to-run"]
|
||||
path = ready-to-run
|
||||
url = https://github.com/OpenXiangShan/ready-to-run
|
||||
url = https://github.com/OpenXiangShan/ready-to-run.git
|
||||
[submodule "huancun"]
|
||||
path = huancun
|
||||
url = https://github.com/OpenXiangshan/huancun.git
|
||||
url = https://github.com/OpenXiangShan/HuanCun.git
|
||||
[submodule "fudian"]
|
||||
path = fudian
|
||||
url = https://github.com/OpenXiangShan/fudian.git
|
||||
[submodule "utility"]
|
||||
path = utility
|
||||
url = https://github.com/OpenXiangShan/utility
|
||||
url = https://github.com/OpenXiangShan/Utility.git
|
||||
[submodule "yunsuan"]
|
||||
path = yunsuan
|
||||
url = https://github.com/OpenXiangShan/YunSuan.git
|
||||
[submodule "coupledL2"]
|
||||
path = coupledL2
|
||||
url = https://github.com/OpenXiangShan/coupledL2
|
||||
url = https://github.com/OpenXiangShan/CoupledL2.git
|
||||
[submodule "openLLC"]
|
||||
path = openLLC
|
||||
url = https://github.com/OpenXiangShan/OpenLLC.git
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
Subproject commit 6608dc16ec944800d39200e2fad5924d0968b42b
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||||
Subproject commit eacee874c515eadfe197cd6b66a52799c30332c1
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||||
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|
@ -1 +1 @@
|
|||
Subproject commit 75d8aeb40e5302a1c2e7c517eb07e4e6f8a2efac
|
||||
Subproject commit 2b60fc5edf50f519a4310dc41620e9a204b4aacb
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@ -71,38 +71,38 @@
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|||
<!-- always add a space after `//` or `/*` before comments -->
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||||
<check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
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||||
<!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
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||||
<check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
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||||
<parameters>
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||||
<!-- (, ~, ! -->
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||||
<parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
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||||
</parameters>
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||||
</check>
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||||
<check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
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||||
<parameters>
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||||
<!-- :, ,, ) -->
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<parameter name="tokens">COLON, COMMA, RPAREN</parameter>
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||||
</parameters>
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||||
</check>
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||||
<check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
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||||
<parameters>
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||||
<!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
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||||
<parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
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</parameters>
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||||
</check>
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||||
<check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
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||||
<parameters>
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||||
<!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
|
||||
<parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
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||||
</parameters>
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||||
</check>
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||||
<check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
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||||
<parameters>
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||||
<!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
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<parameter name="regex"><]]></parameter>
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</parameters>
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||||
<customMessage>No space before operators</customMessage>
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||||
</check>
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||||
<check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
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<check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
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||||
<parameters>
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||||
<!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
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||||
<parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>
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||||
|
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@ -71,43 +71,43 @@
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|||
<!-- always add a space after `//` or `/*` before comments -->
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||||
<check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
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||||
<!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
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||||
<check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
|
||||
<parameters>
|
||||
<!-- (, ~, ! -->
|
||||
<parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
|
||||
</parameters>
|
||||
</check>
|
||||
<check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
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||||
<parameters>
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||||
<!-- :, ,, ) -->
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||||
<parameter name="tokens">COLON, COMMA, RPAREN</parameter>
|
||||
</parameters>
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||||
</check>
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||||
<check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
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||||
<check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
|
||||
<parameters>
|
||||
<!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
|
||||
<parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
|
||||
</parameters>
|
||||
</check>
|
||||
<check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
|
||||
<check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
|
||||
<parameters>
|
||||
<!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
|
||||
<parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
|
||||
</parameters>
|
||||
</check>
|
||||
<check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
|
||||
<check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
|
||||
<parameters>
|
||||
<!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
|
||||
<parameter name="regex"><]]></parameter>
|
||||
</parameters>
|
||||
<customMessage>No space before operators</customMessage>
|
||||
</check>
|
||||
<check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
|
||||
<check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
|
||||
<parameters>
|
||||
<!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
|
||||
<parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ ]]]></parameter>
|
||||
<parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>
|
||||
</parameters>
|
||||
<customMessage>No space after operators</customMessage>
|
||||
<customMessage>No space or newline after operators</customMessage>
|
||||
</check>
|
||||
|
||||
<!-- ===== imports ===== -->
|
||||
|
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@ -158,7 +158,7 @@
|
|||
<!-- pure lower cases for package names -->
|
||||
<check enabled="true" class="org.scalastyle.scalariform.PackageNamesChecker" level="warning">
|
||||
<parameters>
|
||||
<parameter name="regex">^[a-z]*$</parameter>
|
||||
<parameter name="regex">^[a-z0-9]*$</parameter>
|
||||
</parameters>
|
||||
</check>
|
||||
|
||||
|
|
|
|||
|
|
@ -214,7 +214,6 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
|
|||
val cpuReset = reset.asBool || !soc_rst_n
|
||||
val cpuReset_sync = withClockAndReset(clock, cpuReset)(ResetGen(2, io.dft_reset))
|
||||
//Interrupt sources collect
|
||||
|
||||
val msip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(clint.head(0), 3, 0)}
|
||||
val mtip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(clint.head(1), 3, 0)}
|
||||
val meip = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(plic.head(0), 3, 0)}
|
||||
|
|
@ -223,7 +222,6 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
|
|||
val nmi_43 = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(nmi.head(1), 3, 0)}
|
||||
val msi_info_vld = withClockAndReset(clock, cpuReset_sync) {AsyncResetSynchronizerShiftReg(core_with_l2.module.io.msiInfo.valid, 3, 0)}
|
||||
val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, msi_info_vld)
|
||||
|
||||
/*
|
||||
* CPU Low Power State:
|
||||
* 1. core+L2 Low power state transactions is triggered by l2 flush request from core CSR
|
||||
|
|
|
|||
|
|
@ -150,6 +150,6 @@ class TrapHandleIO extends Bundle {
|
|||
val causeNO = new CauseBundle
|
||||
val dbltrpToMN = Bool()
|
||||
val hasDTExcp = Bool()
|
||||
val pcFromXtvec = UInt()
|
||||
val pcFromXtvec = UInt(64.W)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -206,8 +206,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
|
|||
private val inst = Wire(Vec(RenameWidth, new XSInstBitFields))
|
||||
private val isCsr = Wire(Vec(RenameWidth, Bool()))
|
||||
private val isCsrr = Wire(Vec(RenameWidth, Bool()))
|
||||
private val isWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
|
||||
private val isBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
|
||||
private val isNotWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
|
||||
private val isNotBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
|
||||
private val fuType = uops.map(_.fuType)
|
||||
private val fuOpType = uops.map(_.fuOpType)
|
||||
private val vtype = uops.map(_.vpu.vtype)
|
||||
|
|
@ -291,9 +291,9 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
|
|||
inst(i) := uops(i).instr.asTypeOf(new XSInstBitFields)
|
||||
isCsr(i) := inst(i).OPCODE5Bit === OPCODE5Bit.SYSTEM && inst(i).FUNCT3(1, 0) =/= 0.U
|
||||
isCsrr(i) := isCsr(i) && inst(i).FUNCT3 === BitPat("b?1?") && inst(i).RS1 === 0.U
|
||||
isWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
|
||||
isNotWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
|
||||
inst(i).CSRIDX, true.B, CSROoORead.waitForwardInOrderCsrReadList.map(_.U -> false.B))
|
||||
isBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
|
||||
isNotBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
|
||||
inst(i).CSRIDX, true.B, CSROoORead.blockBackwardInOrderCsrReadList.map(_.U -> false.B))
|
||||
|
||||
/*
|
||||
|
|
@ -303,8 +303,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
|
|||
*
|
||||
* Signal "isCsrr" contains not only "CSRR", but also other CSR instructions that do not require writing to CSR.
|
||||
*/
|
||||
uops(i).waitForward := io.in(i).bits.waitForward && !isWaitForwardCsrr(i)
|
||||
uops(i).blockBackward := io.in(i).bits.blockBackward && !isBlockBackwardCsrr(i)
|
||||
uops(i).waitForward := io.in(i).bits.waitForward && !isNotWaitForwardCsrr(i)
|
||||
uops(i).blockBackward := io.in(i).bits.blockBackward && !isNotBlockBackwardCsrr(i)
|
||||
|
||||
// update cf according to ssit result
|
||||
uops(i).storeSetHit := io.ssit(i).valid
|
||||
|
|
|
|||
|
|
@ -378,11 +378,9 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
|
|||
val s1_need_replacement = s1_req.miss && !s1_tag_match
|
||||
val s1_need_eviction = s1_req.miss && !s1_tag_match && s1_repl_coh.state =/= ClientStates.Nothing
|
||||
|
||||
val s1_way_en = Mux(
|
||||
RegEnable(io.pseudo_error.valid, false.B, s0_fire),
|
||||
Mux(ParallelORR(s1_real_tag_match_way), s1_real_tag_match_way, s1_repl_way_en),
|
||||
Mux(s1_need_replacement, s1_repl_way_en, s1_real_tag_match_way)
|
||||
)
|
||||
val s1_no_error_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_real_tag_match_way)
|
||||
val s1_error_way_en = Mux(ParallelORR(s1_real_tag_match_way), s1_real_tag_match_way, s1_repl_way_en)
|
||||
val s1_way_en = Mux(io.pseudo_error.valid, s1_error_way_en, s1_no_error_way_en)
|
||||
assert(!RegNext(s1_fire && PopCount(s1_way_en) > 1.U))
|
||||
|
||||
val s1_tag = s1_hit_tag
|
||||
|
|
@ -413,7 +411,6 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
|
|||
val s2_need_tag = RegEnable(s1_need_tag, s1_fire)
|
||||
val s2_idx = get_idx(s2_req.vaddr)
|
||||
|
||||
|
||||
val s2_way_en = RegEnable(s1_way_en, s1_fire)
|
||||
val s2_tag = Mux(s2_need_replacement, s2_repl_tag, RegEnable(s1_tag, s1_fire))
|
||||
val s2_coh = Mux(s2_need_replacement, s2_repl_coh, RegEnable(s1_coh, s1_fire))
|
||||
|
|
@ -427,8 +424,10 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
|
|||
|
||||
val s2_hit = s2_tag_match && s2_has_permission
|
||||
val s2_sc = s2_req.cmd === M_XSC
|
||||
val s2_lr = s2_req.cmd === M_XLR
|
||||
val s2_amo_hit = s2_hit && !s2_req.probe && !s2_req.miss && s2_req.isAMO
|
||||
val s2_store_hit = s2_hit && !s2_req.probe && !s2_req.miss && s2_req.isStore
|
||||
val s2_should_not_report_ecc_error = !s2_req.miss && (s2_req.isAMO && !s2_lr || s2_req.isStore)
|
||||
|
||||
if(EnableTagEcc) {
|
||||
s2_tag_error := s2_tag_errors.orR && s2_need_tag
|
||||
|
|
@ -978,7 +977,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
|
|||
s.s1.bits.way_en := s1_way_en
|
||||
s.s2.valid := s2_valid && !RegEnable(s1_req.replace, s1_fire)
|
||||
s.s2.bits.set := RegEnable(get_idx(s1_req.vaddr), s1_fire)
|
||||
s.s2.bits.way_en := RegEnable(s1_way_en, s1_fire)
|
||||
s.s2.bits.way_en := s2_way_en
|
||||
s.s3.valid := s3_valid && !RegEnable(s2_req.replace, s2_fire_to_s3)
|
||||
s.s3.bits.set := RegEnable(get_idx(s2_req.vaddr), s2_fire_to_s3)
|
||||
s.s3.bits.way_en := RegEnable(s2_way_en, s2_fire_to_s3)
|
||||
|
|
@ -995,7 +994,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
|
|||
// report error to beu and csr, 1 cycle after read data resp
|
||||
io.error := 0.U.asTypeOf(ValidIO(new L1CacheErrorInfo))
|
||||
// report error, update error csr
|
||||
io.error.valid := s3_error && GatedValidRegNext(s2_fire && !(s2_req.isAMO || s2_req.isStore))
|
||||
io.error.valid := s3_error && GatedValidRegNext(s2_fire && !s2_should_not_report_ecc_error)
|
||||
// only tag_error and data_error will be reported to beu
|
||||
// l2_error should not be reported (l2 will report that)
|
||||
io.error.bits.report_to_beu := (s3_tag_error || s3_data_error) && RegNext(s2_fire)
|
||||
|
|
|
|||
|
|
@ -244,7 +244,15 @@ class PTW()(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
|
|||
|
||||
io.req.ready := idle
|
||||
val ptw_resp = Wire(new PtwMergeResp)
|
||||
ptw_resp.apply(Mux(pte_valid, pageFault && !accessFault, false.B), (accessFault || ppn_af) && !(pte_valid && (pageFault || guestFault)), Mux(accessFault, af_level, Mux(guestFault, gpf_level, level)), Mux(pte_valid, pte, fake_pte), vpn, satp.asid, hgatp.vmid, vpn(sectortlbwidth - 1, 0), not_super = false, not_merge = false, bitmap_checkfailed.asBool)
|
||||
// pageFault is always valid when pte_valid
|
||||
val resp_pf = pte_valid && pageFault
|
||||
// when (pte_valid && (pageFault || guestFault), should not report accessFault or ppn_af
|
||||
val resp_af = (accessFault || ppn_af) && !((pte_valid && pageFault) || guestFault)
|
||||
// should use af_level when accessFault && !((pte_valid && pageFault) || guestFault)
|
||||
val resp_level = Mux(accessFault && resp_af, af_level, Mux(guestFault, gpf_level, level))
|
||||
// when ptw do not really send a memory request, should use fake_pte
|
||||
val resp_pte = Mux(pte_valid, pte, fake_pte)
|
||||
ptw_resp.apply(resp_pf, resp_af, resp_level, resp_pte, vpn, satp.asid, hgatp.vmid, vpn(sectortlbwidth - 1, 0), not_super = false, not_merge = false, bitmap_checkfailed.asBool)
|
||||
|
||||
val normal_resp = idle === false.B && mem_addr_update && !need_last_s2xlate && (guestFault || (w_mem_resp && find_pte) || (s_pmp_check && accessFault) || onlyS2xlate )
|
||||
val stageHit_resp = idle === false.B && hptw_resp_stage2
|
||||
|
|
@ -773,17 +781,28 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
|
|||
val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id)))
|
||||
val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) && !io.mem.flush_latch(io.mem.resp.bits.id) // dup with the entry that data coming next cycle
|
||||
val to_wait = Cat(dup_vec_wait).orR || dup_req_fire
|
||||
val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && !bitmap_enable
|
||||
val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && bitmap_enable
|
||||
val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
|
||||
else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
|
||||
val to_hptw_req = io.in.bits.req_info.s2xlate === allStage
|
||||
val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage
|
||||
|
||||
val last_hptw_req_id = io.mem.resp.bits.id
|
||||
val req_paddr = MakeAddr(io.in.bits.ppn(ppnLen-1, 0), getVpnn(io.in.bits.req_info.vpn, 0))
|
||||
val req_hpaddr = MakeAddr(entries(last_hptw_req_id).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(io.in.bits.req_info.vpn, 0))
|
||||
val index = Mux(entries(last_hptw_req_id).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8))
|
||||
val last_hptw_req_ppn = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index).getPPN()
|
||||
val last_hptw_req_pte = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index)
|
||||
val last_hptw_req_ppn = Mux(last_hptw_req_pte.n === 0.U, last_hptw_req_pte.getPPN(), Cat(last_hptw_req_pte.getPPN()(ptePPNLen - 1, pteNapotBits), io.in.bits.req_info.vpn(pteNapotBits - 1, 0)))
|
||||
// in `to_last_hptw_req`, we have already judged whether s2xlate === allStage
|
||||
val last_hptw_vsStagePf = last_hptw_req_pte.isPf(0.U, io.csr.hPBMTE) || !last_hptw_req_pte.isLeaf()
|
||||
val last_hptw_gStagePf = last_hptw_req_pte.isStage1Gpf(io.csr.hgatp.mode) && !last_hptw_vsStagePf
|
||||
|
||||
// noS2xlate || onlyStage1 || allStage but exception; do not need Stage2 translate
|
||||
val noStage2 = ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) ||
|
||||
(entries(io.mem.resp.bits.id).req_info.s2xlate === allStage && (last_hptw_vsStagePf || last_hptw_gStagePf))
|
||||
val to_mem_out = dup_wait_resp && noStage2 && !bitmap_enable
|
||||
val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && noStage2 && bitmap_enable
|
||||
val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
|
||||
else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
|
||||
val to_hptw_req = io.in.bits.req_info.s2xlate === allStage
|
||||
val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage && !(last_hptw_vsStagePf || last_hptw_gStagePf)
|
||||
val last_hptw_excp = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage && (last_hptw_vsStagePf || last_hptw_gStagePf)
|
||||
|
||||
XSError(RegNext(dup_req_fire && Cat(dup_vec_wait).orR, init = false.B), "mem req but some entries already waiting, should not happed")
|
||||
|
||||
XSError(io.in.fire && ((to_mem_out && to_cache) || (to_wait && to_cache)), "llptw enq, to cache conflict with to mem")
|
||||
|
|
@ -803,7 +822,7 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
|
|||
// so 2 + FilterSize is enough to avoid dead-lock
|
||||
state(enq_ptr) := enq_state
|
||||
entries(enq_ptr).req_info := io.in.bits.req_info
|
||||
entries(enq_ptr).ppn := Mux(to_last_hptw_req, last_hptw_req_ppn, io.in.bits.ppn)
|
||||
entries(enq_ptr).ppn := Mux(to_last_hptw_req || last_hptw_excp, last_hptw_req_ppn, io.in.bits.ppn)
|
||||
entries(enq_ptr).wait_id := Mux(to_wait, wait_id, enq_ptr)
|
||||
entries(enq_ptr).af := false.B
|
||||
if (HasBitmapCheck) {
|
||||
|
|
@ -817,6 +836,7 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
|
|||
entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs
|
||||
}
|
||||
entries(enq_ptr).hptw_resp := Mux(to_last_hptw_req, entries(last_hptw_req_id).hptw_resp, Mux(to_wait, entries(wait_id).hptw_resp, entries(enq_ptr).hptw_resp))
|
||||
entries(enq_ptr).hptw_resp.gpf := Mux(last_hptw_excp, last_hptw_gStagePf, false.B)
|
||||
entries(enq_ptr).first_s2xlate_fault := false.B
|
||||
mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req
|
||||
}
|
||||
|
|
@ -954,7 +974,9 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
|
|||
entries(i).hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || check_g_perm_fail
|
||||
entries(i).first_s2xlate_fault := io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf
|
||||
}.otherwise{ // change the entry that is waiting hptw resp
|
||||
val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting && dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn))
|
||||
val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting &&
|
||||
dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn) &&
|
||||
entries(i).req_info.s2xlate === entries(io.hptw.resp.bits.id).req_info.s2xlate)
|
||||
val waiting_index = ParallelMux(need_to_waiting_vec zip entries.map(_.wait_id))
|
||||
state(i) := Mux(Cat(need_to_waiting_vec).orR, state_mem_waiting, state_addr_check)
|
||||
entries(i).hptw_resp := io.hptw.resp.bits.h_resp
|
||||
|
|
|
|||
|
|
@ -572,10 +572,12 @@ class TLB(Width: Int, nRespDups: Int = 1, Block: Seq[Boolean], q: TLBParameters)
|
|||
val s2xlate = io.ptw.resp.bits.s2xlate
|
||||
resp(idx).valid := true.B
|
||||
resp(idx).bits.miss := false.B
|
||||
val s1_paddr = Cat(stage1.genPPN(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr))
|
||||
val s2_paddr = Cat(stage2.genPPNS2(get_pn(req_out(idx).vaddr)), get_off(req_out(idx).vaddr))
|
||||
val s1_ppn = stage1.genPPN(get_pn(req_out(idx).vaddr))(ppnLen - 1, 0)
|
||||
val s2_ppn = stage2.genPPNS2(get_pn(req_out(idx).vaddr))(ppnLen - 1, 0)
|
||||
val s1_paddr = Cat(s1_ppn, get_off(req_out(idx).vaddr))
|
||||
val s2_paddr = Cat(s2_ppn, get_off(req_out(idx).vaddr))
|
||||
for (d <- 0 until nRespDups) {
|
||||
resp(idx).bits.paddr(d) := Mux(s2xlate =/= noS2xlate, s2_paddr, s1_paddr)
|
||||
resp(idx).bits.paddr(d) := Mux(s2xlate === onlyStage2 || s2xlate === allStage, s2_paddr, s1_paddr)
|
||||
resp(idx).bits.gpaddr(d) := s1_paddr
|
||||
pbmt_check(idx, d, io.ptw.resp.bits.s1.entry.pbmt, io.ptw.resp.bits.s2.entry.pbmt, s2xlate)
|
||||
perm_check(stage1, req_out(idx).cmd, idx, d, stage2, req_out(idx).hlvx, s2xlate)
|
||||
|
|
|
|||
|
|
@ -300,7 +300,7 @@ class LoadQueue(implicit p: Parameters) extends XSModule
|
|||
for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) {
|
||||
// from load_s3
|
||||
val ldinBits = io.ldu.ldin(w).bits
|
||||
buff.valid := io.ldu.ldin(w).valid && (ldinBits.nc || ldinBits.mmio) && !ldinBits.rep_info.need_rep && !ldinBits.nc_with_data
|
||||
buff.valid := io.ldu.ldin(w).valid && !ldinBits.nc_with_data
|
||||
buff.bits := ldinBits
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -939,6 +939,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
|
|||
val cboZeroFlushSb = GatedRegNext(cboZeroToSb)
|
||||
|
||||
val cboZeroUop = RegEnable(PriorityMux(isCboZeroToSbVec, deqPtrExt.map(x=>uop(x.value))), cboZeroToSb)
|
||||
val cboZeroSqIdx = RegEnable(PriorityMux(isCboZeroToSbVec, deqPtrExt), cboZeroToSb)
|
||||
val cboZeroValid = RegInit(false.B)
|
||||
val cboZeroWaitFlushSb = RegInit(false.B)
|
||||
|
||||
|
|
@ -1014,6 +1015,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
|
|||
// cbo Zero writeback to ROB
|
||||
io.cboZeroStout.valid := cboZeroValid && !cboZeroWaitFlushSb
|
||||
io.cboZeroStout.bits.uop := cboZeroUop
|
||||
io.cboZeroStout.bits.uop.sqIdx := cboZeroSqIdx
|
||||
io.cboZeroStout.bits.data := DontCare
|
||||
io.cboZeroStout.bits.isFromLoadUnit := DontCare
|
||||
io.cboZeroStout.bits.debug.isMMIO := false.B
|
||||
|
|
|
|||
|
|
@ -1650,7 +1650,7 @@ class LoadUnit(implicit p: Parameters) extends XSModule
|
|||
io.lsq.ldin.bits.uop := s3_out.bits.uop
|
||||
// io.lsq.ldin.bits.uop.exceptionVec(loadAddrMisaligned) := Mux(s3_in.onlyMisalignException, false.B, s3_in.uop.exceptionVec(loadAddrMisaligned))
|
||||
|
||||
val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep || s3_mis_align
|
||||
val s3_revoke = s3_exception || io.lsq.ldin.bits.rep_info.need_rep || s3_mis_align || (s3_frm_mabuf && io.misalign_ldout.bits.rep_info.need_rep)
|
||||
io.lsq.ldld_nuke_query.revoke := s3_revoke
|
||||
io.lsq.stld_nuke_query.revoke := s3_revoke
|
||||
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule
|
|||
val s0_rob_idx = Mux(s0_use_non_prf_flow, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx))
|
||||
val s0_pc = Mux(s0_use_non_prf_flow, s0_uop.pc, 0.U)
|
||||
val s0_instr_type = Mux(s0_use_non_prf_flow, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U)
|
||||
val s0_wlineflag = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B)
|
||||
val s0_wlineflag = Mux(s0_use_flow_rs, LSUOpType.isCboAll(s0_uop.fuOpType), false.B)
|
||||
val s0_out = Wire(new LsPipelineBundle)
|
||||
val s0_kill = s0_uop.robIdx.needFlush(io.redirect)
|
||||
val s0_can_go = s1_ready
|
||||
|
|
|
|||
Loading…
Reference in New Issue