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fix(FTB, FTQ): dont use CPL2 SplittedSRAM (#4485)
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If the frontend directly uses the SplittedSRAM of coupledL2, the
frontend's SRAM will be marked as a multi-cycle path, the same as
coupledL2's SRAM.
This commit is contained in:
HuSipeng 2025-04-03 10:52:06 +08:00 committed by GitHub
parent 602aa9f1a8
commit 93b51ff08d
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2 changed files with 6 additions and 8 deletions
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7
src/main/scala/xiangshan/frontend/FTB.scala
View File

@ -18,12 +18,11 @@ package xiangshan.frontend
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import coupledL2.utils.SplittedSRAM
import org.chipsalliance.cde.config.Parameters import org.chipsalliance.cde.config.Parameters
import scala.{Tuple2 => &} import scala.{Tuple2 => &}
import utility._ import utility._
import utility.mbist.MbistPipeline import utility.mbist.MbistPipeline
import utility.sram.SRAMTemplate import utility.sram.SplittedSRAMTemplate
import xiangshan._ import xiangshan._
trait FTBParams extends HasXSParameter with HasBPUConst { trait FTBParams extends HasXSParameter with HasBPUConst {
@ -494,7 +493,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
}) })
// Extract holdRead logic to fix bug that update read override predict read result // Extract holdRead logic to fix bug that update read override predict read result
val ftb = Module(new SplittedSRAM( val ftb = Module(new SplittedSRAMTemplate(
new FTBEntryWithTag, new FTBEntryWithTag,
set = numSets, set = numSets,
way = numWays, way = numWays,
@ -502,7 +501,7 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU
shouldReset = true, shouldReset = true,
holdRead = false, holdRead = false,
singlePort = true, singlePort = true,
clockGated = true, withClockGate = true,
hasMbist = hasMbist hasMbist = hasMbist
)) ))
private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeFtb", hasMbist) private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "MbistPipeFtb", hasMbist)

7
src/main/scala/xiangshan/frontend/NewFtq.scala
View File

@ -26,12 +26,11 @@ package xiangshan.frontend
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import coupledL2.utils.SplittedSRAM
import org.chipsalliance.cde.config.Parameters import org.chipsalliance.cde.config.Parameters
import utility._ import utility._
import utility.ChiselDB import utility.ChiselDB
import utility.mbist.MbistPipeline import utility.mbist.MbistPipeline
import utility.sram.SRAMTemplate import utility.sram.SplittedSRAMTemplate
import utils._ import utils._
import xiangshan._ import xiangshan._
import xiangshan.backend.CtrlToFtqIO import xiangshan.backend.CtrlToFtqIO
@ -78,13 +77,13 @@ class FtqNRSRAM[T <: Data](gen: T, numRead: Int)(implicit p: Parameters) extends
}) })
for (i <- 0 until numRead) { for (i <- 0 until numRead) {
val sram = Module(new SplittedSRAM( val sram = Module(new SplittedSRAMTemplate(
gen, gen,
set = FtqSize, set = FtqSize,
way = 1, way = 1,
dataSplit = 2, dataSplit = 2,
singlePort = false, singlePort = false,
clockGated = true, withClockGate = true,
hasMbist = hasMbist hasMbist = hasMbist
)) ))
sram.io.r.req.valid := io.ren(i) sram.io.r.req.valid := io.ren(i)