fix(pma): fix pmaAddr regOut and rdata (#4936)

src/main/scala/xiangshan/backend/fu/NewCSR/CSRPMA.scala

@@ -30,7 +30,8 @@ trait CSRPMA { self: NewCSR =>
   val pmaaddr: Seq[CSRModule[_]] = Range(0, p(PMParameKey).NumPMA).map(num =>
     Module(new CSRModule(s"Pmaaddr$num") with HasPMAAddrSink {
       // read condition
-      regOut := addrRData(num)
+      regOut := addrRegOut(num)
+      rdata := addrRData(num)
     })
       .setAddr(CSRConst.PmaaddrBase + num)
   )
@@ -77,6 +78,7 @@ trait HasPMACfgRSink { self: CSRModule[_] =>
 
 trait HasPMAAddrSink { self: CSRModule[_] =>
   val addrRData = IO(Input(Vec(p(PMParameKey).NumPMA, UInt(64.W))))
+  val addrRegOut = IO(Input(Vec(p(PMParameKey).NumPMA, UInt(64.W))))
 }
 
 trait PMAInit extends HasPMParameters with PMAReadWrite {

src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala

@@ -690,6 +690,7 @@ class NewCSR(implicit val p: Parameters) extends Module
     mod match {
       case m: HasPMAAddrSink =>
         m.addrRData := pmaEntryMod.io.out.pmaAddrRData
+        m.addrRegOut := pmaEntryMod.io.out.pmaAddrRegOut
       case _ =>
     }
     mod match {

src/main/scala/xiangshan/backend/fu/NewCSR/PMAEntryModule.scala

@@ -92,6 +92,7 @@ class PMAEntryHandleModule(implicit p: Parameters) extends PMAModule with PMAIni
   }
 
   io.out.pmaAddrRData := pmaAddrR
+  io.out.pmaAddrRegOut := pmaAddr
 
 }
 
@@ -107,6 +108,7 @@ class PMAEntryHandleIOBundle(implicit p: Parameters) extends PMABundle {
   val out = Output(new Bundle {
     val pmaCfgWdata = UInt(PMXLEN.W)
     val pmaAddrRData = Vec(NumPMA, UInt(64.W))
+    val pmaAddrRegOut = Vec(NumPMA, UInt(64.W))
   })
 }