Makefile: `XSTOP_PREFIX` for nested prefix of `XSTop` (#2799)

* This does not work for chisel 3

Makefile

@@ -54,6 +54,12 @@ FPGA_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(FPGATOP):-o:$(@D)/$(@F).conf --ge
 SIM_MEM_ARGS = --infer-rw --repl-seq-mem -c:$(SIMTOP):-o:$(@D)/$(@F).conf --gen-mem-verilog full
 endif
 
+ifneq ($(XSTOP_PREFIX),)
+RELEASE_ARGS += --xstop-prefix $(XSTOP_PREFIX)
+DEBUG_ARGS += --xstop-prefix $(XSTOP_PREFIX)
+PLDM_ARGS += --xstop-prefix $(XSTOP_PREFIX)
+endif
+
 # co-simulation with DRAMsim3
 ifeq ($(WITH_DRAMSIM3),1)
 ifndef DRAMSIM3_HOME

src/main/scala/system/SoC.scala

@@ -45,7 +45,8 @@ case class SoCParameters
     level = 3,
     ways = 8,
     sets = 2048 // 1MB per bank
-  ))
+  )),
+  XSTopPrefix: Option[String] = None
 ){
   // L3 configurations
   val L3InnerBusWidth = 256

src/main/scala/top/ArgParser.scala

@@ -100,6 +100,10 @@ object ArgParser {
           nextOption(config.alter((site, here, up) => {
             case DebugOptionsKey => up(DebugOptionsKey).copy(EnablePerfDebug = false)
           }), tail)
+        case "--xstop-prefix" :: value :: tail if chisel3.BuildInfo.version != "3.6.0" =>
+          nextOption(config.alter((site, here, up) => {
+            case SoCParamsKey => up(SoCParamsKey).copy(XSTopPrefix = Some(value))
+          }), tail)
         case "--firtool-opt" :: option :: tail =>
           firtoolOpts ++= option.split(" ").filter(_.nonEmpty)
           nextOption(config, tail)

src/main/scala/top/Top.scala

@@ -29,6 +29,8 @@ import org.chipsalliance.cde.config._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.jtag.JTAGIO
+import chisel3.experimental.{annotate, ChiselAnnotation}
+import sifive.enterprise.firrtl.NestedPrefixModulesAnnotation
 
 abstract class BaseXSSoc()(implicit p: Parameters) extends LazyModule
   with BindingScope
@@ -138,6 +140,13 @@ class XSTop()(implicit p: Parameters) extends BaseXSSoc() with HasSoCParameter
   }
 
   class XSTopImp(wrapper: LazyModule) extends LazyRawModuleImp(wrapper) {
+    soc.XSTopPrefix.foreach { prefix =>
+      val mod = this.toNamed
+      annotate(new ChiselAnnotation {
+        def toFirrtl = NestedPrefixModulesAnnotation(mod, prefix, true)
+      })
+    }
+
     FileRegisters.add("dts", dts)
     FileRegisters.add("graphml", graphML)
     FileRegisters.add("json", json)

src/main/scala/xiangshan/transforms/NestedPrefixModulesAnnotation.scala

@@ -0,0 +1,12 @@
+// Hacked from CIRCT source code. Look like some SiFive internal annotations.
+package sifive.enterprise.firrtl
+
+import firrtl.annotations.{ModuleTarget, SingleTargetAnnotation}
+
+case class NestedPrefixModulesAnnotation(
+  target: ModuleTarget,
+  prefix: String,
+  inclusive: Boolean = false,
+) extends SingleTargetAnnotation[ModuleTarget] {
+  def duplicate(n: ModuleTarget): NestedPrefixModulesAnnotation = this.copy(n)
+}