feat: support parameterized addr width with `CHI_ADDR_WIDTH` (#4620)

By default, XiangShan uses a fixed 48-bit physical address width, which
is not configurable. However, some SoCs require support for different
address widths (e.g., CHI buses support 44-52-bit addressing). To
accommodate these SoC needs, this pr introduces a parameterized physical
address width configured via `CHI_ADDR_WIDTH`. Key notes:
1. `CHI_ADDR_WIDTH` only modifies the address width for interactions
between CoupledL2 and the CHI bus. Addresses within CoupledL2 and XSCore
remain 48-bit, incurring some area overhead but functionally correct.
2. If `CHI_ADDR_WIDTH` < 48, CoupledL2 truncates the upper bits of
addresses. As for snoops, truncated bits are treated as zero. Therefore
It is critical to configure PMA at compile time to prevent XiangShan
from generating address beyond the `CHI_ADDR_WIDTH`-defined address
space.

Makefile

@@ -106,6 +106,11 @@ ifeq ($(ENABLE_NS),1)
 COMMON_EXTRA_ARGS += --enable-ns
 endif
 
+# CHI physical address width
+ifneq ($(CHI_ADDR_WIDTH),)
+COMMON_EXTRA_ARGS += --chi-addr-width $(CHI_ADDR_WIDTH)
+endif
+
 # L2 cache size in KB
 ifneq ($(L2_CACHE_SIZE),)
 COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE)

openLLC

@@ -1 +1 @@
-Subproject commit 614ceb4c5d39d32e6ae786693a35da429ea32c12
+Subproject commit e41f5393d30f169ee2f142c429843a0c59062ef6

src/main/scala/top/ArgParser.scala

@@ -210,6 +210,10 @@ object ArgParser {
           nextOption(config.alter((site, here, up) => {
             case SoCParamsKey => up(SoCParamsKey).copy(SeperateDM = true)
           }), tail)
+        case "--chi-addr-width" :: value :: tail =>
+          nextOption(config.alter((site, here, up) => {
+            case coupledL2.tl2chi.CHIAddrWidthKey => value.toInt
+          }), tail)
         case "--wfi-resume" :: value :: tail =>
           nextOption(config.alter((site, here, up) => {
             case XSTileKey => up(XSTileKey).map(_.copy(wfiResume = value.toBoolean))

src/main/scala/xiangshan/L2Top.scala

@@ -27,7 +27,7 @@ import freechips.rocketchip.tile.{BusErrorUnit, BusErrorUnitParams, BusErrors, M
 import freechips.rocketchip.tilelink._
 import coupledL2.{EnableCHI, L2ParamKey, PrefetchCtrlFromCore}
 import coupledL2.tl2tl.TL2TLCoupledL2
-import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2}
+import coupledL2.tl2chi.{CHIIssue, PortIO, TL2CHICoupledL2, CHIAddrWidthKey, NonSecureKey}
 import huancun.BankBitsKey
 import system.HasSoCParameter
 import top.BusPerfMonitor
@@ -114,6 +114,8 @@ class L2TopInlined()(implicit p: Parameters) extends LazyModule
       )
       case EnableCHI => p(EnableCHI)
       case CHIIssue => p(CHIIssue)
+      case CHIAddrWidthKey => p(CHIAddrWidthKey)
+      case NonSecureKey => p(NonSecureKey)
       case BankBitsKey => log2Ceil(coreParams.L2NBanks)
       case MaxHartIdBits => p(MaxHartIdBits)
       case LogUtilsOptionsKey => p(LogUtilsOptionsKey)