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fix(LoadUnit, LSQ): fix report exception type for hardware error (#4619) 

* mmio or nc should report `Hardware Error` when response with `nderr`
* loadunit should report `Hardware Error` when it should be `delay kill`
from fast replay
This commit is contained in:
cz4e 2025-04-29 16:34:46 +08:00 committed by GitHub
parent e4651c49b8
commit bd1e467399
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GPG Key ID: B5690EEEBB952194
4 changed files with 7 additions and 6 deletions
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2
difftest

@ -1 +1 @@
Subproject commit 826fe99144a2abe97905177e86a20b5c445955ad
Subproject commit 1953acff26721e990086613e3b86cf4339122ca0

4
src/main/scala/xiangshan/mem/lsqueue/LoadQueueUncache.scala
View File

@ -213,7 +213,7 @@ class UncacheEntry(entryIndex: Int)(implicit p: Parameters) extends XSModule
io.ncOut.bits := DontCare
io.ncOut.bits.uop := selUop
io.ncOut.bits.uop.lqIdx := req.uop.lqIdx
io.ncOut.bits.uop.exceptionVec(loadAccessFault) := nderr
io.ncOut.bits.uop.exceptionVec(hardwareError) := nderr
io.ncOut.bits.data := rdataPartialLoad
io.ncOut.bits.paddr := req.paddr
io.ncOut.bits.vaddr := req.vaddr
@ -228,7 +228,7 @@ class UncacheEntry(entryIndex: Int)(implicit p: Parameters) extends XSModule
io.mmioOut.bits := DontCare
io.mmioOut.bits.uop := selUop
io.mmioOut.bits.uop.lqIdx := req.uop.lqIdx
io.mmioOut.bits.uop.exceptionVec(loadAccessFault) := nderr
io.mmioOut.bits.uop.exceptionVec(hardwareError) := nderr
io.mmioOut.bits.data := rdataPartialLoad
io.mmioOut.bits.debug.isMMIO := true.B
io.mmioOut.bits.debug.isNC := false.B

4
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
View File

@ -828,13 +828,13 @@ class StoreQueue(implicit p: Parameters) extends XSModule
mmioState := s_wb
when (io.uncache.resp.bits.nderr || io.cmoOpResp.bits.nderr) {
uncacheUop.exceptionVec(storeAccessFault) := true.B
uncacheUop.exceptionVec(hardwareError) := true.B
}
}
}
is(s_wb) {
when (io.mmioStout.fire || io.vecmmioStout.fire) {
when (uncacheUop.exceptionVec(storeAccessFault)) {
when (uncacheUop.exceptionVec(hardwareError)) {
mmioState := s_idle
}.otherwise {
mmioState := s_wait

3
src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala
View File

@ -1028,8 +1028,9 @@ class LoadUnit(implicit p: Parameters) extends XSModule
s1_out.uop.exceptionVec(loadPageFault) := false.B
s1_out.uop.exceptionVec(loadGuestPageFault) := false.B
s1_out.uop.exceptionVec(loadAddrMisaligned) := false.B
s1_out.uop.exceptionVec(loadAccessFault) := false.B
s1_out.uop.exceptionVec(hardwareError) := s1_dly_err && s1_vecActive
s1_out.isMisalign := false.B
s1_out.uop.exceptionVec(loadAccessFault) := s1_dly_err && s1_vecActive
}
// pointer chasing