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fix(MainPipe): fix mainpipe x state when miss request after miss request (#4856)
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Bugs description:
* there are two  miss requests: 1) MissA; 2) MissB
* MissA request write to sram sucessfully (chose a invalid entry, it
means that the data is `x`),
* MissB need replay (will not go to s3), hence MissB read `x` from sram
(it's data which MissA read)

How to fix:
* add a checker for a miss wether go to s3

Co-authored-by: Yacc <yacc@Yaccs-MacBook-Pro.local>
This commit is contained in:
cz4e 2025-07-03 10:23:26 +08:00 committed by GitHub
parent 9af254ae9e
commit c25dcc68df
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1 changed files with 1 additions and 1 deletions
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2
src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala vendored
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@ -587,7 +587,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
val s3_tag_error_wb = RegEnable(s2_tag_error, s2_fire_to_s3)
// data_error will be reported by data array 1 cycle after data read resp
val s3_data_error_beu = io.readline_error && RegEnable(s2_may_report_data_error, s2_fire)
val s3_data_error_beu = io.readline_error && GatedValidRegNext(s2_fire_to_s3) && RegEnable(s2_may_report_data_error, s2_fire)
val s3_data_error_wb = io.readline_error_delayed && RegEnable(s2_may_report_data_error, s2_fire_to_s3)
val s3_l2_error_beu = RegEnable(s2_l2_error, s2_fire)