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Merge f908c054a9 into f9ed852fb2

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Anzo 2025-04-22 10:01:00 +08:00 committed by GitHub
parent f9ed852fb2 f908c054a9
commit c45d6d5834
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1 changed files with 10 additions and 23 deletions
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33
src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
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@ -1132,35 +1132,22 @@ class StoreQueue(implicit p: Parameters) extends XSModule
// Vector instructions that prevent triggered exceptions from being written to the 'databuffer'.
val vecHasExceptionFlagValid = vecExceptionFlag.valid && isVec(ptr) && vecExceptionFlag.bits.robIdx === uop(ptr).robIdx
val misalignToDataBufferValid = allocated(rdataPtrExt(0).value) && committed(rdataPtrExt(0).value) &&
(!isVec(rdataPtrExt(0).value) && allvalid(rdataPtrExt(0).value) || vecMbCommit(rdataPtrExt(0).value)) &&
canDeqMisaligned && (!isCross4KPage || isCross4KPageCanDeq || hasException(rdataPtrExt(0).value))
// Only the first interface can write unaligned directives.
// Simplified design, even if the two ports have exceptions, but still only one unaligned dequeue.
val assert_flag = WireInit(false.B)
when(firstWithMisalign && firstWithCross16Byte) {
dataBuffer.io.enq(0).valid := canDeqMisaligned && allocated(rdataPtrExt(0).value) && committed(rdataPtrExt(0).value) &&
((!isVec(rdataPtrExt(0).value) && allvalid(rdataPtrExt(0).value) || vecMbCommit(rdataPtrExt(0).value)) &&
(!isCross4KPage || isCross4KPageCanDeq) || hasException(rdataPtrExt(0).value)) && !ncStall
dataBuffer.io.enq(1).valid := canDeqMisaligned && allocated(rdataPtrExt(0).value) && committed(rdataPtrExt(0).value) &&
(!isVec(rdataPtrExt(0).value) && allvalid(rdataPtrExt(0).value) || vecMbCommit(rdataPtrExt(0).value)) &&
(!isCross4KPage || isCross4KPageCanDeq) && !hasException(rdataPtrExt(0).value) && !ncStall
dataBuffer.io.enq(i).valid := misalignToDataBufferValid
assert_flag := dataBuffer.io.enq(1).valid
}.otherwise {
if (i == 0) {
dataBuffer.io.enq(i).valid := (
allocated(ptr) && committed(ptr)
&& ((!isVec(ptr) && (allvalid(ptr) || hasException(ptr))) || vecMbCommit(ptr))
&& !mmioStall && !ncStall
&& (!unaligned(ptr) || !cross16Byte(ptr) && (allvalid(ptr) || hasException(ptr)))
)
}
else {
dataBuffer.io.enq(i).valid := (
allocated(ptr) && committed(ptr)
&& ((!isVec(ptr) && (allvalid(ptr) || hasException(ptr))) || vecMbCommit(ptr))
&& !mmioStall && !ncStall
&& (!unaligned(ptr) || !cross16Byte(ptr) && (allvalid(ptr) || hasException(ptr)))
)
}
dataBuffer.io.enq(i).valid := (
allocated(ptr) && committed(ptr)
&& ((!isVec(ptr) && (allvalid(ptr) || hasException(ptr))) || vecMbCommit(ptr))
&& !mmioStall && !ncStall
&& (!unaligned(ptr) || !cross16Byte(ptr) && (allvalid(ptr) || hasException(ptr)))
)
}
val misalignAddrLow = vaddrModule.io.rdata(0)(2, 0)