root
/
XiangShan
mirror of https://github.com/OpenXiangShan/XiangShan.git
1
0
Fork 0
Code Issues Actions 2 Packages Projects Releases Wiki Activity

fix(rob): fix highDeqPtrMax from RobSize.U to (RobSize-1).U (#4690)

This commit is contained in:
xiaofeibao-xjtu 2025-05-16 19:16:20 +08:00 committed by GitHub
parent ef67ee21f0
commit ce863eb347
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/xiangshan/backend/rob/Rob.scala
View File

@ -208,7 +208,7 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
val bankNumWidth = log2Up(bankNum) val bankNumWidth = log2Up(bankNum)
val deqPtrWidth = deqPtr.value.getWidth val deqPtrWidth = deqPtr.value.getWidth
val highDeqPtrThisLine = deqPtr.value(deqPtrWidth - 1, bankNumWidth) val highDeqPtrThisLine = deqPtr.value(deqPtrWidth - 1, bankNumWidth)
val highDeqPtrMax = RobSize.U(deqPtrWidth - 1, bankNumWidth) val highDeqPtrMax = (RobSize - 1).U(deqPtrWidth - 1, bankNumWidth)
val highDeqPtrNextLine = Mux(highDeqPtrThisLine === highDeqPtrMax, 0.U, highDeqPtrThisLine + 1.U) val highDeqPtrNextLine = Mux(highDeqPtrThisLine === highDeqPtrMax, 0.U, highDeqPtrThisLine + 1.U)
val robIdxThisLine = VecInit((0 until bankNum).map(i => Cat(highDeqPtrThisLine, i.U(bankNumWidth.W)))) val robIdxThisLine = VecInit((0 until bankNum).map(i => Cat(highDeqPtrThisLine, i.U(bankNumWidth.W))))
val robIdxNextLine = VecInit((0 until bankNum).map(i => Cat(highDeqPtrNextLine, i.U(bankNumWidth.W)))) val robIdxNextLine = VecInit((0 until bankNum).map(i => Cat(highDeqPtrNextLine, i.U(bankNumWidth.W))))