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fix(CSR, NMI): fix the logic for clearing `nmip` (#4825)
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This commit is contained in:
Guanghui Cheng 2025-06-23 15:24:34 +08:00 committed by GitHub
parent f832341fbd
commit d569aba194
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GPG Key ID: B5690EEEBB952194
1 changed files with 5 additions and 4 deletions
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9
src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
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@ -392,10 +392,6 @@ class NewCSR(implicit val p: Parameters) extends Module
intrMod.io.in.fromAIA.meip := fromAIA.meip
intrMod.io.in.fromAIA.seip := fromAIA.seip
when(intrMod.io.out.nmi && intrMod.io.out.interruptVec.valid) {
nmip.NMI_31 := nmip.NMI_31 & !UIntToOH(intrMod.io.out.interruptVec.bits, 64)(NonMaskableIRNO.NMI_31)
nmip.NMI_43 := nmip.NMI_43 & !UIntToOH(intrMod.io.out.interruptVec.bits, 64)(NonMaskableIRNO.NMI_43)
}
val intrVec = RegEnable(intrMod.io.out.interruptVec.bits, 0.U, intrMod.io.out.interruptVec.valid)
val debug = RegEnable(intrMod.io.out.debug, false.B, intrMod.io.out.interruptVec.valid)
val nmi = RegEnable(intrMod.io.out.nmi, false.B, intrMod.io.out.interruptVec.valid)
@ -403,6 +399,11 @@ class NewCSR(implicit val p: Parameters) extends Module
val irToHS = RegEnable(intrMod.io.out.irToHS, false.B, intrMod.io.out.interruptVec.valid)
val irToVS = RegEnable(intrMod.io.out.irToVS, false.B, intrMod.io.out.interruptVec.valid)
when(hasTrap && trapIsInterrupt && nmi) {
nmip.NMI_31 := nmip.NMI_31 & !UIntToOH(intrVec, 64)(NonMaskableIRNO.NMI_31)
nmip.NMI_43 := nmip.NMI_43 & !UIntToOH(intrVec, 64)(NonMaskableIRNO.NMI_43)
}
val trapHandleMod = Module(new TrapHandleModule)
trapHandleMod.io.in.trapInfo.valid := hasTrap