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Merge 661b73089d into f9ed852fb2

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Zhaoyang You 2025-04-22 10:03:09 +08:00 committed by GitHub
parent f9ed852fb2 661b73089d
commit d9a36eaa7d
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2 changed files with 7 additions and 2 deletions
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4
src/main/scala/xiangshan/backend/fu/NewCSR/MachineLevel.scala
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@ -352,7 +352,9 @@ trait MachineLevel { self: NewCSR =>
}).setAddr(CSRs.mhpmcounter3 - 3 + num)
)
val mvendorid = Module(new CSRModule("Mvendorid") { rdata := 0.U })
val mvendorid = Module(new CSRModule("Mvendorid", new CSRBundle {
val ALL = RO(63, 0)
}))
.setAddr(CSRs.mvendorid)
// architecture id for XiangShan is 25

5
src/main/scala/xiangshan/backend/fu/NewCSR/NewCSR.scala
View File

@ -990,7 +990,10 @@ class NewCSR(implicit val p: Parameters) extends Module
}
})
private val regOut = Mux1H(csrOutMap.map { case (id, regOut) =>
private val rwMask = 0xc00
private val csrOutMapFilter = csrOutMap.filter { case (id, _) => (id & rwMask) != rwMask }
private val regOut = Mux1H(csrOutMapFilter.map { case (id, regOut) =>
if (vsMapS.contains(id)) {
((isModeVS && addr === vsMapS(id).U) || !isModeVS && addr === id.U) -> regOut
} else if (sMapVS.contains(id)) {