device,AXI4RAM: support burst write

src/main/scala/device/AXI4RAM.scala

@@ -17,9 +17,10 @@ class AXI4RAM[T <: AXI4Lite](_type: T = new AXI4,
   def index(addr: UInt) = addr >> log2Ceil(beatBytes)
 
   val wdata = VecInit.tabulate(beatBytes) { i => in.w.bits.data(8*(i+1)-1, 8*i) }
-  when (in.aw.fire()) {
-    mem.write(index(in.aw.bits.addr), wdata, in.w.bits.strb.toBools)
+  when (in.w.fire()) {
+    mem.write(index(waddr) + writeBeatCnt, wdata, in.w.bits.strb.toBools)
   }
+  in.b.valid := BoolStopWatch(in.w.fire() && wLast, in.b.fire(), startHighPriority = true)
 
   val ren = in.ar.fire() || (in.r.fire() && !rLast)
   in.r.bits.data := RegEnable(Cat(mem.read(index(raddr) + readBeatCnt).reverse), ren)

src/main/scala/device/AXI4Slave.scala

@@ -10,12 +10,6 @@ abstract class AXI4SlaveModule[T <: AXI4Lite](_type :T = new AXI4) extends Modul
   val io = IO(new Bundle{ val in = Flipped(_type) })
   val in = io.in
 
-  val w_full = BoolStopWatch(in.aw.fire(), in.b.fire(), startHighPriority = true)
-  in. b.valid := w_full
-  in.aw.ready := in. w.valid && (in.b.ready || !w_full)
-  in. w.ready := in.aw.valid && (in.b.ready || !w_full)
-  in.b.bits.resp := AXI4Parameters.RESP_OKAY
-
   val raddr = Wire(UInt())
   val (readBeatCnt, rLast) = in match {
     case axi4: AXI4 =>
@@ -38,6 +32,28 @@ abstract class AXI4SlaveModule[T <: AXI4Lite](_type :T = new AXI4) extends Modul
   in.ar.ready := in.r.ready || !r_busy
   in.r.bits.resp := AXI4Parameters.RESP_OKAY
 
+
+  val waddr = Wire(UInt())
+  val (writeBeatCnt, wLast) = in match {
+    case axi4: AXI4 =>
+      val c = Counter(256)
+      waddr := Mux(axi4.aw.fire(), axi4.aw.bits.addr, RegEnable(axi4.aw.bits.addr, axi4.aw.fire()))
+      when (axi4.w.fire()) {
+        c.inc()
+        when (axi4.w.bits.last) { c.value := 0.U }
+      }
+      (c.value, axi4.w.bits.last)
+
+    case axi4lite: AXI4Lite =>
+      waddr := axi4lite.aw.bits.addr
+      (0.U, true.B)
+  }
+
+  val w_busy = BoolStopWatch(in.aw.fire(), in.b.fire(), startHighPriority = true)
+  in.aw.ready := !w_busy
+  in. w.ready := in.aw.valid || (w_busy)
+  in.b.bits.resp := AXI4Parameters.RESP_OKAY
+
   in match {
     case axi4: AXI4 =>
       axi4.b.bits.id   := RegEnable(axi4.aw.bits.id, axi4.aw.fire())