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feat: mark topdown, cycle and instr as critical perf counters (#4431)
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This commit is contained in:
Tang Haojin 2025-03-18 16:01:04 +08:00 committed by GitHub
parent 7eb878b5ca
commit ef7a7f80bf
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2 changed files with 3 additions and 3 deletions
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2
src/main/scala/xiangshan/backend/dispatch/NewDispatch.scala
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@ -906,7 +906,7 @@ class NewDispatch(implicit p: Parameters) extends XSModule with HasPerfEvents wi
))
}
TopDownCounters.values.foreach(ctr => XSPerfAccumulate(ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U))))
TopDownCounters.values.foreach(ctr => XSPerfAccumulate(ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)), XSPerfLevel.CRITICAL))
val robTrueCommit = io.debugTopDown.fromRob.robTrueCommit
TopDownCounters.values.foreach(ctr => XSPerfRolling("td_"+ctr.toString(), PopCount(stallReason.map(_ === ctr.id.U)),

4
src/main/scala/xiangshan/backend/rob/Rob.scala
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@ -1297,10 +1297,10 @@ class RobImp(override val wrapper: Rob)(implicit p: Parameters, params: BackendP
def ifCommitReg(counter: UInt): UInt = Mux(isCommitReg, counter, 0.U)
val commitDebugUop = deqPtrVec.map(_.value).map(debug_microOp(_))
XSPerfAccumulate("clock_cycle", 1.U)
XSPerfAccumulate("clock_cycle", 1.U, XSPerfLevel.CRITICAL)
QueuePerf(RobSize, numValidEntries, numValidEntries === RobSize.U)
XSPerfAccumulate("commitUop", ifCommit(commitCnt))
XSPerfAccumulate("commitInstr", ifCommitReg(trueCommitCnt))
XSPerfAccumulate("commitInstr", ifCommitReg(trueCommitCnt), XSPerfLevel.CRITICAL)
XSPerfRolling("ipc", ifCommitReg(trueCommitCnt), 1000, clock, reset)
XSPerfRolling("cpi", perfCnt = 1.U /*Cycle*/ , eventTrigger = ifCommitReg(trueCommitCnt), granularity = 1000, clock, reset)
XSPerfAccumulate("commitInstrFused", ifCommitReg(fuseCommitCnt))