### 1. Purpose of this Pull Request
XSPdb is a specialized Python pdb-based debugging tool for RISC-V IP
cores, customized for Xiangshan's difftest interface. It provides
GDB-like interactive debugging capabilities, integrating: Terminal
command-line interface, RTL-level waveform toggling, Automated script
replay, System snapshot save/restore, Register initialization
configuration
### 2. Changes Made
* **New Tool (`XSPdb`)**: The core Python scripts for XSPdb have been
added under `scripts/xspdb/`. This tool provides an interactive
debugging console with standard pdb commands (e.g., breakpoints, step,
continue, register inspection).
* **Build System Integration**: A new Makefile, `pdb.mk`, has been
created to define the build targets and logic required for XSPdb.
* **Makefile Modification**: The root Makefile has been updated to
include `pdb.mk`, integrating the new `pdb` target into the main build
system.
### 3. Usage
The new tool can be built and used via a new `make` target.
1. **Build the XSPdb package**:
```bash
make pdb NOOP_HOME=$(pwd)
```
2. **Run a simulation with the XSPdb**:
```bash
make pdb-run NOOP_HOME=$(pwd)
```
---------
Co-authored-by: Zhicheng Yao <yaozhicheng@ict.ac.cn>
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Many variables in XiangShan Makefile can be overridden from command
line. Without forwarding these to docker, commands executed in the
container may produce unexpected results due to variable mismatches.
Signed-off-by: Jiuyue Ma <majiuyue@bosc.ac.cn>
PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py
How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface
This commit implements a basic nop-based Zawrs extension.
- `wrs.sto` in this commit acts as a nop instruction.
- `wrs.nto` in this commit acts as a nop instruction, except it:
- raises illegal instruction exception when !isModeM && mstatus.TW=1, or
- raises virtual instruction exception when privState.V && mstatus.TW=0
&& hstatus.VTW=1
Seems that completely raises no exception is also a valid
implementation,
but raises an exception can help OS to do scheduling during waiting.
Also, like WFI, interrupts cannot take on wrs instructions.
This commit enables complicated parameterization by yaml parsing. We use
circe to do this.
In this commit, we implement 6 configurations:
- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr
For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.
This commit also changes PMAConfigs and PmemRanges into List of case
classes.
* fix the access check for custom CSR and remove the illegal instruction
check when accessing S-mode custom CSR from VS mode. This is because we
can now use the Smstateen extension to control access to custom content
at different privilege levels.
* fix the misjudgment of the U-mode custom CSR.
* fix the missing access check for the stopi CSR in AIA.
This change can help us to capture the waveform of problem caused by
hardware stuck. Besides, since we enlarged mmap memory, it may take much
more time on `fork()` syscall. Enlarging the fork interval here also
results better simulation speed in some circumstances.
* remove tcontrol.
* use xIE to control trigger's breakpoint exception.
* modify medelege: bit(EX_BP) is writable.
* fix emu.yml to make medelege.EX_BP writable in SMP Linux jobs.
The previous riscv64-xs config for nexus-am includes VGA and AUDIO
devices, which do not exist in XiangShan simulation environment. This
patch modifies the workloads used by xiangshan.py to solve the above
problem.
Signed-off-by: "Xu, Zefan" <ceba_robot@outlook.com>
This PR supports handling load store unaligned exceptions by hardware
and provides CSR-controlled switches
---------
Co-authored-by: xiaofeibao <1441675923@qq.com>
Anzooooo
SFangYy
xu_zh
Jiuyue Ma
Yan Xu
Tang Haojin
Zakilim
Yanqin Li
xiaofeibao-xjtu
Anzo
Haoyuan Feng
linzhida
NewPaulWalker
HuSipeng
HeiHuDie
chengguanghui
xiaofeibao
Xu, Zefan
Chen Xi
happy-lx
lwd
Xuan Hu