In our development pratices, it's common to name stdout and stderr
output log as *.log and *.err, respectively, based on informal
observation within our team.
This patch adds *.log and *.err to the .gitignore file to ensure they
are ignored by Git. Notably, *.log is already ignored due to existing
rules, and there is no source files in the projects with a *.err
extension. As such, this patch is safe.
This patch also adds .gitignore into .github/filters.yaml to sikp ci. It
seems no need to run CI again when .gitignore is modified.
- Remove module RefillPipe, move DCache replacer access/update to
MainPipe.
- Using l2_hint as an early wake-up signal for MSHR.
---------
Co-authored-by: YukunXue <1004205984@qq.com>
Co-authored-by: Tang Haojin <tanghaojin@outlook.com>
Co-authored-by: ssszwic <114381825+ssszwic@users.noreply.github.com>
Co-authored-by: Kunlin You <youkunlin20@mails.ucas.ac.cn>
This commit sets up a basic dcache way predictor framework and a dummy predictor.
A Way Predictor Unit (WPU) module has been added to dcache. Dcache data SRAMs
have been reorganized for that.
The dummy predictor is disabled by default.
Besides, dcache bank conflict check has been optimized. It may cause timing problems,
to be fixed in the future.
* ideal wpu
* BankedDataArray: change architecture to reduce bank_conflict
* BankedDataArray: add db analysis
* Merge: the rest
* BankedDataArray: change the logic of rrl_bank_conflict, but let the number of rw_bank_conflict up
* Load Logic: changed to be as expected
reading data will be delayed by one cycle to make selection
writing data will be also delayed by one cycle to do write operation
* fix: ecc check error
* update the gitignore
* WPU: add regular wpu and change the replay mechanism
* WPU: fix refill fail bug, but a new addiw fail bug appears
* WPU: temporarily turn off to PR
* WPU: tfix all bug
* loadqueue: fix the initialization of replayCarry
* bankeddataarray: fix the bug
* DCacheWrapper: fix bug
* ready-to-run: correct the version
* WayPredictor: comments clean
* BankedDataArray: fix ecc_bank bug
* Parameter: set the enable signal of wpu
This commit adds support for using Synopsys VCS to simulate SimTop.
Difftest is also supported.
For now, we use src/test/vsrc/vcs/top.v as the top-level module.
In the future, we may support VCS slave mode for better scalability.
Jiuyue Ma
Xu, Zefan
Yanqin Li
CharlieLiu
Maxpicca-Li
Haojin Tang
wakafa
Yinan Xu
William Wang
Dan Tang
ZhangZifei
Jiuyang liu
Zihao Yu