Zihao Yu
|
d9ad7a31d9
|
fpga,axu3cg: use macro to control the usage of HDMI
|
2020-03-08 13:36:14 +08:00 |
|
Zihao Yu
|
f8c1200b89
|
fpga,boot,README: update doc
|
2019-12-24 10:49:30 +08:00 |
|
Zihao Yu
|
5a28a19212
|
fpga,resource: add ddr-loader
|
2019-12-24 10:49:10 +08:00 |
|
Zihao Yu
|
dfa3bd7fb4
|
fpga,noop.tcl: add AXI4Flash and ILA
|
2019-12-24 10:47:30 +08:00 |
|
Zihao Yu
|
0867df909c
|
fpga,axu3cg: use 200MHz for coreclk
* TLB makes timing worse
|
2019-11-26 11:22:21 +08:00 |
|
Zihao Yu
|
02e4adbecc
|
fpga,axu3cg: disable hdmi
|
2019-11-26 11:21:59 +08:00 |
|
Zihao Yu
|
3d51825846
|
fpga,noop.tcl: connect mtip
|
2019-10-05 16:23:37 +08:00 |
|
Zihao Yu
|
b28961ec19
|
fpga,axu3cg: add hdmi support
* change the fix clk to 40MHz to obtain good timing result
* 50MHz and the 27MHz i2c clock yield bad timing result for inter-clock
|
2019-10-01 09:56:08 +08:00 |
|
Zihao Yu
|
3265aa0990
|
fpga,board,zedboard: support rv64
|
2019-09-24 11:00:04 +08:00 |
|
Zihao Yu
|
a4898ff153
|
fpga,boot: update bug-list
|
2019-09-24 00:11:58 +08:00 |
|
Zihao Yu
|
86d6041ccc
|
fpga,boot,axu3cg: add prebuild u-boot.elf from petalinux 2018.3
* The official version from github seems not work. Maybe there is some
difference between zcu102 and axu3cg.
|
2019-09-24 00:10:18 +08:00 |
|
Zihao Yu
|
964bd05404
|
fpga,board: add axu3cg
|
2019-09-24 00:09:27 +08:00 |
|
Zihao Yu
|
74d05ed6bd
|
fpga,board,ultraZ: use 64-bit data width
|
2019-09-22 00:24:35 +08:00 |
|
Zihao Yu
|
5468444e18
|
fpga,zedboard: update to vivado 2019.1
|
2019-09-09 09:38:04 +08:00 |
|
Zihao Yu
|
c7dbca7c05
|
fpga,noop.tcl: match chisel code
* now the name of RTL module in the block design becomes NOOPSoC
|
2019-09-03 14:17:38 +08:00 |
|
Zihao Yu
|
29d1f10c0d
|
noop: move difftest and monitor
|
2019-08-24 00:02:07 +08:00 |
|
Zihao Yu
|
2dee93d1fd
|
fpga,board: add ultraZ
|
2019-08-21 22:14:20 +08:00 |
|
Zihao Yu
|
3f064ffaf6
|
fpga: use 133MHz coreclk and set multicycle path
|
2019-06-06 17:35:59 +08:00 |
|
Zihao Yu
|
81be003e46
|
board,zedboard: remove GPU
|
2019-05-10 20:25:43 +08:00 |
|
Zihao Yu
|
c357e0e172
|
fpga,zedboard: add monitor.v
|
2019-05-10 20:25:04 +08:00 |
|
Zihao Yu
|
2017417da2
|
fpga,noop: reorganize interconnects
|
2019-03-03 23:38:28 +08:00 |
|
Zihao Yu
|
f9ca23cdb3
|
gpu: support burst read for metaData channel
|
2019-03-02 18:44:53 +08:00 |
|
Zihao Yu
|
70a0b32835
|
fpga,noop: use interconnect to refactor axi connections
|
2019-03-02 17:25:51 +08:00 |
|
Zihao Yu
|
46253fc63e
|
fpga,zedboard: add gpu and run videotest successfully
|
2019-03-02 11:37:33 +08:00 |
|
Zihao Yu
|
8b16d27654
|
device,VGA: rename to AXI4VGA
|
2019-03-01 19:57:44 +08:00 |
|
Zihao Yu
|
8445b62067
|
device,VGA: add frame buffer
|
2019-03-01 13:44:59 +08:00 |
|
Zihao Yu
|
b54f33c2e7
|
device: add basic vga
|
2019-02-28 23:11:19 +08:00 |
|
Zihao Yu
|
13e32bb7b3
|
fpga,noop.tcl: remove unnecessary crossbar
|
2019-02-26 16:42:36 +08:00 |
|
Zihao Yu
|
8caf28820a
|
fpga,board,zedboard: change coreclk to 50MHz
|
2019-02-24 23:12:24 +08:00 |
|
Zihao Yu
|
e69ab0a95e
|
fpga,board,zedboard: set coreclk to 60MHz
|
2019-02-23 00:22:06 +08:00 |
|
Zihao Yu
|
4c1d735b4f
|
fpga,noop: add synchronizer to let corerstn across clock domain
* uncoreclk -> coreclk
|
2019-02-23 00:18:59 +08:00 |
|
Zihao Yu
|
52af9031c2
|
fpga,board,zedboard: remove deleted signals to avoid warnings
|
2019-02-22 17:29:06 +08:00 |
|
Zihao Yu
|
f57a1a74b3
|
fpga,noop.tcl: move ILA to a clock region faster than 10MHz
* else it will be too slow to work
|
2019-02-22 10:39:35 +08:00 |
|
Zihao Yu
|
0c173a2071
|
fpga,board,common.tcl: remove deleted files
|
2019-02-22 01:16:03 +08:00 |
|
Zihao Yu
|
4c92c5be04
|
fpga: add timer and refactor devices
|
2019-02-22 01:05:40 +08:00 |
|
Zihao Yu
|
b2ea3b5205
|
fpga,zedboard,rtl: set ID bits long enough to fix truncation bug
|
2019-02-21 20:11:45 +08:00 |
|
Zihao Yu
|
7e65af41dc
|
fpga,noop.tcl: use AXI to replace AHB bridges
|
2019-02-21 20:11:02 +08:00 |
|
Zihao Yu
|
a9d2aa03ea
|
fpga: add zedboard from labeled-riscv project
* But uart will output extra characters, and microbench fails. It seems
that there may be some bugs in the AHB bridge in chisel code.
|
2019-02-21 14:59:37 +08:00 |