Merge 13db863b94 into 1e7e38e249

chore(Parameters): remove the incorrect parameter description (#4391 )
This is a misrepresentation; currently, there is only one item in the fofbuffer.
2025-04-22 10:21:37 +08:00 · 2025-04-22 10:04:43 +08:00 · 2025-04-22 09:52:44 +08:00 · 2025-04-22 00:42:41 +08:00 · 2025-04-22 00:42:07 +08:00 · 2025-04-22 00:40:40 +08:00
14 changed files with 68 additions and 54 deletions
--- a/.mill-version
+++ b/.mill-version
@ -1 +1 @@
-0.12.3
+0.12.4
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit 6608dc16ec944800d39200e2fad5924d0968b42b
+Subproject commit eacee874c515eadfe197cd6b66a52799c30332c1
--- a/2
+++ b/2
@ -1 +1 @@
-Subproject commit c22a4b2e81d97680380c38cb1ccc7cc2028f01fa
+Subproject commit 2b60fc5edf50f519a4310dc41620e9a204b4aacb
--- a/scalastyle-config.xml
+++ b/scalastyle-config.xml
@ -71,38 +71,38 @@
 <!-- always add a space after `//` or `/*` before comments -->
 <check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
 <!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- (, ~, ! -->
   <parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- :, ,, ) -->
   <parameter name="tokens">COLON, COMMA, RPAREN</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
   <parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
   <parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
   <parameter name="regex"><![CDATA[[^ ](:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)]]></parameter>
  </parameters>
  <customMessage>No space before operators</customMessage>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>
--- a/scalastyle-test-config.xml
+++ b/scalastyle-test-config.xml
@ -71,43 +71,43 @@
 <!-- always add a space after `//` or `/*` before comments -->
 <check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
 <!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- (, ~, ! -->
   <parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- :, ,, ) -->
   <parameter name="tokens">COLON, COMMA, RPAREN</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
  <parameters>
   <!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
   <parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
  <parameters>
   <!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
   <parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
  </parameters>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
   <parameter name="regex"><![CDATA[[^ ](:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)]]></parameter>
  </parameters>
  <customMessage>No space before operators</customMessage>
 </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
  <parameters>
   <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
-   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ ]]]></parameter>
+   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>
  </parameters>
-  <customMessage>No space after operators</customMessage>
+  <customMessage>No space or newline after operators</customMessage>
 </check>

 <!-- ===== imports ===== -->
@ -158,7 +158,7 @@
 <!-- pure lower cases for package names -->
 <check enabled="true" class="org.scalastyle.scalariform.PackageNamesChecker" level="warning">
  <parameters>
-   <parameter name="regex">^[a-z]*$</parameter>
+   <parameter name="regex">^[a-z0-9]*$</parameter>
  </parameters>
 </check>

--- a/src/main/scala/top/XSNoCTop.scala
+++ b/src/main/scala/top/XSNoCTop.scala
@ -222,8 +222,9 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
    val seip  = plic.last(0)
    val nmi_31 = nmi.head(0)
    val nmi_43 = nmi.head(1)
+    val debugIntr = debug.head(0)
    val msi_info_vld = core_with_l2.module.io.msiInfo.valid
-    val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, msi_info_vld)
+    val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, debugIntr, msi_info_vld)

    /*
     * CPU Low Power State:
--- a/src/main/scala/xiangshan/Parameters.scala
+++ b/src/main/scala/xiangshan/Parameters.scala
@ -233,8 +233,6 @@ case class XSCoreParameters
  VLUopWritebackWidth: Int = 2,
  VSUopWritebackWidth: Int = 1,
  VSegmentBufferSize: Int = 8,
-  VFOFBufferSize: Int = 8,
-  VLFOFWritebackWidth: Int = 1,
  // ==============================
  UncacheBufferSize: Int = 4,
  EnableLoadToLoadForward: Boolean = false,
@ -813,7 +811,6 @@ trait HasXSParameter {
  def VLUopWritebackWidth = coreParams.VLUopWritebackWidth
  def VSUopWritebackWidth = coreParams.VSUopWritebackWidth
  def VSegmentBufferSize = coreParams.VSegmentBufferSize
-  def VFOFBufferSize = coreParams.VFOFBufferSize
  def UncacheBufferSize = coreParams.UncacheBufferSize
  def UncacheBufferIndexWidth = log2Up(UncacheBufferSize)
  def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward
--- a/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
+++ b/src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala
@ -204,11 +204,11 @@ class ISelectField(final val maxValue: Int, reserved: Seq[Range]) extends CSREnu
 }

 object VSISelectField extends ISelectField(
-  0x1FF,
+  0xFFF,
  reserved = Seq(
    Range.inclusive(0x000, 0x02F),
    Range.inclusive(0x040, 0x06F),
-    Range.inclusive(0x100, 0x1FF),
+    Range.inclusive(0x100, 0xFFF),
  ),
 )

@ -221,15 +221,16 @@ object MISelectField extends ISelectField(
 )

 object SISelectField extends ISelectField(
-  maxValue = 0xFF,
+  maxValue = 0xFFF,
  reserved = Seq(
-    Range.inclusive(0x00, 0x2F),
-    Range.inclusive(0x40, 0x6F),
+    Range.inclusive(0x000, 0x02F),
+    Range.inclusive(0x040, 0x06F),
+    Range.inclusive(0x100, 0xFFF),
  ),
 )

 class VSISelectBundle extends CSRBundle {
-  val ALL = VSISelectField(log2Up(0x1FF), 0, null).withReset(0.U)
+  val ALL = VSISelectField(log2Up(0xFFF), 0, null).withReset(0.U)
 }

 class MISelectBundle extends CSRBundle {
@ -237,7 +238,7 @@ class MISelectBundle extends CSRBundle {
 }

 class SISelectBundle extends CSRBundle {
-  val ALL = SISelectField(log2Up(0xFF), 0, null).withReset(0.U)
+  val ALL = SISelectField(log2Up(0xFFF), 0, null).withReset(0.U)
 }

 class TopIBundle extends CSRBundle {
--- a/src/main/scala/xiangshan/backend/rename/Rename.scala
+++ b/src/main/scala/xiangshan/backend/rename/Rename.scala
@ -206,8 +206,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
  private val inst         = Wire(Vec(RenameWidth, new XSInstBitFields))
  private val isCsr        = Wire(Vec(RenameWidth, Bool()))
  private val isCsrr       = Wire(Vec(RenameWidth, Bool()))
-  private val isWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
-  private val isBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
+  private val isNotWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
+  private val isNotBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
  private val fuType       = uops.map(_.fuType)
  private val fuOpType     = uops.map(_.fuOpType)
  private val vtype        = uops.map(_.vpu.vtype)
@ -291,9 +291,9 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
    inst(i) := uops(i).instr.asTypeOf(new XSInstBitFields)
    isCsr(i) := inst(i).OPCODE5Bit === OPCODE5Bit.SYSTEM && inst(i).FUNCT3(1, 0) =/= 0.U
    isCsrr(i) := isCsr(i) && inst(i).FUNCT3 === BitPat("b?1?") && inst(i).RS1 === 0.U
-    isWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
+    isNotWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
      inst(i).CSRIDX, true.B, CSROoORead.waitForwardInOrderCsrReadList.map(_.U -> false.B))
-    isBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
+    isNotBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
      inst(i).CSRIDX, true.B, CSROoORead.blockBackwardInOrderCsrReadList.map(_.U -> false.B))

    /*
@ -303,8 +303,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     *
     * Signal "isCsrr" contains not only "CSRR", but also other CSR instructions that do not require writing to CSR.
     */
-    uops(i).waitForward := io.in(i).bits.waitForward && !isWaitForwardCsrr(i)
-    uops(i).blockBackward := io.in(i).bits.blockBackward && !isBlockBackwardCsrr(i)
+    uops(i).waitForward := io.in(i).bits.waitForward && !isNotWaitForwardCsrr(i)
+    uops(i).blockBackward := io.in(i).bits.blockBackward && !isNotBlockBackwardCsrr(i)

    // update cf according to ssit result
    uops(i).storeSetHit := io.ssit(i).valid
--- a/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
+++ b/src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala
@ -378,11 +378,9 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
  val s1_need_replacement = s1_req.miss && !s1_tag_match
  val s1_need_eviction = s1_req.miss && !s1_tag_match && s1_repl_coh.state =/= ClientStates.Nothing

-  val s1_way_en = Mux(
-    RegEnable(io.pseudo_error.valid, false.B, s0_fire),
-    Mux(ParallelORR(s1_real_tag_match_way), s1_real_tag_match_way, s1_repl_way_en),
-    Mux(s1_need_replacement, s1_repl_way_en, s1_real_tag_match_way)
-  )
+  val s1_no_error_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_real_tag_match_way)
+  val s1_error_way_en = Mux(ParallelORR(s1_real_tag_match_way), s1_real_tag_match_way, s1_repl_way_en)
+  val s1_way_en = Mux(io.pseudo_error.valid, s1_error_way_en, s1_no_error_way_en)
  assert(!RegNext(s1_fire && PopCount(s1_way_en) > 1.U))

  val s1_tag = s1_hit_tag
@ -413,7 +411,6 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
  val s2_need_tag = RegEnable(s1_need_tag, s1_fire)
  val s2_idx = get_idx(s2_req.vaddr)

-
  val s2_way_en = RegEnable(s1_way_en, s1_fire)
  val s2_tag = Mux(s2_need_replacement, s2_repl_tag, RegEnable(s1_tag, s1_fire))
  val s2_coh = Mux(s2_need_replacement, s2_repl_coh, RegEnable(s1_coh, s1_fire))
@ -427,8 +424,10 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w

  val s2_hit = s2_tag_match && s2_has_permission
  val s2_sc = s2_req.cmd === M_XSC
+  val s2_lr = s2_req.cmd === M_XLR
  val s2_amo_hit = s2_hit && !s2_req.probe && !s2_req.miss && s2_req.isAMO
  val s2_store_hit = s2_hit && !s2_req.probe && !s2_req.miss && s2_req.isStore
+  val s2_should_not_report_ecc_error = !s2_req.miss && (s2_req.isAMO && !s2_lr || s2_req.isStore)

  if(EnableTagEcc) {
    s2_tag_error := s2_tag_errors.orR && s2_need_tag
@ -978,7 +977,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
    s.s1.bits.way_en := s1_way_en
    s.s2.valid := s2_valid && !RegEnable(s1_req.replace, s1_fire)
    s.s2.bits.set := RegEnable(get_idx(s1_req.vaddr), s1_fire)
-    s.s2.bits.way_en := RegEnable(s1_way_en, s1_fire)
+    s.s2.bits.way_en := s2_way_en
    s.s3.valid := s3_valid && !RegEnable(s2_req.replace, s2_fire_to_s3)
    s.s3.bits.set := RegEnable(get_idx(s2_req.vaddr), s2_fire_to_s3)
    s.s3.bits.way_en := RegEnable(s2_way_en, s2_fire_to_s3)
@ -995,7 +994,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
  // report error to beu and csr, 1 cycle after read data resp
  io.error := 0.U.asTypeOf(ValidIO(new L1CacheErrorInfo))
  // report error, update error csr
-  io.error.valid := s3_error && GatedValidRegNext(s2_fire && !(s2_req.isAMO || s2_req.isStore))
+  io.error.valid := s3_error && GatedValidRegNext(s2_fire && !s2_should_not_report_ecc_error)
  // only tag_error and data_error will be reported to beu
  // l2_error should not be reported (l2 will report that)
  io.error.bits.report_to_beu := (s3_tag_error || s3_data_error) && RegNext(s2_fire)
--- a/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
+++ b/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala
@ -781,17 +781,28 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
  val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id)))
  val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) && !io.mem.flush_latch(io.mem.resp.bits.id) // dup with the entry that data coming next cycle
  val to_wait = Cat(dup_vec_wait).orR || dup_req_fire
-  val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && !bitmap_enable
-  val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) && bitmap_enable
-  val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
-                 else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
-  val to_hptw_req = io.in.bits.req_info.s2xlate === allStage
-  val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage
+
  val last_hptw_req_id = io.mem.resp.bits.id
  val req_paddr = MakeAddr(io.in.bits.ppn(ppnLen-1, 0), getVpnn(io.in.bits.req_info.vpn, 0))
  val req_hpaddr = MakeAddr(entries(last_hptw_req_id).hptw_resp.genPPNS2(get_pn(req_paddr)), getVpnn(io.in.bits.req_info.vpn, 0))
  val index =  Mux(entries(last_hptw_req_id).req_info.s2xlate === allStage, req_hpaddr, req_paddr)(log2Up(l2tlbParams.blockBytes)-1, log2Up(XLEN/8))
-  val last_hptw_req_ppn = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index).getPPN()
+  val last_hptw_req_pte = io.mem.resp.bits.value.asTypeOf(Vec(blockBits / XLEN, new PteBundle()))(index)
+  val last_hptw_req_ppn = Mux(last_hptw_req_pte.n === 0.U, last_hptw_req_pte.getPPN(), Cat(last_hptw_req_pte.getPPN()(ptePPNLen - 1, pteNapotBits), io.in.bits.req_info.vpn(pteNapotBits - 1, 0)))
+  // in `to_last_hptw_req`, we have already judged whether s2xlate === allStage
+  val last_hptw_vsStagePf = last_hptw_req_pte.isPf(0.U, io.csr.hPBMTE) || !last_hptw_req_pte.isLeaf()
+  val last_hptw_gStagePf = last_hptw_req_pte.isStage1Gpf(io.csr.hgatp.mode) && !last_hptw_vsStagePf
+
+  // noS2xlate || onlyStage1 || allStage but exception; do not need Stage2 translate
+  val noStage2 = ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) ||
+    (entries(io.mem.resp.bits.id).req_info.s2xlate === allStage && (last_hptw_vsStagePf || last_hptw_gStagePf))
+  val to_mem_out = dup_wait_resp && noStage2 && !bitmap_enable
+  val to_bitmap_req = (if (HasBitmapCheck) true.B else false.B) && dup_wait_resp && noStage2 && bitmap_enable
+  val to_cache = if (HasBitmapCheck) Cat(dup_vec_bitmap).orR || Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
+                 else Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR
+  val to_hptw_req = io.in.bits.req_info.s2xlate === allStage
+  val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage && !(last_hptw_vsStagePf || last_hptw_gStagePf)
+  val last_hptw_excp = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage && (last_hptw_vsStagePf || last_hptw_gStagePf)
+
  XSError(RegNext(dup_req_fire && Cat(dup_vec_wait).orR, init = false.B), "mem req but some entries already waiting, should not happed")

  XSError(io.in.fire && ((to_mem_out && to_cache) || (to_wait && to_cache)), "llptw enq, to cache conflict with to mem")
@ -811,7 +822,7 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
    // so 2 + FilterSize is enough to avoid dead-lock
    state(enq_ptr) := enq_state
    entries(enq_ptr).req_info := io.in.bits.req_info
-    entries(enq_ptr).ppn := Mux(to_last_hptw_req, last_hptw_req_ppn, io.in.bits.ppn)
+    entries(enq_ptr).ppn := Mux(to_last_hptw_req || last_hptw_excp, last_hptw_req_ppn, io.in.bits.ppn)
    entries(enq_ptr).wait_id := Mux(to_wait, wait_id, enq_ptr)
    entries(enq_ptr).af := false.B
    if (HasBitmapCheck) {
@ -825,6 +836,7 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
      entries(enq_ptr).cfs := io.in.bits.bitmapCheck.get.cfs
    }
    entries(enq_ptr).hptw_resp := Mux(to_last_hptw_req, entries(last_hptw_req_id).hptw_resp, Mux(to_wait, entries(wait_id).hptw_resp, entries(enq_ptr).hptw_resp))
+    entries(enq_ptr).hptw_resp.gpf := Mux(last_hptw_excp, last_hptw_gStagePf, false.B)
    entries(enq_ptr).first_s2xlate_fault := false.B
    mem_resp_hit(enq_ptr) := to_bitmap_req || to_mem_out || to_last_hptw_req
  }
@ -962,7 +974,9 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe
          entries(i).hptw_resp.gpf := io.hptw.resp.bits.h_resp.gpf || check_g_perm_fail
          entries(i).first_s2xlate_fault := io.hptw.resp.bits.h_resp.gaf || io.hptw.resp.bits.h_resp.gpf
        }.otherwise{ // change the entry that is waiting hptw resp
-          val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting && dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn))
+          val need_to_waiting_vec = state.indices.map(i => state(i) === state_mem_waiting &&
+            dup(entries(i).req_info.vpn, entries(io.hptw.resp.bits.id).req_info.vpn) &&
+            entries(i).req_info.s2xlate === entries(io.hptw.resp.bits.id).req_info.s2xlate)
          val waiting_index = ParallelMux(need_to_waiting_vec zip entries.map(_.wait_id))
          state(i) := Mux(Cat(need_to_waiting_vec).orR, state_mem_waiting, state_addr_check)
          entries(i).hptw_resp := io.hptw.resp.bits.h_resp
--- a/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala
@ -300,7 +300,7 @@ class LoadQueue(implicit p: Parameters) extends XSModule
  for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) {
    // from load_s3
    val ldinBits = io.ldu.ldin(w).bits
-    buff.valid := io.ldu.ldin(w).valid && (ldinBits.nc || ldinBits.mmio) && !ldinBits.rep_info.need_rep && !ldinBits.nc_with_data
+    buff.valid := io.ldu.ldin(w).valid && !ldinBits.nc_with_data
    buff.bits := ldinBits
  }

--- a/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
+++ b/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala
@ -939,6 +939,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
  val cboZeroFlushSb     = GatedRegNext(cboZeroToSb)

  val cboZeroUop         = RegEnable(PriorityMux(isCboZeroToSbVec, deqPtrExt.map(x=>uop(x.value))), cboZeroToSb)
+  val cboZeroSqIdx       = RegEnable(PriorityMux(isCboZeroToSbVec, deqPtrExt), cboZeroToSb)
  val cboZeroValid       = RegInit(false.B)
  val cboZeroWaitFlushSb = RegInit(false.B)

@ -1014,6 +1015,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
  // cbo Zero writeback to ROB
  io.cboZeroStout.valid                := cboZeroValid && !cboZeroWaitFlushSb
  io.cboZeroStout.bits.uop             := cboZeroUop
+  io.cboZeroStout.bits.uop.sqIdx       := cboZeroSqIdx
  io.cboZeroStout.bits.data            := DontCare
  io.cboZeroStout.bits.isFromLoadUnit  := DontCare
  io.cboZeroStout.bits.debug.isMMIO    := false.B
--- a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
+++ b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala
@ -114,7 +114,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule
  val s0_rob_idx      = Mux(s0_use_non_prf_flow, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx))
  val s0_pc           = Mux(s0_use_non_prf_flow, s0_uop.pc, 0.U)
  val s0_instr_type   = Mux(s0_use_non_prf_flow, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U)
-  val s0_wlineflag    = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B)
+  val s0_wlineflag    = Mux(s0_use_flow_rs, LSUOpType.isCboAll(s0_uop.fuOpType), false.B)
  val s0_out          = Wire(new LsPipelineBundle)
  val s0_kill         = s0_uop.robIdx.needFlush(io.redirect)
  val s0_can_go       = s1_ready
Author	SHA1	Message	Date
Tang Haojin	a67f6a3acf	Merge `13db863b94` into `1e7e38e249`	2025-04-22 10:21:37 +08:00
Anzo	1e7e38e249	chore(Parameters): remove the incorrect parameter description (#4391 ) EMU Test / Changes Detection (push) Waiting to run Details EMU Test / Generate Verilog (push) Blocked by required conditions Details EMU Test / EMU - Basics (push) Blocked by required conditions Details EMU Test / EMU - CHI (push) Blocked by required conditions Details EMU Test / EMU - Performance (push) Blocked by required conditions Details EMU Test / EMU - MC (push) Blocked by required conditions Details EMU Test / SIMV - Basics (push) Blocked by required conditions Details EMU Test / Upload Artifacts (push) Blocked by required conditions Details EMU Test / Check Submodules (push) Blocked by required conditions Details EMU Test / Check Format (push) Blocked by required conditions Details This is a misrepresentation; currently, there is only one item in the fofbuffer.	2025-04-22 10:04:43 +08:00
NewPaulWalker	f9ed852fb2	fix(xiselect): set the minimum range for xiselect (#4594 ) The miselect register implements at least enough bits to support all implemented miselect values. The siselect register will support the value range 0..0xFFF at a minimum. The vsiselect register will support the value range 0..0xFFF at a minimum.	2025-04-22 09:52:44 +08:00
cz4e	99a48a761c	timing(LoadQueueUncache): adjust s1 enq and s2 enq valid generate logic (#4603 ) EMU Test / Changes Detection (push) Waiting to run Details EMU Test / Generate Verilog (push) Blocked by required conditions Details EMU Test / EMU - Basics (push) Blocked by required conditions Details EMU Test / EMU - CHI (push) Blocked by required conditions Details EMU Test / EMU - Performance (push) Blocked by required conditions Details EMU Test / EMU - MC (push) Blocked by required conditions Details EMU Test / SIMV - Basics (push) Blocked by required conditions Details EMU Test / Upload Artifacts (push) Blocked by required conditions Details EMU Test / Check Submodules (push) Blocked by required conditions Details EMU Test / Check Format (push) Blocked by required conditions Details	2025-04-22 00:42:41 +08:00
Anzo	cd450e3243	submodule(ready-to-run): bump nemu and spike ref in ready-to-run (#4604 )	2025-04-22 00:42:07 +08:00
Zhaoyang You	51ad03b0f6	fix(rename): fix Csrr format (#4605 )	2025-04-22 00:40:40 +08:00
zhaohong1988	d7dd2491d4	submodule(ChiselAIA): bump ChiselAIA (#4595 )	2025-04-22 00:37:45 +08:00
xu_zh	be3685ffd1	chore(scalastyle): disable space-around-operator checks (#4567 )	2025-04-22 00:37:04 +08:00
Guanghui Cheng	b5c820f608	fix(top): enable cpuclock when debug halt req (#4583 )	2025-04-22 00:36:20 +08:00
Anzo	3aa632ec4e	fix(StoreUnit): cbo violation check should check cacheline (#4592 ) EMU Test / Changes Detection (push) Waiting to run Details EMU Test / Generate Verilog (push) Blocked by required conditions Details EMU Test / EMU - Basics (push) Blocked by required conditions Details EMU Test / EMU - CHI (push) Blocked by required conditions Details EMU Test / EMU - Performance (push) Blocked by required conditions Details EMU Test / EMU - MC (push) Blocked by required conditions Details EMU Test / SIMV - Basics (push) Blocked by required conditions Details EMU Test / Upload Artifacts (push) Blocked by required conditions Details EMU Test / Check Submodules (push) Blocked by required conditions Details EMU Test / Check Format (push) Blocked by required conditions Details The cbo instruction should check for violations at the granularity of cacheline. Theoretically modifying the condition of this variable would allow checking at cacheline granularity in RAW and should not introduce any other side effects.	2025-04-21 18:55:13 +08:00
Anzo	ce78e60ca4	fix(StoreQueue): remove `cboZeroUop` saved `sqptr` (#4591 )	2025-04-21 18:53:08 +08:00
cz4e	dccbba583f	fix(MainPipe): fix error report valid when Atomics and SBuffer request miss (#4572 ) * Sbuffer write and Atomics should not report errors, but refill from L2 should report ecc error, but requests in MissQueue carry `isAmo` or `isStore` and `req.miss` in a request, hence `(s2_req.isAMO \|\| s2_req.isStore)` includes the refill, so the missing request of `isAmo` or `isStore` will not report an error	2025-04-21 18:35:02 +08:00
cz4e	d69a82861a	fix(MainPipe): fix `s1_way_en` logic when pseudo tag error inject (#4573 ) * `s1_way_en` should use `io.pseudo_error.valid` on the same stage, not `RegNext(io.pseudo_error.valid)`. Otherwise, `MainPipe` may use wrong way enable to write DCache, it will result in two identical tags.	2025-04-21 18:33:20 +08:00
Haoyuan Feng	57a8ca5e38	fix(LLPTW): dup_wait_resp should not send last_hptw_req when excp (#4596 ) EMU Test / Changes Detection (push) Waiting to run Details EMU Test / Generate Verilog (push) Blocked by required conditions Details EMU Test / EMU - Basics (push) Blocked by required conditions Details EMU Test / EMU - CHI (push) Blocked by required conditions Details EMU Test / EMU - Performance (push) Blocked by required conditions Details EMU Test / EMU - MC (push) Blocked by required conditions Details EMU Test / SIMV - Basics (push) Blocked by required conditions Details EMU Test / Upload Artifacts (push) Blocked by required conditions Details EMU Test / Check Submodules (push) Blocked by required conditions Details EMU Test / Check Format (push) Blocked by required conditions Details In the original design, the condition for `to_last_hptw_req` was: `dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage`. As a result, when a newly entered LLPTW request dups with an entry currently returning from memory, and the new request is marked as allStage, the `to_last_hptw_req` signal would be true. This causes the state machine to transition to the `state_last_hptw_req` state and send a request to HPTW. However, if the page table returned from memory contains a `vsStagePf` or `gStagePf`, it should directly go to `mem_out` or `bitmap_check` without performing a final HPTW translation. Therefore, this commit fixes the bug by adding a restriction to the original `to_last_hptw_req` condition to ensure that no exceptions are present; otherwise, the state machine will transition to either `mem_out` or `bitmap_check`. Additionally, this PR also fixes a bug where `last_hptw_req_ppn` did not account for the napot case.	2025-04-21 00:47:49 +08:00
Haoyuan Feng	96b05afa13	fix(LLPTW): dup entry should consider s2xlate in need_to_waiting_vec (#4597 )	2025-04-21 00:47:31 +08:00
Tang Haojin	13db863b94	build: bump mill to 0.12.4	2024-12-18 12:19:19 +08:00
 @ -1 +1 @@
 .12.3
 .12.4