Merge 3c0da37db6 into 1e7e38e249

This is a misrepresentation; currently, there is only one item in the fofbuffer.

ChiselAIA

@@ -1 +1 @@
-Subproject commit 6608dc16ec944800d39200e2fad5924d0968b42b
+Subproject commit eacee874c515eadfe197cd6b66a52799c30332c1

ready-to-run

@@ -1 +1 @@
-Subproject commit c22a4b2e81d97680380c38cb1ccc7cc2028f01fa
+Subproject commit 2b60fc5edf50f519a4310dc41620e9a204b4aacb

scalastyle-config.xml

@@ -71,38 +71,38 @@
  <!-- always add a space after `//` or `/*` before comments -->
  <check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
  <!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
   <parameters>
    <!-- (, ~, ! -->
    <parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
   <parameters>
    <!-- :, ,, ) -->
    <parameter name="tokens">COLON, COMMA, RPAREN</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
   <parameters>
    <!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
    <parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
   <parameters>
    <!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
    <parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
   <parameters>
    <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
    <parameter name="regex"><![CDATA[[^ ](:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)]]></parameter>
   </parameters>
   <customMessage>No space before operators</customMessage>
  </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
   <parameters>
    <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
    <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>

scalastyle-test-config.xml

@@ -71,43 +71,43 @@
  <!-- always add a space after `//` or `/*` before comments -->
  <check enabled="true" class="org.scalastyle.scalariform.SpaceAfterCommentStartChecker" level="warning"/>
  <!-- check space around operators, ref: https://github.com/scala-ide/scalariform/blob/master/scalariform/src/main/scala/scalariform/lexer/Tokens.scala -->
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceAfterTokenChecker" level="warning">
   <parameters>
    <!-- (, ~, ! -->
    <parameter name="tokens">LPAREN, TILDE, EXCLAMATION</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.DisallowSpaceBeforeTokenChecker" level="warning">
   <parameters>
    <!-- :, ,, ) -->
    <parameter name="tokens">COLON, COMMA, RPAREN</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceAfterTokenChecker" level="warning">
   <parameters>
    <!-- if, match, case, for, while, =>, <-, {, <:, <%:, >:, +, -, *, |, = -->
    <parameter name="tokens">IF, MATCH, CASE, FOR, WHILE, ARROW, LARROW, LBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.scalariform.EnsureSingleSpaceBeforeTokenChecker" level="warning">
   <parameters>
    <!-- =>, <-, }, <:, <%, >:, +, -, *, |, = -->
    <parameter name="tokens">ARROW, LARROW, RBRACE, SUBTYPE, VIEWBOUND, SUPERTYPE, PLUS, MINUS, STAR, PIPE, EQUAL</parameter>
   </parameters>
  </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
   <parameters>
    <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
    <parameter name="regex"><![CDATA[[^ ](:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)]]></parameter>
   </parameters>
   <customMessage>No space before operators</customMessage>
  </check>
- <check enabled="true" class="org.scalastyle.file.RegexChecker" level="warning">
+ <check enabled="false" class="org.scalastyle.file.RegexChecker" level="warning">
   <parameters>
    <!-- :=, :<=, :>=, :<>=, :#=, <>, ===, =/=, <<, >>, <=, >= -->
-   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ ]]]></parameter>
+   <parameter name="regex"><![CDATA[(:<?#?>?=|<>|=[=/]=|<<|>>|[<>]=)[^ \n]]]></parameter>
   </parameters>
-  <customMessage>No space after operators</customMessage>
+  <customMessage>No space or newline after operators</customMessage>
  </check>
 
  <!-- ===== imports ===== -->
@@ -158,7 +158,7 @@
  <!-- pure lower cases for package names -->
  <check enabled="true" class="org.scalastyle.scalariform.PackageNamesChecker" level="warning">
   <parameters>
-   <parameter name="regex">^[a-z]*$</parameter>
+   <parameter name="regex">^[a-z0-9]*$</parameter>
   </parameters>
  </check>
 

src/main/scala/top/XSNoCTop.scala

@@ -222,8 +222,9 @@ class XSNoCTop()(implicit p: Parameters) extends BaseXSSoc with HasSoCParameter
     val seip  = plic.last(0)
     val nmi_31 = nmi.head(0)
     val nmi_43 = nmi.head(1)
+    val debugIntr = debug.head(0)
     val msi_info_vld = core_with_l2.module.io.msiInfo.valid
-    val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, msi_info_vld)
+    val intSrc = Cat(msip, mtip, meip, seip, nmi_31, nmi_43, debugIntr, msi_info_vld)
 
     /*
      * CPU Low Power State:

src/main/scala/xiangshan/Parameters.scala

@@ -233,8 +233,6 @@ case class XSCoreParameters
   VLUopWritebackWidth: Int = 2,
   VSUopWritebackWidth: Int = 1,
   VSegmentBufferSize: Int = 8,
-  VFOFBufferSize: Int = 8,
-  VLFOFWritebackWidth: Int = 1,
   // ==============================
   UncacheBufferSize: Int = 4,
   EnableLoadToLoadForward: Boolean = false,
@@ -813,7 +811,6 @@ trait HasXSParameter {
   def VLUopWritebackWidth = coreParams.VLUopWritebackWidth
   def VSUopWritebackWidth = coreParams.VSUopWritebackWidth
   def VSegmentBufferSize = coreParams.VSegmentBufferSize
-  def VFOFBufferSize = coreParams.VFOFBufferSize
   def UncacheBufferSize = coreParams.UncacheBufferSize
   def UncacheBufferIndexWidth = log2Up(UncacheBufferSize)
   def EnableLoadToLoadForward = coreParams.EnableLoadToLoadForward

src/main/scala/xiangshan/backend/fu/Bku.scala

@@ -186,6 +186,14 @@ class HashModule(implicit p: Parameters) extends XSModule {
 }
 
 class BlockCipherModule(implicit p: Parameters) extends XSModule {
+  def asVecByWidth(x: UInt, width: Int): Vec[UInt] = {
+    require(x.getWidth % width == 0)
+    val numElem: Int = x.getWidth / width
+    VecInit((0 until numElem).map(i => x(width * (i + 1) - 1, width * i)))
+  }
+
+  def asBytes(x: UInt): Vec[UInt] = asVecByWidth(x, 8)
+
   val io = IO(new Bundle() {
     val src = Vec(2, Input(UInt(XLEN.W)))
     val func = Input(UInt())
@@ -195,36 +203,62 @@ class BlockCipherModule(implicit p: Parameters) extends XSModule {
 
   val (src1, src2, func, funcReg) = (io.src(0), io.src(1), io.func, RegEnable(io.func, io.regEnable))
 
-  val src1Bytes = VecInit((0 until 8).map(i => src1(i*8+7, i*8)))
-  val src2Bytes = VecInit((0 until 8).map(i => src2(i*8+7, i*8)))
+  val src1Bytes = asBytes(src1)
+  val src2Bytes = asBytes(src2)
+
+  val src1_reg = RegEnable(src1, io.regEnable)
+  val src2_reg = RegEnable(src2, io.regEnable)
 
   // AES
-  val aesSboxIn  = ForwardShiftRows(src1Bytes, src2Bytes)
-  val aesSboxMid  = Reg(Vec(8, Vec(18, Bool())))
+  val aesSboxIn   = Wire(Vec(8, UInt(8.W)))
   val aesSboxOut  = Wire(Vec(8, UInt(8.W)))
-
-  val iaesSboxIn = InverseShiftRows(src1Bytes, src2Bytes)
-  val iaesSboxMid  = Reg(Vec(8, Vec(18, Bool())))
+  val iaesSboxIn  = Wire(Vec(8, UInt(8.W)))
   val iaesSboxOut = Wire(Vec(8, UInt(8.W)))
+  val ksSboxIn    = Wire(Vec(4, UInt(8.W)))
+  val ksSboxOut   = Wire(Vec(4, UInt(8.W)))
 
-  aesSboxOut.zip(aesSboxMid).zip(aesSboxIn)foreach { case ((out, mid), in) =>
-    when (io.regEnable) {
-      mid := SboxInv(SboxAesTop(in))
-    }
-    out := SboxAesOut(mid)
-  }
-
-  iaesSboxOut.zip(iaesSboxMid).zip(iaesSboxIn)foreach { case ((out, mid), in) =>
-    when (io.regEnable) {
-      mid := SboxInv(SboxIaesTop(in))
-    }
-    out := SboxIaesOut(mid)
+  val isInvAes = func(1) // 0: aes64es/aes64esm/aes64ks1i  1: aes64ds/aes64dsm
+  val isKsAes  = func(2) // 0: aes64es/aes64esm            1: aes64ks1i
+
+  val aesEncSboxIn = Wire(Vec(8, UInt(8.W)))
+  val aesDecSboxIn = Wire(Vec(8, UInt(8.W)))
+  val aesEncSboxInLow  = Wire(Vec(4, UInt(8.W)))
+  val aesEncSboxInHigh = Wire(Vec(4, UInt(8.W)))
+
+  aesEncSboxIn := ForwardShiftRows(src1Bytes, src2Bytes)
+  aesDecSboxIn := InverseShiftRows(src1Bytes, src2Bytes)
+  aesEncSboxInLow  := aesEncSboxIn.take(4)
+  aesEncSboxInHigh := aesEncSboxIn.drop(4)
+  ksSboxIn := Mux(
+    src2(3, 0) === 0xa.U(4.W),
+    VecInit(src1Bytes(4), src1Bytes(5), src1Bytes(6), src1Bytes(7)),
+    VecInit(src1Bytes(5), src1Bytes(6), src1Bytes(7), src1Bytes(4))
+  )
+
+  aesSboxIn  := Mux(isKsAes, ksSboxIn, aesEncSboxInLow) ++ aesEncSboxInHigh
+  iaesSboxIn := aesDecSboxIn
+
+  (aesSboxIn lazyZip iaesSboxIn lazyZip aesSboxOut lazyZip iaesSboxOut).foreach {
+    case (fwdIn, invIn, fwdOut, invOut) =>
+      val aesSBox1FwdOut = SboxAesTop(fwdIn)
+      val aesSBox1InvOut = SboxIaesTop(invIn)
+
+      val aesSBox2In  = Mux(isInvAes, aesSBox1InvOut, aesSBox1FwdOut)
+      val aesSBox2Out = Reg(UInt(18.W)) // 1 cycle delay
+      when (io.regEnable) {
+        aesSBox2Out := SboxInv(aesSBox2In)
+      }
+
+      fwdOut := SboxAesOut(aesSBox2Out)
+      invOut := SboxIaesOut(aesSBox2Out)
   }
+  ksSboxOut := aesSboxOut.take(4)
 
+  // AES encryption/decryption
   val aes64es = aesSboxOut.asUInt
   val aes64ds = iaesSboxOut.asUInt
 
-  val imMinIn  = RegEnable(src1Bytes, io.regEnable)
+  val imMinIn = asBytes(src1_reg)
 
   val aes64esm = Cat(MixFwd(Seq(aesSboxOut(4), aesSboxOut(5), aesSboxOut(6), aesSboxOut(7))),
                      MixFwd(Seq(aesSboxOut(0), aesSboxOut(1), aesSboxOut(2), aesSboxOut(3))))
@@ -233,30 +267,19 @@ class BlockCipherModule(implicit p: Parameters) extends XSModule {
   val aes64im  = Cat(MixInv(Seq(imMinIn(4), imMinIn(5), imMinIn(6), imMinIn(7))),
                      MixInv(Seq(imMinIn(0), imMinIn(1), imMinIn(2), imMinIn(3))))
 
+  // AES key schedule
+  val rconSeq: Seq[Int] = Seq(
+    0x01, 0x02, 0x04, 0x08,
+    0x10, 0x20, 0x40, 0x80,
+    0x1b, 0x36, 0x00
+  )
+  val rcon = VecInit(rconSeq.map(_.U(8.W)))
 
-  val rcon = WireInit(VecInit(Seq("h01".U, "h02".U, "h04".U, "h08".U,
-                                  "h10".U, "h20".U, "h40".U, "h80".U,
-                                  "h1b".U, "h36".U, "h00".U)))
-
-  val ksSboxIn  = Wire(Vec(4, UInt(8.W)))
-  val ksSboxTop = Reg(Vec(4, Vec(21, Bool())))
-  val ksSboxOut = Wire(Vec(4, UInt(8.W)))
-  ksSboxIn(0) := Mux(src2(3,0) === "ha".U, src1Bytes(4), src1Bytes(5))
-  ksSboxIn(1) := Mux(src2(3,0) === "ha".U, src1Bytes(5), src1Bytes(6))
-  ksSboxIn(2) := Mux(src2(3,0) === "ha".U, src1Bytes(6), src1Bytes(7))
-  ksSboxIn(3) := Mux(src2(3,0) === "ha".U, src1Bytes(7), src1Bytes(4))
-  ksSboxOut.zip(ksSboxTop).zip(ksSboxIn).foreach{ case ((out, top), in) =>
-    when (io.regEnable) {
-      top := SboxAesTop(in)
-    }
-    out := SboxAesOut(SboxInv(top))
-    }
-
-  val ks1Idx = RegEnable(src2(3,0), io.regEnable)
+  val ks1Idx = src2_reg(3, 0)
   val aes64ks1i = Cat(ksSboxOut.asUInt ^ rcon(ks1Idx), ksSboxOut.asUInt ^ rcon(ks1Idx))
 
-  val aes64ks2Temp = src1(63,32) ^ src2(31,0)
-  val aes64ks2 = RegEnable(Cat(aes64ks2Temp ^ src2(63,32), aes64ks2Temp), io.regEnable)
+  val aes64ks2Temp = src1_reg(63, 32) ^ src2_reg(31, 0)
+  val aes64ks2 = Cat(aes64ks2Temp ^ src2_reg(63, 32), aes64ks2Temp)
 
   val aesResult = LookupTreeDefault(funcReg, aes64es, List(
     BKUOpType.aes64es   -> aes64es,
@@ -269,26 +292,35 @@ class BlockCipherModule(implicit p: Parameters) extends XSModule {
   ))
 
   // SM4
-  val sm4SboxIn  = src2Bytes(func(1,0))
-  val sm4SboxTop = Reg(Vec(21, Bool()))
+  val sm4SboxIn  = src2Bytes(func(1, 0))
+  val sm4SboxTop = Reg(UInt(21.W))
   when (io.regEnable) {
     sm4SboxTop := SboxSm4Top(sm4SboxIn)
   }
   val sm4SboxOut = SboxSm4Out(SboxInv(sm4SboxTop))
+  // val sm4SboxTop = Reg(Vec(21, Bool()))
+  // when (io.regEnable) {
+  //   sm4SboxTop := SboxSm4Top(sm4SboxIn)
+  // }
+  // val sm4SboxOut = SboxSm4Out(SboxInv(sm4SboxTop))
 
-  val sm4ed = sm4SboxOut ^ (sm4SboxOut<<8) ^ (sm4SboxOut<<2) ^ (sm4SboxOut<<18) ^ ((sm4SboxOut&"h3f".U)<<26) ^ ((sm4SboxOut&"hc0".U)<<10)
-  val sm4ks = sm4SboxOut ^ ((sm4SboxOut&"h07".U)<<29) ^ ((sm4SboxOut&"hfe".U)<<7) ^ ((sm4SboxOut&"h01".U)<<23) ^ ((sm4SboxOut&"hf8".U)<<13)
+  val sm4ed = sm4SboxOut ^ (sm4SboxOut << 8).asUInt ^ (sm4SboxOut << 2).asUInt ^ (sm4SboxOut << 18).asUInt ^
+              ((sm4SboxOut & 0x3f.U) << 26).asUInt ^ ((sm4SboxOut & 0xc0.U) << 10).asUInt
+  val sm4ks = sm4SboxOut ^ ((sm4SboxOut & 0x07.U) << 29).asUInt ^ ((sm4SboxOut & 0xfe.U) << 7).asUInt ^
+              ((sm4SboxOut & 0x01.U) << 23).asUInt ^ ((sm4SboxOut & 0xf8.U) << 13).asUInt
   val sm4Source = VecInit(Seq(
-    sm4ed(31,0),
-    Cat(sm4ed(23,0), sm4ed(31,24)),
-    Cat(sm4ed(15,0), sm4ed(31,16)),
-    Cat(sm4ed( 7,0), sm4ed(31,8)),
-    sm4ks(31,0),
-    Cat(sm4ks(23,0), sm4ks(31,24)),
-    Cat(sm4ks(15,0), sm4ks(31,16)),
-    Cat(sm4ks( 7,0), sm4ks(31,8))
+    sm4ed(31, 0),
+    Cat(sm4ed(23, 0), sm4ed(31, 24)),
+    Cat(sm4ed(15, 0), sm4ed(31, 16)),
+    Cat(sm4ed( 7, 0), sm4ed(31, 8)),
+    sm4ks(31, 0),
+    Cat(sm4ks(23, 0), sm4ks(31, 24)),
+    Cat(sm4ks(15, 0), sm4ks(31, 16)),
+    Cat(sm4ks( 7, 0), sm4ks(31, 8))
   ))
-  val sm4Result = SignExt((sm4Source(funcReg(2,0)) ^ RegEnable(src1(31,0), io.regEnable))(31,0), XLEN)
+  val sm4ResultTemp = Wire(UInt(32.W))
+  sm4ResultTemp := sm4Source(funcReg(2, 0)) ^ src1_reg(31, 0)
+  val sm4Result = SignExt(sm4ResultTemp, XLEN)
 
   io.out := Mux(funcReg(3), sm4Result, aesResult)
 }

src/main/scala/xiangshan/backend/fu/NewCSR/CSRAIA.scala

@@ -204,11 +204,11 @@ class ISelectField(final val maxValue: Int, reserved: Seq[Range]) extends CSREnu
 }
 
 object VSISelectField extends ISelectField(
-  0x1FF,
+  0xFFF,
   reserved = Seq(
     Range.inclusive(0x000, 0x02F),
     Range.inclusive(0x040, 0x06F),
-    Range.inclusive(0x100, 0x1FF),
+    Range.inclusive(0x100, 0xFFF),
   ),
 )
 
@@ -221,15 +221,16 @@ object MISelectField extends ISelectField(
 )
 
 object SISelectField extends ISelectField(
-  maxValue = 0xFF,
+  maxValue = 0xFFF,
   reserved = Seq(
-    Range.inclusive(0x00, 0x2F),
-    Range.inclusive(0x40, 0x6F),
+    Range.inclusive(0x000, 0x02F),
+    Range.inclusive(0x040, 0x06F),
+    Range.inclusive(0x100, 0xFFF),
   ),
 )
 
 class VSISelectBundle extends CSRBundle {
-  val ALL = VSISelectField(log2Up(0x1FF), 0, null).withReset(0.U)
+  val ALL = VSISelectField(log2Up(0xFFF), 0, null).withReset(0.U)
 }
 
 class MISelectBundle extends CSRBundle {
@@ -237,7 +238,7 @@ class MISelectBundle extends CSRBundle {
 }
 
 class SISelectBundle extends CSRBundle {
-  val ALL = SISelectField(log2Up(0xFF), 0, null).withReset(0.U)
+  val ALL = SISelectField(log2Up(0xFFF), 0, null).withReset(0.U)
 }
 
 class TopIBundle extends CSRBundle {

src/main/scala/xiangshan/backend/fu/util/CryptoUtils.scala

@@ -61,25 +61,27 @@ object ROR64 {
 
 // AES forward shift rows
 object ForwardShiftRows {
-  def apply(src1: Seq[UInt], src2: Seq[UInt]): Seq[UInt] = {
-    VecInit(Seq(src1(0), src1(5), src2(2), src2(7),
-                src1(4), src2(1), src2(6), src1(3)))
+  def apply(src1: Vec[UInt], src2: Vec[UInt]): Vec[UInt] = {
+    VecInit(src1(0), src1(5), src2(2), src2(7),
+            src1(4), src2(1), src2(6), src1(3))
   }
 }
 
 // AES inverse shift rows
 object InverseShiftRows {
-  def apply(src1: Seq[UInt], src2: Seq[UInt]): Seq[UInt] = {
-    VecInit(Seq(src1(0), src2(5), src2(2), src1(7),
-                src1(4), src1(1), src2(6), src2(3)))
+  def apply(src1: Vec[UInt], src2: Vec[UInt]): Vec[UInt] = {
+    VecInit(src1(0), src2(5), src2(2), src1(7),
+            src1(4), src1(1), src2(6), src2(3))
   }
 }
 
 // AES encode sbox top
 object SboxAesTop {
-  def apply(i: UInt): Seq[Bool] = {
+  def apply(i: UInt): UInt = {
+    require(i.getWidth == 8)
     val t = Wire(Vec(6, Bool()))
     val o = Wire(Vec(21, Bool()))
+
     t( 0) := i( 3) ^ i( 1)
     t( 1) := i( 6) ^ i( 5)
     t( 2) := i( 6) ^ i( 2)
@@ -107,15 +109,17 @@ object SboxAesTop {
     o(18) := o( 2) ^ o( 8)
     o(19) := o(15) ^ o(13)
     o(20) := o( 1) ^ t( 3)
-    o
+    o.asUInt
   }
 }
 
 // AES decode sbox top
 object SboxIaesTop {
-  def apply(i: UInt): Seq[Bool] = {
+  def apply(i: UInt): UInt = {
+    require(i.getWidth == 8)
     val t = Wire(Vec(5, Bool()))
     val o = Wire(Vec(21, Bool()))
+
     t( 0) := i( 1) ^  i( 0)
     t( 1) := i( 6) ^  i( 1)
     t( 2) := i( 5) ^ ~i( 2)
@@ -142,15 +146,17 @@ object SboxIaesTop {
     o(18) := i( 3) ^ ~i( 0)
     o(19) := i( 5) ^ ~o( 1)
     o(20) := o( 1) ^  t( 3)
-    o
+    o.asUInt
   }
 }
 
 // SM4 encode/decode sbox top
 object SboxSm4Top {
-  def apply(i: UInt): Seq[Bool] = {
+  def apply(i: UInt): UInt = {
+    require(i.getWidth == 8)
     val t = Wire(Vec(7, Bool()))
     val o = Wire(Vec(21, Bool()))
+
     t( 0) := i(3) ^  i( 4)
     t( 1) := i(2) ^  i( 7)
     t( 2) := i(7) ^  o(18)
@@ -179,15 +185,17 @@ object SboxSm4Top {
     o(18) := i(2) ^  i( 6)
     o(19) := i(5) ^ ~o(14)
     o(20) := i(0) ^  t( 1)
-    o
+    o.asUInt
   }
 }
 
 // Sbox middle part for AES, AES^-1, SM4
 object SboxInv {
-  def apply(i: Seq[Bool]): Seq[Bool] = {
+  def apply(i: UInt): UInt = {
+    require(i.getWidth == 21)
     val t = Wire(Vec(46, Bool()))
     val o = Wire(Vec(18, Bool()))
+
     t( 0) := i( 3) ^ i(12)
     t( 1) := i( 9) & i( 5)
     t( 2) := i(17) & i( 6)
@@ -252,15 +260,17 @@ object SboxInv {
     o(15) := t(40) & i( 6)
     o(16) := t(39) & i( 0)
     o(17) := t(43) & i(12)
-    o
+    o.asUInt
   }
 }
 
 // AES encode sbox out
 object SboxAesOut {
-  def apply(i: Seq[Bool]): UInt = {
+  def apply(i: UInt): UInt = {
+    require(i.getWidth == 18)
     val t = Wire(Vec(30, Bool()))
     val o = Wire(Vec(8, Bool()))
+
     t( 0) := i(11) ^  i(12)
     t( 1) := i( 0) ^  i( 6)
     t( 2) := i(14) ^  i(16)
@@ -305,9 +315,11 @@ object SboxAesOut {
 
 // AES decode sbox out
 object SboxIaesOut {
-  def apply(i: Seq[Bool]): UInt = {
+  def apply(i: UInt): UInt = {
+    require(i.getWidth == 18)
     val t = Wire(Vec(30, Bool()))
     val o = Wire(Vec(8, Bool()))
+
     t( 0) := i( 2) ^ i(11)
     t( 1) := i( 8) ^ i( 9)
     t( 2) := i( 4) ^ i(12)
@@ -352,9 +364,11 @@ object SboxIaesOut {
 
 // SM4 encode/decode sbox out
 object SboxSm4Out {
-  def apply(i: Seq[Bool]): UInt = {
+  def apply(i: UInt): UInt = {
+    require(i.getWidth == 18)
     val t = Wire(Vec(30, Bool()))
     val o = Wire(Vec(8, Bool()))
+
     t( 0) := i( 4) ^  i( 7)
     t( 1) := i(13) ^  i(15)
     t( 2) := i( 2) ^  i(16)
@@ -417,7 +431,7 @@ object SboxSm4 {
 
 // Mix Column
 object XtN {
-  def Xt2(byte: UInt): UInt = ((byte << 1) ^ Mux(byte(7), "h1b".U, 0.U))(7,0)
+  def Xt2(byte: UInt): UInt = ((byte << 1).asUInt ^ Mux(byte(7), "h1b".U, 0.U))(7,0)
 
   def apply(byte: UInt, t: UInt): UInt = {
     val byte1 = Xt2(byte)

src/main/scala/xiangshan/backend/rename/Rename.scala

@@ -206,8 +206,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
   private val inst         = Wire(Vec(RenameWidth, new XSInstBitFields))
   private val isCsr        = Wire(Vec(RenameWidth, Bool()))
   private val isCsrr       = Wire(Vec(RenameWidth, Bool()))
-  private val isWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
-  private val isBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
+  private val isNotWaitForwardCsrr = Wire(Vec(RenameWidth, Bool()))
+  private val isNotBlockBackwardCsrr = Wire(Vec(RenameWidth, Bool()))
   private val fuType       = uops.map(_.fuType)
   private val fuOpType     = uops.map(_.fuOpType)
   private val vtype        = uops.map(_.vpu.vtype)
@@ -291,9 +291,9 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
     inst(i) := uops(i).instr.asTypeOf(new XSInstBitFields)
     isCsr(i) := inst(i).OPCODE5Bit === OPCODE5Bit.SYSTEM && inst(i).FUNCT3(1, 0) =/= 0.U
     isCsrr(i) := isCsr(i) && inst(i).FUNCT3 === BitPat("b?1?") && inst(i).RS1 === 0.U
-    isWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
+    isNotWaitForwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
       inst(i).CSRIDX, true.B, CSROoORead.waitForwardInOrderCsrReadList.map(_.U -> false.B))
-    isBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
+    isNotBlockBackwardCsrr(i) := isCsrr(i) && LookupTreeDefault(
       inst(i).CSRIDX, true.B, CSROoORead.blockBackwardInOrderCsrReadList.map(_.U -> false.B))
 
     /*
@@ -303,8 +303,8 @@ class Rename(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHe
      *
      * Signal "isCsrr" contains not only "CSRR", but also other CSR instructions that do not require writing to CSR.
      */
-    uops(i).waitForward := io.in(i).bits.waitForward && !isWaitForwardCsrr(i)
-    uops(i).blockBackward := io.in(i).bits.blockBackward && !isBlockBackwardCsrr(i)
+    uops(i).waitForward := io.in(i).bits.waitForward && !isNotWaitForwardCsrr(i)
+    uops(i).blockBackward := io.in(i).bits.blockBackward && !isNotBlockBackwardCsrr(i)
 
     // update cf according to ssit result
     uops(i).storeSetHit := io.ssit(i).valid

src/main/scala/xiangshan/cache/dcache/mainpipe/MainPipe.scala

@@ -378,11 +378,9 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
   val s1_need_replacement = s1_req.miss && !s1_tag_match
   val s1_need_eviction = s1_req.miss && !s1_tag_match && s1_repl_coh.state =/= ClientStates.Nothing
 
-  val s1_way_en = Mux(
-    RegEnable(io.pseudo_error.valid, false.B, s0_fire),
-    Mux(ParallelORR(s1_real_tag_match_way), s1_real_tag_match_way, s1_repl_way_en),
-    Mux(s1_need_replacement, s1_repl_way_en, s1_real_tag_match_way)
-  )
+  val s1_no_error_way_en = Mux(s1_need_replacement, s1_repl_way_en, s1_real_tag_match_way)
+  val s1_error_way_en = Mux(ParallelORR(s1_real_tag_match_way), s1_real_tag_match_way, s1_repl_way_en)
+  val s1_way_en = Mux(io.pseudo_error.valid, s1_error_way_en, s1_no_error_way_en)
   assert(!RegNext(s1_fire && PopCount(s1_way_en) > 1.U))
 
   val s1_tag = s1_hit_tag
@@ -413,7 +411,6 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
   val s2_need_tag = RegEnable(s1_need_tag, s1_fire)
   val s2_idx = get_idx(s2_req.vaddr)
 
-
   val s2_way_en = RegEnable(s1_way_en, s1_fire)
   val s2_tag = Mux(s2_need_replacement, s2_repl_tag, RegEnable(s1_tag, s1_fire))
   val s2_coh = Mux(s2_need_replacement, s2_repl_coh, RegEnable(s1_coh, s1_fire))
@@ -427,8 +424,10 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
 
   val s2_hit = s2_tag_match && s2_has_permission
   val s2_sc = s2_req.cmd === M_XSC
+  val s2_lr = s2_req.cmd === M_XLR
   val s2_amo_hit = s2_hit && !s2_req.probe && !s2_req.miss && s2_req.isAMO
   val s2_store_hit = s2_hit && !s2_req.probe && !s2_req.miss && s2_req.isStore
+  val s2_should_not_report_ecc_error = !s2_req.miss && (s2_req.isAMO && !s2_lr || s2_req.isStore)
 
   if(EnableTagEcc) {
     s2_tag_error := s2_tag_errors.orR && s2_need_tag
@@ -978,7 +977,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
     s.s1.bits.way_en := s1_way_en
     s.s2.valid := s2_valid && !RegEnable(s1_req.replace, s1_fire)
     s.s2.bits.set := RegEnable(get_idx(s1_req.vaddr), s1_fire)
-    s.s2.bits.way_en := RegEnable(s1_way_en, s1_fire)
+    s.s2.bits.way_en := s2_way_en
     s.s3.valid := s3_valid && !RegEnable(s2_req.replace, s2_fire_to_s3)
     s.s3.bits.set := RegEnable(get_idx(s2_req.vaddr), s2_fire_to_s3)
     s.s3.bits.way_en := RegEnable(s2_way_en, s2_fire_to_s3)
@@ -995,7 +994,7 @@ class MainPipe(implicit p: Parameters) extends DCacheModule with HasPerfEvents w
   // report error to beu and csr, 1 cycle after read data resp
   io.error := 0.U.asTypeOf(ValidIO(new L1CacheErrorInfo))
   // report error, update error csr
-  io.error.valid := s3_error && GatedValidRegNext(s2_fire && !(s2_req.isAMO || s2_req.isStore))
+  io.error.valid := s3_error && GatedValidRegNext(s2_fire && !s2_should_not_report_ecc_error)
   // only tag_error and data_error will be reported to beu
   // l2_error should not be reported (l2 will report that)
   io.error.bits.report_to_beu := (s3_tag_error || s3_data_error) && RegNext(s2_fire)

src/main/scala/xiangshan/mem/lsqueue/LoadQueue.scala

@@ -300,7 +300,7 @@ class LoadQueue(implicit p: Parameters) extends XSModule
   for ((buff, w) <- uncacheBuffer.io.req.zipWithIndex) {
     // from load_s3
     val ldinBits = io.ldu.ldin(w).bits
-    buff.valid := io.ldu.ldin(w).valid && (ldinBits.nc || ldinBits.mmio) && !ldinBits.rep_info.need_rep && !ldinBits.nc_with_data
+    buff.valid := io.ldu.ldin(w).valid && !ldinBits.nc_with_data
     buff.bits := ldinBits
   }
 

src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala

@@ -939,6 +939,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   val cboZeroFlushSb     = GatedRegNext(cboZeroToSb)
 
   val cboZeroUop         = RegEnable(PriorityMux(isCboZeroToSbVec, deqPtrExt.map(x=>uop(x.value))), cboZeroToSb)
+  val cboZeroSqIdx       = RegEnable(PriorityMux(isCboZeroToSbVec, deqPtrExt), cboZeroToSb)
   val cboZeroValid       = RegInit(false.B)
   val cboZeroWaitFlushSb = RegInit(false.B)
 
@@ -1014,6 +1015,7 @@ class StoreQueue(implicit p: Parameters) extends XSModule
   // cbo Zero writeback to ROB
   io.cboZeroStout.valid                := cboZeroValid && !cboZeroWaitFlushSb
   io.cboZeroStout.bits.uop             := cboZeroUop
+  io.cboZeroStout.bits.uop.sqIdx       := cboZeroSqIdx
   io.cboZeroStout.bits.data            := DontCare
   io.cboZeroStout.bits.isFromLoadUnit  := DontCare
   io.cboZeroStout.bits.debug.isMMIO    := false.B

src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala

@@ -114,7 +114,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule
   val s0_rob_idx      = Mux(s0_use_non_prf_flow, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx))
   val s0_pc           = Mux(s0_use_non_prf_flow, s0_uop.pc, 0.U)
   val s0_instr_type   = Mux(s0_use_non_prf_flow, STORE_SOURCE.U, DCACHE_PREFETCH_SOURCE.U)
-  val s0_wlineflag    = Mux(s0_use_flow_rs, s0_uop.fuOpType === LSUOpType.cbo_zero, false.B)
+  val s0_wlineflag    = Mux(s0_use_flow_rs, LSUOpType.isCboAll(s0_uop.fuOpType), false.B)
   val s0_out          = Wire(new LsPipelineBundle)
   val s0_kill         = s0_uop.robIdx.needFlush(io.redirect)
   val s0_can_go       = s1_ready