360 lines
10 KiB
Makefile
360 lines
10 KiB
Makefile
#***************************************************************************************
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# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
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# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
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# Copyright (c) 2020-2021 Peng Cheng Laboratory
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#
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# XiangShan is licensed under Mulan PSL v2.
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# You can use this software according to the terms and conditions of the Mulan PSL v2.
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# You may obtain a copy of Mulan PSL v2 at:
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# http://license.coscl.org.cn/MulanPSL2
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#
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# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
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# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
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# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
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#
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# See the Mulan PSL v2 for more details.
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#***************************************************************************************
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BUILD_DIR = ./build
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RTL_DIR = $(BUILD_DIR)/rtl
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# import docker support
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include scripts/Makefile.docker
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# import pdb support
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include scripts/Makefile.pdb
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# if XSTopPrefix is specified in yaml, use it.
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ifneq ($(YAML_CONFIG),)
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HAS_PREFIX_FROM_YAML = $(shell grep 'XSTopPrefix *:' $(YAML_CONFIG))
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ifneq ($(HAS_PREFIX_FROM_YAML),)
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XSTOP_PREFIX_YAML = $(shell grep 'XSTopPrefix *:' $(YAML_CONFIG) | sed 's/XSTopPrefix *: *//' | tr -d \"\')
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override XSTOP_PREFIX = $(XSTOP_PREFIX_YAML)
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endif
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endif
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TOP = $(XSTOP_PREFIX)XSTop
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SIM_TOP = SimTop
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FPGATOP = top.TopMain
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SIMTOP = top.SimTop
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RTL_SUFFIX ?= sv
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TOP_V = $(RTL_DIR)/$(TOP).$(RTL_SUFFIX)
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SIM_TOP_V = $(RTL_DIR)/$(SIM_TOP).$(RTL_SUFFIX)
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JAR = $(BUILD_DIR)/xsgen.jar
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SCALA_FILE = $(shell find ./src/main/scala -name '*.scala')
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TEST_FILE = $(shell find ./src/test/scala -name '*.scala')
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MEM_GEN = ./scripts/vlsi_mem_gen
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MEM_GEN_SEP = ./scripts/gen_sep_mem.sh
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CONFIG ?= DefaultConfig
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NUM_CORES ?= 1
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ISSUE ?= E.b
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CHISEL_TARGET ?= systemverilog
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SUPPORT_CHI_ISSUE = B C E.b
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ifeq ($(findstring $(ISSUE), $(SUPPORT_CHI_ISSUE)),)
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$(error "Unsupported CHI issue: $(ISSUE)")
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endif
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ifneq ($(shell echo "$(MAKECMDGOALS)" | grep ' '),)
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$(error At most one target can be specified)
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endif
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ifeq ($(MAKECMDGOALS),)
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GOALS = verilog
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else
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GOALS = $(MAKECMDGOALS)
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endif
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# JVM memory configurations
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JVM_XMX ?= 40G
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JVM_XSS ?= 256m
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# mill arguments for build.sc
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MILL_BUILD_ARGS = -Djvm-xmx=$(JVM_XMX) -Djvm-xss=$(JVM_XSS)
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# common chisel args
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FPGA_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(TOP).$(RTL_SUFFIX).conf"
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SIM_MEM_ARGS = --firtool-opt "--repl-seq-mem --repl-seq-mem-file=$(SIM_TOP).$(RTL_SUFFIX).conf"
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MFC_ARGS = --target $(CHISEL_TARGET) \
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--firtool-opt "-O=release --disable-annotation-unknown --lowering-options=explicitBitcast,disallowLocalVariables,disallowPortDeclSharing,locationInfoStyle=none"
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ifeq ($(CHISEL_TARGET),systemverilog)
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MFC_ARGS += --split-verilog --dump-fir
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endif
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ifneq ($(FIRTOOL),)
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MFC_ARGS += --firtool-binary-path $(abspath $(FIRTOOL))
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endif
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# prefix of XSTop or XSNoCTop
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ifneq ($(XSTOP_PREFIX),)
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COMMON_EXTRA_ARGS += --xstop-prefix $(XSTOP_PREFIX)
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endif
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# IMSIC bus type (AXI, TL or NONE)
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ifneq ($(IMSIC_BUS_TYPE),)
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COMMON_EXTRA_ARGS += --imsic-bus-type $(IMSIC_BUS_TYPE)
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endif
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# enable or disable dfx manually
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ifeq ($(DFX),1)
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COMMON_EXTRA_ARGS += --dfx true
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else
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ifeq ($(DFX),0)
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COMMON_EXTRA_ARGS += --dfx false
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endif
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endif
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# enable or disable sram ctl maunally
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ifeq ($(SRAM_WITH_CTL),1)
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COMMON_EXTRA_ARGS += --sram-with-ctl
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endif
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# enable non-secure access or not
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# CHI requests are secure as default by now
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ifeq ($(ENABLE_NS),1)
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COMMON_EXTRA_ARGS += --enable-ns
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endif
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# CHI physical address width
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ifneq ($(CHI_ADDR_WIDTH),)
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COMMON_EXTRA_ARGS += --chi-addr-width $(CHI_ADDR_WIDTH)
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endif
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# L2 cache size in KB
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ifneq ($(L2_CACHE_SIZE),)
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COMMON_EXTRA_ARGS += --l2-cache-size $(L2_CACHE_SIZE)
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endif
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# L3 cache size in KB
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ifneq ($(L3_CACHE_SIZE),)
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COMMON_EXTRA_ARGS += --l3-cache-size $(L3_CACHE_SIZE)
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endif
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# hart id bits
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ifneq ($(HART_ID_BITS),)
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COMMON_EXTRA_ARGS += --hartidbits $(HART_ID_BITS)
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endif
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# disable xmr
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ifeq ($(DISABLE_XMR),1)
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COMMON_EXTRA_ARGS += --disable-xmr
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endif
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# configuration from yaml file
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ifneq ($(YAML_CONFIG),)
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COMMON_EXTRA_ARGS += --yaml-config $(YAML_CONFIG)
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endif
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# public args sumup
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RELEASE_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
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DEBUG_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
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override PLDM_ARGS += $(MFC_ARGS) $(COMMON_EXTRA_ARGS)
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# co-simulation with DRAMsim3
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ifeq ($(WITH_DRAMSIM3),1)
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ifndef DRAMSIM3_HOME
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$(error DRAMSIM3_HOME is not set)
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endif
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override SIM_ARGS += --with-dramsim3
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endif
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# run emu with chisel-db
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ifeq ($(WITH_CHISELDB),1)
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override SIM_ARGS += --with-chiseldb
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endif
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# run emu with chisel-db
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ifeq ($(WITH_ROLLINGDB),1)
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override SIM_ARGS += --with-rollingdb
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endif
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# enable ResetGen
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ifeq ($(WITH_RESETGEN),1)
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override SIM_ARGS += --reset-gen
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endif
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# run with disable all perf
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ifeq ($(DISABLE_PERF),1)
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override SIM_ARGS += --disable-perf
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endif
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# run with disable all db
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ifeq ($(DISABLE_ALWAYSDB),1)
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override SIM_ARGS += --disable-alwaysdb
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endif
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# dynamic switch CONSTANTIN
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ifeq ($(WITH_CONSTANTIN),1)
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override SIM_ARGS += --with-constantin
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endif
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# emu for the release version
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RELEASE_ARGS += --fpga-platform --disable-all --remove-assert --reset-gen --firtool-opt --ignore-read-enable-mem
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DEBUG_ARGS += --enable-difftest
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override PLDM_ARGS += --enable-difftest
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ifeq ($(RELEASE),1)
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override SIM_ARGS += $(RELEASE_ARGS)
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else ifeq ($(PLDM),1)
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override SIM_ARGS += $(PLDM_ARGS)
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else
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override SIM_ARGS += $(DEBUG_ARGS)
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endif
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# Coverage support
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ifneq ($(FIRRTL_COVER),)
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comma := ,
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splitcomma = $(foreach w,$(subst $(comma), ,$1),$(if $(strip $w),$w))
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override SIM_ARGS += $(foreach c,$(call splitcomma,$(FIRRTL_COVER)),--extract-$(c)-cover)
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endif
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# use RELEASE_ARGS for TopMain by default
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ifeq ($(PLDM), 1)
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TOPMAIN_ARGS += $(PLDM_ARGS)
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else
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TOPMAIN_ARGS += $(RELEASE_ARGS)
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endif
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TIMELOG = $(BUILD_DIR)/time.log
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TIME_CMD = time -avp -o $(TIMELOG)
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ifeq ($(PLDM),1)
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SED_IFNDEF = `ifndef SYNTHESIS // src/main/scala/device/RocketDebugWrapper.scala
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SED_ENDIF = `endif // not def SYNTHESIS
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endif
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.DEFAULT_GOAL = verilog
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help:
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mill -i xiangshan.runMain $(FPGATOP) --help
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version:
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mill -i xiangshan.runMain $(FPGATOP) --version
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jar:
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mill -i xiangshan.assembly
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$(JAR): FORCE
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mill -i xiangshan.test.assembly
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@mkdir -p $(@D); \
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JAR_REF=$(shell mill -i show xiangshan.test.assembly 2> /dev/null); \
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[ ! -z $${JAR_REF} ] && echo $${JAR_REF} | sed 's/"//g' | awk -F: '{print $$4}' \
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| xargs -I{} cp {} $@
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test-jar: $(call docker-deps,$(JAR))
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comp:
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mill -i xiangshan.compile
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mill -i xiangshan.test.compile
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$(TOP_V): $(SCALA_FILE)
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mkdir -p $(@D)
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$(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.runMain $(FPGATOP) \
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--target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(FPGA_MEM_ARGS) \
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--num-cores $(NUM_CORES) $(TOPMAIN_ARGS)
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ifeq ($(CHISEL_TARGET),systemverilog)
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$(MEM_GEN_SEP) "$(MEM_GEN)" "$@.conf" "$(@D)"
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@{ git log -n 1; git diff; } | sed 's/^/\/\// ' > $(dir $@).__diff__
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@cat $(dir $@).__diff__ $@ > $(dir $@).__out__ && mv $(dir $@).__out__ $@
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endif
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verilog: $(call docker-deps,$(TOP_V))
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$(SIM_TOP_V): $(SCALA_FILE) $(TEST_FILE)
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mkdir -p $(@D)
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@echo -e "\n[mill] Generating Verilog files..." > $(TIMELOG)
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@date -R | tee -a $(TIMELOG)
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$(TIME_CMD) mill -i $(MILL_BUILD_ARGS) xiangshan.test.runMain $(SIMTOP) \
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--target-dir $(@D) --config $(CONFIG) --issue $(ISSUE) $(SIM_MEM_ARGS) \
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--num-cores $(NUM_CORES) $(SIM_ARGS) --full-stacktrace
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ifeq ($(CHISEL_TARGET),systemverilog)
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$(MEM_GEN_SEP) "$(MEM_GEN)" "$@.conf" "$(@D)"
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@{ git log -n 1; git diff; } | sed 's/^/\/\// ' > $(dir $@).__diff__
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@cat $(dir $@).__diff__ $@ > $(dir $@).__out__ && mv $(dir $@).__out__ $@
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ifeq ($(PLDM),1)
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sed -i -e 's/$$fatal/$$finish/g' $(RTL_DIR)/*.$(RTL_SUFFIX)
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sed -i -e '/sed/! { \|$(SED_IFNDEF)|, \|$(SED_ENDIF)| { \|$(SED_IFNDEF)|d; \|$(SED_ENDIF)|d; } }' $(RTL_DIR)/*.$(RTL_SUFFIX)
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else
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ifeq ($(ENABLE_XPROP),1)
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sed -i -e "s/\$$fatal/assert(1\'b0)/g" $(RTL_DIR)/*.$(RTL_SUFFIX)
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else
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sed -i -e 's/$$fatal/xs_assert_v2(`__FILE__, `__LINE__)/g' $(RTL_DIR)/*.$(RTL_SUFFIX)
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endif
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endif
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sed -i -e "s/\$$error(/\$$fwrite(32\'h80000002, /g" $(RTL_DIR)/*.$(RTL_SUFFIX)
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endif
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sim-verilog: $(call docker-deps,$(SIM_TOP_V))
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clean:
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$(MAKE) -C ./difftest clean
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rm -rf $(BUILD_DIR)
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init:
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git submodule update --init
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cd rocket-chip && git submodule update --init cde hardfloat
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cd openLLC && git submodule update --init openNCB
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bump:
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git submodule foreach "git fetch origin&&git checkout master&&git reset --hard origin/master"
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deps:
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mill -i __.prepareOffline
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mill -i xiangshan.resolveFirtoolDeps
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bsp:
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mill -i mill.bsp.BSP/install
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idea:
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mill -i mill.idea.GenIdea/idea
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check-format:
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mill xiangshan.checkFormat
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reformat:
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mill xiangshan.reformat
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# verilator simulation
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emu-mk: sim-verilog
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$(MAKE) -C ./difftest emu-mk SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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emu: $(call docker-deps,emu-mk)
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$(MAKE) -C ./difftest emu SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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emu-run: emu
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$(MAKE) -C ./difftest emu-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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# vcs simulation
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simv: sim-verilog
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$(MAKE) -C ./difftest simv SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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simv-run:
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$(MAKE) -C ./difftest simv-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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# galaxsim simulation
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xsim: sim-verilog
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$(MAKE) -C ./difftest xsim SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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xsim-run:
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$(MAKE) -C ./difftest xsim-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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# palladium simulation
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pldm-build: sim-verilog
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$(MAKE) -C ./difftest pldm-build SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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pldm-run:
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$(MAKE) -C ./difftest pldm-run SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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pldm-debug:
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$(MAKE) -C ./difftest pldm-debug SIM_TOP=SimTop DESIGN_DIR=$(NOOP_HOME) NUM_CORES=$(NUM_CORES) RTL_SUFFIX=$(RTL_SUFFIX)
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include Makefile.test
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include src/main/scala/device/standalone/standalone_device.mk
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.PHONY: FORCE verilog sim-verilog emu clean help init bump bsp $(REF_SO)
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